Lines Matching refs:iobase
286 static void SetMaxRxPacketSize(__u16 iobase, __u16 size) in SetMaxRxPacketSize() argument
292 WriteReg(iobase, I_CF_L_2, low); in SetMaxRxPacketSize()
293 WriteReg(iobase, I_CF_H_2, high); in SetMaxRxPacketSize()
301 static void SetFIFO(__u16 iobase, __u16 value) in SetFIFO() argument
305 WriteRegBit(iobase, 0x11, 0, 0); in SetFIFO()
306 WriteRegBit(iobase, 0x11, 7, 1); in SetFIFO()
309 WriteRegBit(iobase, 0x11, 0, 0); in SetFIFO()
310 WriteRegBit(iobase, 0x11, 7, 0); in SetFIFO()
313 WriteRegBit(iobase, 0x11, 0, 1); in SetFIFO()
314 WriteRegBit(iobase, 0x11, 7, 0); in SetFIFO()
317 WriteRegBit(iobase, 0x11, 0, 0); in SetFIFO()
318 WriteRegBit(iobase, 0x11, 7, 0); in SetFIFO()
412 static void SetTimer(__u16 iobase, __u8 count) in SetTimer() argument
414 EnTimerInt(iobase, OFF); in SetTimer()
415 WriteReg(iobase, TIMER, count); in SetTimer()
416 EnTimerInt(iobase, ON); in SetTimer()
420 static void SetSendByte(__u16 iobase, __u32 count) in SetSendByte() argument
427 WriteReg(iobase, TX_C_L, low); in SetSendByte()
428 WriteReg(iobase, TX_C_H, high); in SetSendByte()
432 static void ResetChip(__u16 iobase, __u8 type) in ResetChip() argument
437 WriteReg(iobase, RESET, type); in ResetChip()
440 static int CkRxRecv(__u16 iobase, struct via_ircc_cb *self) in CkRxRecv() argument
445 low = ReadReg(iobase, RX_C_L); in CkRxRecv()
446 high = ReadReg(iobase, RX_C_H); in CkRxRecv()
450 low = ReadReg(iobase, RX_C_L); in CkRxRecv()
451 high = ReadReg(iobase, RX_C_H); in CkRxRecv()
461 static __u16 RxCurCount(__u16 iobase, struct via_ircc_cb * self) in RxCurCount() argument
466 low = ReadReg(iobase, RX_P_L); in RxCurCount()
467 high = ReadReg(iobase, RX_P_H); in RxCurCount()
477 static __u16 GetRecvByte(__u16 iobase, struct via_ircc_cb * self) in GetRecvByte() argument
482 low = ReadReg(iobase, RX_P_L); in GetRecvByte()
483 high = ReadReg(iobase, RX_P_H); in GetRecvByte()
534 static void ActClk(__u16 iobase, __u8 value) in ActClk() argument
537 bTmp = ReadReg(iobase, 0x34); in ActClk()
539 WriteReg(iobase, 0x34, bTmp | Clk_bit); in ActClk()
541 WriteReg(iobase, 0x34, bTmp & ~Clk_bit); in ActClk()
544 static void ClkTx(__u16 iobase, __u8 Clk, __u8 Tx) in ClkTx() argument
548 bTmp = ReadReg(iobase, 0x34); in ClkTx()
555 WriteReg(iobase, 0x34, bTmp); in ClkTx()
563 WriteReg(iobase, 0x34, bTmp); in ClkTx()
566 static void Wr_Byte(__u16 iobase, __u8 data) in Wr_Byte() argument
572 ClkTx(iobase, 0, 1); in Wr_Byte()
575 ActClk(iobase, 1); in Wr_Byte()
581 ClkTx(iobase, 0, 1); //bit data = 1; in Wr_Byte()
583 ClkTx(iobase, 0, 0); //bit data = 1; in Wr_Byte()
587 ActClk(iobase, 1); //clk hi in Wr_Byte()
592 static __u8 Rd_Indx(__u16 iobase, __u8 addr, __u8 index) in Rd_Indx() argument
598 ClkTx(iobase, 0, 0); in Rd_Indx()
600 ActClk(iobase, 1); in Rd_Indx()
602 Wr_Byte(iobase, bTmp); in Rd_Indx()
604 ClkTx(iobase, 0, 0); in Rd_Indx()
607 ActClk(iobase, 1); in Rd_Indx()
609 ActClk(iobase, 0); in Rd_Indx()
611 ClkTx(iobase, 0, 1); in Rd_Indx()
613 bTmp = ReadReg(iobase, 0x34); in Rd_Indx()
619 ActClk(iobase, 1); in Rd_Indx()
621 ActClk(iobase, 0); in Rd_Indx()
622 bTmp = ReadReg(iobase, 0x34); in Rd_Indx()
632 ActClk(iobase, 1); in Rd_Indx()
634 ActClk(iobase, 0); in Rd_Indx()
637 bTmp = ReadReg(iobase, 0x34); in Rd_Indx()
640 ActClk(iobase, 1); in Rd_Indx()
642 ActClk(iobase, 0); in Rd_Indx()
645 ClkTx(iobase, 0, 0); in Rd_Indx()
648 ActClk(iobase, 1); in Rd_Indx()
650 ActClk(iobase, 0); in Rd_Indx()
656 static void Wr_Indx(__u16 iobase, __u8 addr, __u8 index, __u8 data) in Wr_Indx() argument
661 ClkTx(iobase, 0, 0); in Wr_Indx()
663 ActClk(iobase, 1); in Wr_Indx()
666 Wr_Byte(iobase, bTmp); in Wr_Indx()
667 Wr_Byte(iobase, data); in Wr_Indx()
669 ClkTx(iobase, 0, 0); in Wr_Indx()
671 ActClk(iobase, 1); in Wr_Indx()
674 ActClk(iobase, 0); in Wr_Indx()
677 static void ResetDongle(__u16 iobase) in ResetDongle() argument
680 ClkTx(iobase, 0, 0); in ResetDongle()
683 ActClk(iobase, 1); in ResetDongle()
685 ActClk(iobase, 0); in ResetDongle()
688 ActClk(iobase, 0); in ResetDongle()
691 static void SetSITmode(__u16 iobase) in SetSITmode() argument
698 bTmp = ReadReg(iobase, 0x35); in SetSITmode()
699 WriteReg(iobase, 0x35, bTmp | 0x40); // Driver ITMOFF in SetSITmode()
700 WriteReg(iobase, 0x28, bTmp | 0x80); // enable All interrupt in SetSITmode()
703 static void SI_SetMode(__u16 iobase, int mode) in SI_SetMode() argument
709 SetSITmode(iobase); in SI_SetMode()
710 ResetDongle(iobase); in SI_SetMode()
712 Wr_Indx(iobase, 0x40, 0x0, 0x17); //RX ,APEN enable,Normal power in SI_SetMode()
713 Wr_Indx(iobase, 0x40, 0x1, mode); //Set Mode in SI_SetMode()
714 Wr_Indx(iobase, 0x40, 0x2, 0xff); //Set power to FIR VFIR > 1m in SI_SetMode()
715 bTmp = Rd_Indx(iobase, 0x40, 1); in SI_SetMode()
718 static void InitCard(__u16 iobase) in InitCard() argument
720 ResetChip(iobase, 5); in InitCard()
721 WriteReg(iobase, I_ST_CT_0, 0x00); // open CHIP on in InitCard()
722 SetSIRBOF(iobase, 0xc0); // hardware default value in InitCard()
723 SetSIREOF(iobase, 0xc1); in InitCard()
726 static void CommonInit(__u16 iobase) in CommonInit() argument
729 SwapDMA(iobase, OFF); in CommonInit()
730 SetMaxRxPacketSize(iobase, 0x0fff); //set to max:4095 in CommonInit()
731 EnRXFIFOReadyInt(iobase, OFF); in CommonInit()
732 EnRXFIFOHalfLevelInt(iobase, OFF); in CommonInit()
733 EnTXFIFOHalfLevelInt(iobase, OFF); in CommonInit()
734 EnTXFIFOUnderrunEOMInt(iobase, ON); in CommonInit()
736 InvertTX(iobase, OFF); in CommonInit()
737 InvertRX(iobase, OFF); in CommonInit()
739 if (IsSIROn(iobase)) { in CommonInit()
740 SIRFilter(iobase, ON); in CommonInit()
741 SIRRecvAny(iobase, ON); in CommonInit()
743 SIRFilter(iobase, OFF); in CommonInit()
744 SIRRecvAny(iobase, OFF); in CommonInit()
746 EnRXSpecInt(iobase, ON); in CommonInit()
747 WriteReg(iobase, I_ST_CT_0, 0x80); in CommonInit()
748 EnableDMA(iobase, ON); in CommonInit()
751 static void SetBaudRate(__u16 iobase, __u32 rate) in SetBaudRate() argument
755 if (IsSIROn(iobase)) { in SetBaudRate()
778 } else if (IsMIROn(iobase)) { in SetBaudRate()
780 } else if (IsFIROn(iobase)) { in SetBaudRate()
783 temp = (ReadReg(iobase, I_CF_H_1) & 0x03); in SetBaudRate()
785 WriteReg(iobase, I_CF_H_1, temp); in SetBaudRate()
788 static void SetPulseWidth(__u16 iobase, __u8 width) in SetPulseWidth() argument
792 temp = (ReadReg(iobase, I_CF_L_1) & 0x1f); in SetPulseWidth()
793 temp1 = (ReadReg(iobase, I_CF_H_1) & 0xfc); in SetPulseWidth()
798 WriteReg(iobase, I_CF_L_1, temp); in SetPulseWidth()
799 WriteReg(iobase, I_CF_H_1, temp1); in SetPulseWidth()
802 static void SetSendPreambleCount(__u16 iobase, __u8 count) in SetSendPreambleCount() argument
806 temp = ReadReg(iobase, I_CF_L_1) & 0xe0; in SetSendPreambleCount()
808 WriteReg(iobase, I_CF_L_1, temp); in SetSendPreambleCount()