194 	int tmp_mask;  in ar9002_hw_spur_mitigate()  local
334 	tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)  in ar9002_hw_spur_mitigate()
342 	REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);  in ar9002_hw_spur_mitigate()
343 	REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);  in ar9002_hw_spur_mitigate()
345 	tmp_mask = (mask_m[31] << 28)  in ar9002_hw_spur_mitigate()
353 	REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);  in ar9002_hw_spur_mitigate()
354 	REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);  in ar9002_hw_spur_mitigate()
356 	tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)  in ar9002_hw_spur_mitigate()
364 	REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);  in ar9002_hw_spur_mitigate()
365 	REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);  in ar9002_hw_spur_mitigate()
367 	tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)  in ar9002_hw_spur_mitigate()
375 	REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);  in ar9002_hw_spur_mitigate()
376 	REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);  in ar9002_hw_spur_mitigate()
378 	tmp_mask = (mask_p[15] << 28)  in ar9002_hw_spur_mitigate()
386 	REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);  in ar9002_hw_spur_mitigate()
387 	REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);  in ar9002_hw_spur_mitigate()
389 	tmp_mask = (mask_p[30] << 28)  in ar9002_hw_spur_mitigate()
397 	REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);  in ar9002_hw_spur_mitigate()
398 	REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);  in ar9002_hw_spur_mitigate()
400 	tmp_mask = (mask_p[45] << 28)  in ar9002_hw_spur_mitigate()
408 	REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);  in ar9002_hw_spur_mitigate()
409 	REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);  in ar9002_hw_spur_mitigate()
411 	tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)  in ar9002_hw_spur_mitigate()
419 	REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);  in ar9002_hw_spur_mitigate()
420 	REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);  in ar9002_hw_spur_mitigate()