1269 	u32 regval;  in ar9003_hw_antdiv_comb_conf_get()  local
1271 	regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);  in ar9003_hw_antdiv_comb_conf_get()
1272 	antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>  in ar9003_hw_antdiv_comb_conf_get()
1274 	antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>  in ar9003_hw_antdiv_comb_conf_get()
1276 	antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>  in ar9003_hw_antdiv_comb_conf_get()
1297 	u32 regval;  in ar9003_hw_antdiv_comb_conf_set()  local
1299 	regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);  in ar9003_hw_antdiv_comb_conf_set()
1300 	regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |  in ar9003_hw_antdiv_comb_conf_set()
1305 	regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)  in ar9003_hw_antdiv_comb_conf_set()
1307 	regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)  in ar9003_hw_antdiv_comb_conf_set()
1309 	regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)  in ar9003_hw_antdiv_comb_conf_set()
1311 	regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)  in ar9003_hw_antdiv_comb_conf_set()
1313 	regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)  in ar9003_hw_antdiv_comb_conf_set()
1316 	REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);  in ar9003_hw_antdiv_comb_conf_set()
1323 	u32 regval;  in ar9003_hw_antctrl_shared_chain_lnadiv()  local
1331 	regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);  in ar9003_hw_antctrl_shared_chain_lnadiv()
1332 	regval &= (~AR_ANT_DIV_CTRL_ALL);  in ar9003_hw_antctrl_shared_chain_lnadiv()
1333 	regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;  in ar9003_hw_antctrl_shared_chain_lnadiv()
1334 	regval &= ~AR_PHY_ANT_DIV_LNADIV;  in ar9003_hw_antctrl_shared_chain_lnadiv()
1335 	regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;  in ar9003_hw_antctrl_shared_chain_lnadiv()
1338 		regval |= AR_ANT_DIV_ENABLE;  in ar9003_hw_antctrl_shared_chain_lnadiv()
1340 	REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);  in ar9003_hw_antctrl_shared_chain_lnadiv()
1342 	regval = REG_READ(ah, AR_PHY_CCK_DETECT);  in ar9003_hw_antctrl_shared_chain_lnadiv()
1343 	regval &= ~AR_FAST_DIV_ENABLE;  in ar9003_hw_antctrl_shared_chain_lnadiv()
1344 	regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;  in ar9003_hw_antctrl_shared_chain_lnadiv()
1347 		regval |= AR_FAST_DIV_ENABLE;  in ar9003_hw_antctrl_shared_chain_lnadiv()
1349 	REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);  in ar9003_hw_antctrl_shared_chain_lnadiv()
1367 		regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);  in ar9003_hw_antctrl_shared_chain_lnadiv()
1368 		regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |  in ar9003_hw_antctrl_shared_chain_lnadiv()
1372 		regval |= (AR_PHY_ANT_DIV_LNA1 << AR_PHY_ANT_DIV_MAIN_LNACONF_S);  in ar9003_hw_antctrl_shared_chain_lnadiv()
1373 		regval |= (AR_PHY_ANT_DIV_LNA2 << AR_PHY_ANT_DIV_ALT_LNACONF_S);  in ar9003_hw_antctrl_shared_chain_lnadiv()
1374 		REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);  in ar9003_hw_antctrl_shared_chain_lnadiv()