Lines Matching refs:r0
4356 mov r0, #CPSR_INITIAL
4357 msr CPSR_c, r0 /* This is probably unnecessary */
4360 ldr r0, =SPI_CGEN_BASE
4364 str r1, [r0]
4365 ldr r1, [r0, #28]
4367 str r1, [r0, #28]
4369 str r1, [r0, #8]
4371 ldr r0, =MRBASE
4373 strh r1, [r0, #MR1]
4374 strh r1, [r0, #MR2]
4375 strh r1, [r0, #MR3]
4376 strh r1, [r0, #MR4]
4380 mov r0, #10
4384 ldr r0, =MRBASE
4386 strh r1, [r0, #MR2]
4388 strh r1, [r0, #MR4]
4390 strh r1, [r0, #MR3]
4398 ldr r0, =NVRAM_IMAGE
4410 ldr r0, =MAC_ADDRESS_MIB
4418 adds r0, r0, r0, LSL #3 /* r0 = r0 * 9 */
4421 subs r0, r0, #1
4430 ldr r0, =SP_BASE
4431 str r1, [r0, #SP_CR] /* reset the SPI */
4433 str r1, [r0, #SP_CR] /* release SPI from reset state */
4435 str r1, [r0, #SP_MR] /* set the SPI to MASTER mode*/
4436 str r1, [r0, #SP_CR] /* enable the SPI */
4445 str r1, [r0, #SP_CSR0]
4447 str r1, [r0, #SP_CSR1]
4448 str r1, [r0, #SP_CSR2]
4449 str r1, [r0, #SP_CSR3]
4450 ldr r1, [r0, #SP_SR]
4451 ldr r0, [r0, #SP_RDR]
4457 ldr r0, [r1, #SP_RDR]
4458 mov r0, #NVRAM_CMD_RDSR
4459 str r0, [r1, #SP_TDR]
4461 ldr r0, [r1, #SP_SR]
4462 tst r0, #SP_TDRE
4465 mov r0, #SPI_8CLOCKS
4466 str r0, [r1, #SP_TDR]
4468 ldr r0, [r1, #SP_SR]
4469 tst r0, #SP_TDRE
4472 ldr r0, [r1, #SP_RDR]
4474 ldr r0, [r1, #SP_SR]
4475 tst r0, #SP_RDRF
4478 ldr r0, [r1, #SP_RDR]
4479 and r0, r0, #255
4490 mov r5, r0 /* save r0 (dest address) */
4492 mov r0, r2, LSR #5 /* SPI memories put A8 in the command field */
4493 and r0, r0, #8
4494 add r0, r0, #NVRAM_CMD_READ
4496 strb r0, [r1, #0] /* save command in NVRAM_SCRATCH[0] */
4500 tst r0, #NVRAM_SR_RDY
4502 mov r0, #20
4506 mov r0, #2 /* bytes to transfer in command */
4517 cmp r0, #0
4528 cmp r3, r0 /* r0 is # of bytes to send out (command+addr) */
4533 ldr r0, [r4, #SP_RDR]
4535 ldr r0, [r4, #SP_SR]
4536 tst r0, #SP_RDRF
4538 …ldr r0, [r4, #SP_RDR] /* what's this byte? It's the byte read while writing the TDR -- nonsense, …
4539 mov r0, #0
4553 add r0, r0, #1
4554 cmp r0, r2
4557 mov r0, #200