Lines Matching refs:BIT
73 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
76 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0)|BIT(1), 0}, \
79 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
82 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \
85 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4)|BIT(3), 0}, \
88 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
91 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0}, \
93 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*LDO normal mode*/\
95 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*SDIO Driving*/\
103 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*LDO Sleep mode*/\
106 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
109 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}, \
118 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
121 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)|BIT(4)},\
125 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, BIT(7)}, \
129 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
133 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
136 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
139 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0},
146 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \
149 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
152 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
159 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
163 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
171 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
174 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
177 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
179 PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/
186 PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/ \
189 PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/\
192 PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, \
200 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},/* 0x04[16] = 0*/ \
202 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/
209 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/
231 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
238 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
241 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)}, \
257 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
260 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0}, \
263 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0}, \
266 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
272 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0)}, \