Lines Matching refs:rtl_set_bbreg
123 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, in _rtl92c_phy_rf_serial_read()
126 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); in _rtl92c_phy_rf_serial_read()
128 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, in _rtl92c_phy_rf_serial_read()
166 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); in _rtl92c_phy_rf_serial_write()
186 rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2); in _rtl92c_phy_bb_config_1t()
187 rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022); in _rtl92c_phy_bb_config_1t()
188 rtl_set_bbreg(hw, RCCK0_AFESETTING, MASKBYTE3, 0x45); in _rtl92c_phy_bb_config_1t()
189 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23); in _rtl92c_phy_bb_config_1t()
190 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, 0x30, 0x1); in _rtl92c_phy_bb_config_1t()
191 rtl_set_bbreg(hw, 0xe74, 0x0c000000, 0x2); in _rtl92c_phy_bb_config_1t()
192 rtl_set_bbreg(hw, 0xe78, 0x0c000000, 0x2); in _rtl92c_phy_bb_config_1t()
193 rtl_set_bbreg(hw, 0xe7c, 0x0c000000, 0x2); in _rtl92c_phy_bb_config_1t()
194 rtl_set_bbreg(hw, 0xe80, 0x0c000000, 0x2); in _rtl92c_phy_bb_config_1t()
195 rtl_set_bbreg(hw, 0xe88, 0x0c000000, 0x2); in _rtl92c_phy_bb_config_1t()
867 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f); in _rtl92c_phy_path_a_iqk()
868 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f); in _rtl92c_phy_path_a_iqk()
869 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102); in _rtl92c_phy_path_a_iqk()
870 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, in _rtl92c_phy_path_a_iqk()
874 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22); in _rtl92c_phy_path_a_iqk()
875 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22); in _rtl92c_phy_path_a_iqk()
876 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102); in _rtl92c_phy_path_a_iqk()
877 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160202); in _rtl92c_phy_path_a_iqk()
880 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x001028d1); in _rtl92c_phy_path_a_iqk()
881 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); in _rtl92c_phy_path_a_iqk()
882 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92c_phy_path_a_iqk()
910 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); in _rtl92c_phy_path_b_iqk()
911 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); in _rtl92c_phy_path_b_iqk()
948 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); in _rtl92c_phy_path_a_fill_iqk_matrix()
949 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31), in _rtl92c_phy_path_a_fill_iqk_matrix()
955 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, in _rtl92c_phy_path_a_fill_iqk_matrix()
957 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, in _rtl92c_phy_path_a_fill_iqk_matrix()
959 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29), in _rtl92c_phy_path_a_fill_iqk_matrix()
964 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); in _rtl92c_phy_path_a_fill_iqk_matrix()
966 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); in _rtl92c_phy_path_a_fill_iqk_matrix()
968 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); in _rtl92c_phy_path_a_fill_iqk_matrix()
988 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a); in _rtl92c_phy_path_b_fill_iqk_matrix()
989 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27), in _rtl92c_phy_path_b_fill_iqk_matrix()
995 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, in _rtl92c_phy_path_b_fill_iqk_matrix()
997 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000, in _rtl92c_phy_path_b_fill_iqk_matrix()
999 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25), in _rtl92c_phy_path_b_fill_iqk_matrix()
1004 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); in _rtl92c_phy_path_b_fill_iqk_matrix()
1006 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); in _rtl92c_phy_path_b_fill_iqk_matrix()
1008 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg); in _rtl92c_phy_path_b_fill_iqk_matrix()
1040 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]); in _rtl92c_phy_reload_adda_registers()
1063 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0); in _rtl92c_phy_path_adda_on()
1065 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathOn); in _rtl92c_phy_path_adda_on()
1069 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathOn); in _rtl92c_phy_path_adda_on()
1088 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); in _rtl92c_phy_path_a_standby()
1089 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); in _rtl92c_phy_path_a_standby()
1090 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92c_phy_path_a_standby()
1098 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); in _rtl92c_phy_pi_mode_switch()
1099 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); in _rtl92c_phy_pi_mode_switch()
1205 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600); in _rtl92c_phy_iq_calibrate()
1206 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4); in _rtl92c_phy_iq_calibrate()
1207 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000); in _rtl92c_phy_iq_calibrate()
1209 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); in _rtl92c_phy_iq_calibrate()
1210 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000); in _rtl92c_phy_iq_calibrate()
1214 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000); in _rtl92c_phy_iq_calibrate()
1216 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x00080000); in _rtl92c_phy_iq_calibrate()
1217 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92c_phy_iq_calibrate()
1218 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); in _rtl92c_phy_iq_calibrate()
1219 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); in _rtl92c_phy_iq_calibrate()
1272 rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04); in _rtl92c_phy_iq_calibrate()
1273 rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874); in _rtl92c_phy_iq_calibrate()
1274 rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08); in _rtl92c_phy_iq_calibrate()
1275 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); in _rtl92c_phy_iq_calibrate()
1276 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3); in _rtl92c_phy_iq_calibrate()
1278 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3); in _rtl92c_phy_iq_calibrate()
1420 rtl_set_bbreg(hw, offset, MASKDWORD, in _rtl92c_phy_ap_calibrate()
1427 rtl_set_bbreg(hw, 0xb98, MASKDWORD, 0x12680000); in _rtl92c_phy_ap_calibrate()
1431 rtl_set_bbreg(hw, offset, MASKDWORD, in _rtl92c_phy_ap_calibrate()
1438 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x40000000); in _rtl92c_phy_ap_calibrate()
1442 rtl_set_bbreg(hw, offset, MASKDWORD, in _rtl92c_phy_ap_calibrate()
1448 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000); in _rtl92c_phy_ap_calibrate()
1452 rtl_set_bbreg(hw, offset, MASKDWORD, in _rtl92c_phy_ap_calibrate()
1458 rtl_set_bbreg(hw, 0xb28, MASKDWORD, 0x12680000); in _rtl92c_phy_ap_calibrate()
1459 rtl_set_bbreg(hw, 0xb98, MASKDWORD, 0x12680000); in _rtl92c_phy_ap_calibrate()
1464 rtl_set_bbreg(hw, offset, MASKDWORD, in _rtl92c_phy_ap_calibrate()
1471 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x40000000); in _rtl92c_phy_ap_calibrate()
1475 rtl_set_bbreg(hw, offset, MASKDWORD, in _rtl92c_phy_ap_calibrate()
1481 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000); in _rtl92c_phy_ap_calibrate()
1488 rtl_set_bbreg(hw, afe_reg[index], MASKDWORD, in _rtl92c_phy_ap_calibrate()
1495 rtl_set_bbreg(hw, bb_reg[index], MASKDWORD, in _rtl92c_phy_ap_calibrate()
1556 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80000000); in _rtl92c_phy_ap_calibrate()
1557 rtl_set_bbreg(hw, apk_offset[path], in _rtl92c_phy_ap_calibrate()
1568 rtl_set_bbreg(hw, apk_offset[path], in _rtl92c_phy_ap_calibrate()
1579 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000); in _rtl92c_phy_ap_calibrate()
1605 rtl_set_bbreg(hw, bb_reg[index], MASKDWORD, bb_backup[index]); in _rtl92c_phy_ap_calibrate()
1658 rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01); in _rtl92c_phy_set_rfpath_switch()
1659 rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01); in _rtl92c_phy_set_rfpath_switch()
1663 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, in _rtl92c_phy_set_rfpath_switch()
1666 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, in _rtl92c_phy_set_rfpath_switch()
1670 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x2); in _rtl92c_phy_set_rfpath_switch()
1672 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1); in _rtl92c_phy_set_rfpath_switch()