64 	rtl_write_dword(rtlpriv, REG_DBI_WDATA, value);  in rtl92de_write_dword_dbi()
311 			rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, regtoSet);  in rtl92de_set_hw_reg()
375 		rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);  in rtl92de_set_hw_reg()
455 		rtl_write_dword(rtlpriv, REG_TSFTR,  in rtl92de_set_hw_reg()
457 		rtl_write_dword(rtlpriv, REG_TSFTR + 4,  in rtl92de_set_hw_reg()
473 			rtl_write_dword(rtlpriv, REG_INT_MIG, 0xfe000fa0);  in rtl92de_set_hw_reg()
477 			rtl_write_dword(rtlpriv, REG_INT_MIG, 0);  in rtl92de_set_hw_reg()
518 	rtl_write_dword(rtlpriv, REG_LLT_INIT, value);  in _rtl92de_llt_write()
560 	rtl_write_dword(rtlpriv, REG_RQPN, value32);  in _rtl92de_llt_table_init()
564 	rtl_write_dword(rtlpriv, REG_TRXFF_BNDY,  in _rtl92de_llt_table_init()
716 	rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);  in _rtl92de_init_mac()
750 	rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);  in _rtl92de_init_mac()
754 	rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);  in _rtl92de_init_mac()
760 	rtl_write_dword(rtlpriv, REG_BCNQ_DESA,  in _rtl92de_init_mac()
762 	rtl_write_dword(rtlpriv, REG_MGQ_DESA, rtlpci->tx_ring[MGNT_QUEUE].dma);  in _rtl92de_init_mac()
763 	rtl_write_dword(rtlpriv, REG_VOQ_DESA, rtlpci->tx_ring[VO_QUEUE].dma);  in _rtl92de_init_mac()
764 	rtl_write_dword(rtlpriv, REG_VIQ_DESA, rtlpci->tx_ring[VI_QUEUE].dma);  in _rtl92de_init_mac()
765 	rtl_write_dword(rtlpriv, REG_BEQ_DESA, rtlpci->tx_ring[BE_QUEUE].dma);  in _rtl92de_init_mac()
766 	rtl_write_dword(rtlpriv, REG_BKQ_DESA, rtlpci->tx_ring[BK_QUEUE].dma);  in _rtl92de_init_mac()
767 	rtl_write_dword(rtlpriv, REG_HQ_DESA, rtlpci->tx_ring[HIGH_QUEUE].dma);  in _rtl92de_init_mac()
769 	rtl_write_dword(rtlpriv, REG_RX_DESA,  in _rtl92de_init_mac()
778 	rtl_write_dword(rtlpriv, REG_INT_MIG, 0);  in _rtl92de_init_mac()
792 	rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);  in _rtl92de_init_mac()
808 	rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);  in _rtl92de_hw_configure()
813 	rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);  in _rtl92de_hw_configure()
815 	rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);  in _rtl92de_hw_configure()
816 	rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);  in _rtl92de_hw_configure()
817 	rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);  in _rtl92de_hw_configure()
818 	rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);  in _rtl92de_hw_configure()
821 		rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb9726641);  in _rtl92de_hw_configure()
823 		rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x66626641);  in _rtl92de_hw_configure()
825 		rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);  in _rtl92de_hw_configure()
846 	rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);  in _rtl92de_hw_configure()
847 	rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);  in _rtl92de_hw_configure()
1202 		rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);  in rtl92de_set_qos()
1207 		rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);  in rtl92de_set_qos()
1210 		rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);  in rtl92de_set_qos()
1223 	rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);  in rtl92de_enable_interrupt()
1224 	rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);  in rtl92de_enable_interrupt()
1232 	rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);  in rtl92de_disable_interrupt()
1233 	rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);  in rtl92de_disable_interrupt()
1263 	rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);  in _rtl92de_poweroff_adapter()
1270 	rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL,  in _rtl92de_poweroff_adapter()
1389 	rtl_write_dword(rtlpriv, ISR, *p_inta);  in rtl92de_interrupt_recognized()
1958 	rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);  in rtl92de_update_hal_rate_table()