Lines Matching refs:BIT
327 #define RXDMA_AGG_EN BIT(7)
333 #define ISO_MD2PP BIT(0)
334 #define ISO_PA2PCIE BIT(3)
335 #define ISO_PLL2MD BIT(4)
336 #define ISO_PWC_DV2RP BIT(11)
337 #define ISO_PWC_RV2RP BIT(12)
340 #define FEN_MREGEN BIT(15)
341 #define FEN_DCORE BIT(11)
342 #define FEN_CPUEN BIT(10)
344 #define PAD_HWPD_IDN BIT(22)
346 #define SYS_CLKSEL_80M BIT(0)
347 #define SYS_PS_CLKSEL BIT(1)
348 #define SYS_CPU_CLKSEL BIT(2)
349 #define SYS_MAC_CLK_EN BIT(11)
350 #define SYS_SWHW_SEL BIT(14)
351 #define SYS_FWHW_SEL BIT(15)
353 #define CmdEEPROM_En BIT(5)
354 #define CmdEERPOMSEL BIT(4)
355 #define Cmd9346CR_9356SEL BIT(4)
357 #define AFE_MBEN BIT(1)
358 #define AFE_BGEN BIT(0)
360 #define SPS1_SWEN BIT(1)
361 #define SPS1_LDEN BIT(0)
363 #define RF_EN BIT(0)
364 #define RF_RSTB BIT(1)
365 #define RF_SDMRSTB BIT(2)
367 #define LDA15_EN BIT(0)
369 #define LDV12_EN BIT(0)
370 #define LDV12_SDBY BIT(1)
372 #define XTAL_GATE_AFE BIT(10)
374 #define APLL_EN BIT(0)
376 #define AFR_CardBEn BIT(0)
377 #define AFR_CLKRUN_SEL BIT(1)
378 #define AFR_FuncRegEn BIT(2)
380 #define APSDOFF_STATUS BIT(15)
381 #define APSDOFF BIT(14)
382 #define BBRSTN BIT(13)
383 #define BB_GLB_RSTN BIT(12)
384 #define SCHEDULE_EN BIT(10)
385 #define MACRXEN BIT(9)
386 #define MACTXEN BIT(8)
387 #define DDMA_EN BIT(7)
388 #define FW2HW_EN BIT(6)
389 #define RXDMA_EN BIT(5)
390 #define TXDMA_EN BIT(4)
391 #define HCI_RXDMA_EN BIT(3)
392 #define HCI_TXDMA_EN BIT(2)
394 #define StopHCCA BIT(6)
395 #define StopHigh BIT(5)
396 #define StopMgt BIT(4)
397 #define StopVO BIT(3)
398 #define StopVI BIT(2)
399 #define StopBE BIT(1)
400 #define StopBK BIT(0)
403 #define LBK_MAC_LB (BIT(0) | BIT(1) | BIT(3))
404 #define LBK_MAC_DLB (BIT(0) | BIT(1))
405 #define LBK_DMA_LB (BIT(0) | BIT(1) | BIT(2))
407 #define TCP_OFDL_EN BIT(25)
408 #define HWPC_TX_EN BIT(24)
409 #define TXDMAPRE2FULL BIT(23)
410 #define DISCW BIT(20)
411 #define TCRICV BIT(19)
412 #define CfendForm BIT(17)
413 #define TCRCRC BIT(16)
414 #define FAKE_IMEM_EN BIT(15)
415 #define TSFRST BIT(9)
416 #define TSFEN BIT(8)
417 #define FWALLRDY (BIT(0) | BIT(1) | BIT(2) | \
418 BIT(3) | BIT(4) | BIT(5) | \
419 BIT(6) | BIT(7))
420 #define FWRDY BIT(7)
421 #define BASECHG BIT(6)
422 #define IMEM BIT(5)
423 #define DMEM_CODE_DONE BIT(4)
424 #define EXT_IMEM_CHK_RPT BIT(3)
425 #define EXT_IMEM_CODE_DONE BIT(2)
426 #define IMEM_CHK_RPT BIT(1)
427 #define IMEM_CODE_DONE BIT(0)
428 #define IMEM_CODE_DONE BIT(0)
429 #define IMEM_CHK_RPT BIT(1)
430 #define EMEM_CODE_DONE BIT(2)
431 #define EMEM_CHK_RPT BIT(3)
432 #define DMEM_CODE_DONE BIT(4)
433 #define IMEM_RDY BIT(5)
434 #define BASECHG BIT(6)
435 #define FWRDY BIT(7)
444 #define TCR_TSFEN BIT(8)
445 #define TCR_TSFRST BIT(9)
446 #define TCR_FAKE_IMEM_EN BIT(15)
447 #define TCR_CRC BIT(16)
448 #define TCR_ICV BIT(19)
449 #define TCR_DISCW BIT(20)
450 #define TCR_HWPC_TX_EN BIT(24)
451 #define TCR_TCP_OFDL_EN BIT(25)
455 #define RCR_APPFCS BIT(31)
456 #define RCR_DIS_ENC_2BYTE BIT(30)
457 #define RCR_DIS_AES_2BYTE BIT(29)
458 #define RCR_HTC_LOC_CTRL BIT(28)
459 #define RCR_ENMBID BIT(27)
460 #define RCR_RX_TCPOFDL_EN BIT(26)
461 #define RCR_APP_PHYST_RXFF BIT(25)
462 #define RCR_APP_PHYST_STAFF BIT(24)
463 #define RCR_CBSSID BIT(23)
464 #define RCR_APWRMGT BIT(22)
465 #define RCR_ADD3 BIT(21)
466 #define RCR_AMF BIT(20)
467 #define RCR_ACF BIT(19)
468 #define RCR_ADF BIT(18)
469 #define RCR_APP_MIC BIT(17)
470 #define RCR_APP_ICV BIT(16)
471 #define RCR_RXFTH BIT(13)
472 #define RCR_AICV BIT(12)
473 #define RCR_RXDESC_LK_EN BIT(11)
474 #define RCR_APP_BA_SSN BIT(6)
475 #define RCR_ACRC32 BIT(5)
476 #define RCR_RXSHFT_EN BIT(4)
477 #define RCR_AB BIT(3)
478 #define RCR_AM BIT(2)
479 #define RCR_APM BIT(1)
480 #define RCR_AAP BIT(0)
496 #define ENUART BIT(7)
497 #define ENJTAG BIT(3)
498 #define BTMODE (BIT(2) | BIT(1))
499 #define ENBT BIT(0)
501 #define ENMBID BIT(7)
502 #define BCNUM (BIT(6) | BIT(5) | BIT(4))
510 #define ENSWBCN BIT(15)
522 #define RRSR_1M BIT(0)
523 #define RRSR_2M BIT(1)
524 #define RRSR_5_5M BIT(2)
525 #define RRSR_11M BIT(3)
526 #define RRSR_6M BIT(4)
527 #define RRSR_9M BIT(5)
528 #define RRSR_12M BIT(6)
529 #define RRSR_18M BIT(7)
530 #define RRSR_24M BIT(8)
531 #define RRSR_36M BIT(9)
532 #define RRSR_48M BIT(10)
533 #define RRSR_54M BIT(11)
534 #define RRSR_MCS0 BIT(12)
535 #define RRSR_MCS1 BIT(13)
536 #define RRSR_MCS2 BIT(14)
537 #define RRSR_MCS3 BIT(15)
538 #define RRSR_MCS4 BIT(16)
539 #define RRSR_MCS5 BIT(17)
540 #define RRSR_MCS6 BIT(18)
541 #define RRSR_MCS7 BIT(19)
542 #define BRSR_AckShortPmb BIT(23)
593 #define AcmHw_HwEn BIT(0)
594 #define AcmHw_BeqEn BIT(1)
595 #define AcmHw_ViqEn BIT(2)
596 #define AcmHw_VoqEn BIT(3)
597 #define AcmHw_BeqStatus BIT(4)
598 #define AcmHw_ViqStatus BIT(5)
599 #define AcmHw_VoqStatus BIT(6)
604 #define NAV_UPPER_EN BIT(16)
608 #define BW_OPMODE_20MHZ BIT(2)
609 #define BW_OPMODE_5G BIT(1)
610 #define BW_OPMODE_11J BIT(0)
612 #define RXERR_RPT_RST BIT(27)
628 #define SCR_TXUSEDK BIT(0)
629 #define SCR_RXUSEDK BIT(1)
630 #define SCR_TXENCENABLE BIT(2)
631 #define SCR_RXENCENABLE BIT(3)
632 #define SCR_SKBYA2 BIT(4)
633 #define SCR_NOSKMC BIT(5)
635 #define CAM_VALID BIT(15)
637 #define CAM_USEDK BIT(5)
648 #define CAM_WRITE BIT(16)
650 #define CAM_POLLINIG BIT(31)
652 #define WOW_PMEN BIT(0)
653 #define WOW_WOMEN BIT(1)
654 #define WOW_MAGIC BIT(2)
655 #define WOW_UWF BIT(3)
657 #define GPIOMUX_EN BIT(3)
662 #define GPIOSEL_GPIO_MASK (~(BIT(0)|BIT(1)))
664 #define HST_RDBUSY BIT(0)
665 #define CPU_WTBUSY BIT(1)
668 #define IMR_CPUERR BIT(5)
669 #define IMR_ATIMEND BIT(4)
670 #define IMR_TBDOK BIT(3)
671 #define IMR_TBDER BIT(2)
672 #define IMR_BCNDMAINT8 BIT(1)
673 #define IMR_BCNDMAINT7 BIT(0)
674 #define IMR_BCNDMAINT6 BIT(31)
675 #define IMR_BCNDMAINT5 BIT(30)
676 #define IMR_BCNDMAINT4 BIT(29)
677 #define IMR_BCNDMAINT3 BIT(28)
678 #define IMR_BCNDMAINT2 BIT(27)
679 #define IMR_BCNDMAINT1 BIT(26)
680 #define IMR_BCNDOK8 BIT(25)
681 #define IMR_BCNDOK7 BIT(24)
682 #define IMR_BCNDOK6 BIT(23)
683 #define IMR_BCNDOK5 BIT(22)
684 #define IMR_BCNDOK4 BIT(21)
685 #define IMR_BCNDOK3 BIT(20)
686 #define IMR_BCNDOK2 BIT(19)
687 #define IMR_BCNDOK1 BIT(18)
688 #define IMR_TIMEOUT2 BIT(17)
689 #define IMR_TIMEOUT1 BIT(16)
690 #define IMR_TXFOVW BIT(15)
691 #define IMR_PSTIMEOUT BIT(14)
692 #define IMR_BCNINT BIT(13)
693 #define IMR_RXFOVW BIT(12)
694 #define IMR_RDU BIT(11)
695 #define IMR_RXCMDOK BIT(10)
696 #define IMR_BDOK BIT(9)
697 #define IMR_HIGHDOK BIT(8)
698 #define IMR_COMDOK BIT(7)
699 #define IMR_MGNTDOK BIT(6)
700 #define IMR_HCCADOK BIT(5)
701 #define IMR_BKDOK BIT(4)
702 #define IMR_BEDOK BIT(3)
703 #define IMR_VIDOK BIT(2)
704 #define IMR_VODOK BIT(1)
705 #define IMR_ROK BIT(0)
707 #define TPPOLL_BKQ BIT(0)
708 #define TPPOLL_BEQ BIT(1)
709 #define TPPOLL_VIQ BIT(2)
710 #define TPPOLL_VOQ BIT(3)
711 #define TPPOLL_BQ BIT(4)
712 #define TPPOLL_CQ BIT(5)
713 #define TPPOLL_MQ BIT(6)
714 #define TPPOLL_HQ BIT(7)
715 #define TPPOLL_HCCAQ BIT(8)
716 #define TPPOLL_STOPBK BIT(9)
717 #define TPPOLL_STOPBE BIT(10)
718 #define TPPOLL_STOPVI BIT(11)
719 #define TPPOLL_STOPVO BIT(12)
720 #define TPPOLL_STOPMGT BIT(13)
721 #define TPPOLL_STOPHIGH BIT(14)
722 #define TPPOLL_STOPHCCA BIT(15)
725 #define CCX_CMD_CLM_ENABLE BIT(0)
726 #define CCX_CMD_NHM_ENABLE BIT(1)
727 #define CCX_CMD_FUNCTION_ENABLE BIT(8)
728 #define CCX_CMD_IGNORE_CCA BIT(9)
729 #define CCX_CMD_IGNORE_TXON BIT(10)
730 #define CCX_CLM_RESULT_READY BIT(16)
731 #define CCX_NHM_RESULT_READY BIT(16)
850 #define RCR_9356SEL BIT(6)
854 #define TCR_SAT BIT(24)
857 #define RCR_OnlyErlPkt BIT(31)
885 #define HAL_8192S_HW_GPIO_OFF_BIT BIT(3)
887 #define HAL_8192S_HW_GPIO_WPS_BIT BIT(4)