Lines Matching refs:mask
141 enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
142 void (*mux_A_periph)(void __iomem *pio, unsigned mask);
143 void (*mux_B_periph)(void __iomem *pio, unsigned mask);
144 void (*mux_C_periph)(void __iomem *pio, unsigned mask);
145 void (*mux_D_periph)(void __iomem *pio, unsigned mask);
147 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool in_on);
149 void (*set_debounce)(void __iomem *pio, unsigned mask, bool in_on, u32 div);
151 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool in_on);
153 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
321 static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) in at91_mux_disable_interrupt() argument
323 writel_relaxed(mask, pio + PIO_IDR); in at91_mux_disable_interrupt()
331 static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) in at91_mux_set_pullup() argument
333 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR)); in at91_mux_set_pullup()
341 static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on) in at91_mux_set_multidrive() argument
343 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR)); in at91_mux_set_multidrive()
346 static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask) in at91_mux_set_A_periph() argument
348 writel_relaxed(mask, pio + PIO_ASR); in at91_mux_set_A_periph()
351 static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask) in at91_mux_set_B_periph() argument
353 writel_relaxed(mask, pio + PIO_BSR); in at91_mux_set_B_periph()
356 static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask) in at91_mux_pio3_set_A_periph() argument
359 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, in at91_mux_pio3_set_A_periph()
361 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, in at91_mux_pio3_set_A_periph()
365 static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask) in at91_mux_pio3_set_B_periph() argument
367 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, in at91_mux_pio3_set_B_periph()
369 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, in at91_mux_pio3_set_B_periph()
373 static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask) in at91_mux_pio3_set_C_periph() argument
375 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); in at91_mux_pio3_set_C_periph()
376 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); in at91_mux_pio3_set_C_periph()
379 static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask) in at91_mux_pio3_set_D_periph() argument
381 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); in at91_mux_pio3_set_D_periph()
382 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); in at91_mux_pio3_set_D_periph()
385 static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask) in at91_mux_pio3_get_periph() argument
389 if (readl_relaxed(pio + PIO_PSR) & mask) in at91_mux_pio3_get_periph()
392 select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask); in at91_mux_pio3_get_periph()
393 select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1); in at91_mux_pio3_get_periph()
398 static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask) in at91_mux_get_periph() argument
402 if (readl_relaxed(pio + PIO_PSR) & mask) in at91_mux_get_periph()
405 select = readl_relaxed(pio + PIO_ABSR) & mask; in at91_mux_get_periph()
415 static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) in at91_mux_set_deglitch() argument
417 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); in at91_mux_set_deglitch()
420 static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) in at91_mux_pio3_set_deglitch() argument
423 __raw_writel(mask, pio + PIO_IFSCDR); in at91_mux_pio3_set_deglitch()
424 at91_mux_set_deglitch(pio, mask, is_on); in at91_mux_pio3_set_deglitch()
434 static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask, in at91_mux_pio3_set_debounce() argument
438 __raw_writel(mask, pio + PIO_IFSCER); in at91_mux_pio3_set_debounce()
440 __raw_writel(mask, pio + PIO_IFER); in at91_mux_pio3_set_debounce()
442 __raw_writel(mask, pio + PIO_IFDR); in at91_mux_pio3_set_debounce()
451 static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) in at91_mux_pio3_set_pulldown() argument
453 __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); in at91_mux_pio3_set_pulldown()
456 static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask) in at91_mux_pio3_disable_schmitt_trig() argument
458 __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT); in at91_mux_pio3_disable_schmitt_trig()
541 static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask) in at91_mux_gpio_disable() argument
543 writel_relaxed(mask, pio + PIO_PDR); in at91_mux_gpio_disable()
546 static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input) in at91_mux_gpio_enable() argument
548 writel_relaxed(mask, pio + PIO_PER); in at91_mux_gpio_enable()
549 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER)); in at91_mux_gpio_enable()
560 unsigned mask; in at91_pmx_enable() local
579 mask = pin_to_mask(pin->pin); in at91_pmx_enable()
580 at91_mux_disable_interrupt(pio, mask); in at91_pmx_enable()
583 at91_mux_gpio_enable(pio, mask, 1); in at91_pmx_enable()
586 info->ops->mux_A_periph(pio, mask); in at91_pmx_enable()
589 info->ops->mux_B_periph(pio, mask); in at91_pmx_enable()
594 info->ops->mux_C_periph(pio, mask); in at91_pmx_enable()
599 info->ops->mux_D_periph(pio, mask); in at91_pmx_enable()
603 at91_mux_gpio_disable(pio, mask); in at91_pmx_enable()
617 unsigned mask; in at91_pmx_disable() local
624 mask = pin_to_mask(pin->pin); in at91_pmx_disable()
625 at91_mux_gpio_enable(pio, mask, 1); in at91_pmx_disable()
663 unsigned mask; in at91_gpio_request_enable() local
678 mask = 1 << (offset - chip->base); in at91_gpio_request_enable()
681 offset, 'A' + range->id, offset - chip->base, mask); in at91_gpio_request_enable()
683 writel_relaxed(mask, at91_chip->regbase + PIO_PER); in at91_gpio_request_enable()
742 unsigned mask; in at91_pinconf_set() local
747 mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK); in at91_pinconf_set()
752 at91_mux_set_pullup(pio, mask, config & PULL_UP); in at91_pinconf_set()
753 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE); in at91_pinconf_set()
755 info->ops->set_deglitch(pio, mask, config & DEGLITCH); in at91_pinconf_set()
757 info->ops->set_debounce(pio, mask, config & DEBOUNCE, in at91_pinconf_set()
760 info->ops->set_pulldown(pio, mask, config & PULL_DOWN); in at91_pinconf_set()
762 info->ops->disable_schmitt_trig(pio, mask); in at91_pinconf_set()
1099 unsigned mask = 1 << offset; in at91_gpio_direction_input() local
1101 writel_relaxed(mask, pio + PIO_ODR); in at91_gpio_direction_input()
1109 unsigned mask = 1 << offset; in at91_gpio_get() local
1113 return (pdsr & mask) != 0; in at91_gpio_get()
1121 unsigned mask = 1 << offset; in at91_gpio_set() local
1123 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); in at91_gpio_set()
1131 unsigned mask = 1 << offset; in at91_gpio_direction_output() local
1133 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); in at91_gpio_direction_output()
1134 writel_relaxed(mask, pio + PIO_OER); in at91_gpio_direction_output()
1164 unsigned mask = pin_to_mask(pin); in at91_gpio_dbg_show() local
1171 mode = at91_gpio->ops->get_periph(pio, mask); in at91_gpio_dbg_show()
1178 pdsr & mask ? in at91_gpio_dbg_show()
1208 unsigned mask = 1 << d->hwirq; in gpio_irq_mask() local
1211 writel_relaxed(mask, pio + PIO_IDR); in gpio_irq_mask()
1218 unsigned mask = 1 << d->hwirq; in gpio_irq_unmask() local
1221 writel_relaxed(mask, pio + PIO_IER); in gpio_irq_unmask()
1240 unsigned mask = 1 << d->hwirq; in alt_gpio_irq_type() local
1244 writel_relaxed(mask, pio + PIO_ESR); in alt_gpio_irq_type()
1245 writel_relaxed(mask, pio + PIO_REHLSR); in alt_gpio_irq_type()
1248 writel_relaxed(mask, pio + PIO_ESR); in alt_gpio_irq_type()
1249 writel_relaxed(mask, pio + PIO_FELLSR); in alt_gpio_irq_type()
1252 writel_relaxed(mask, pio + PIO_LSR); in alt_gpio_irq_type()
1253 writel_relaxed(mask, pio + PIO_FELLSR); in alt_gpio_irq_type()
1256 writel_relaxed(mask, pio + PIO_LSR); in alt_gpio_irq_type()
1257 writel_relaxed(mask, pio + PIO_REHLSR); in alt_gpio_irq_type()
1264 writel_relaxed(mask, pio + PIO_AIMDR); in alt_gpio_irq_type()
1273 writel_relaxed(mask, pio + PIO_AIMER); in alt_gpio_irq_type()
1287 unsigned mask = 1 << d->hwirq; in gpio_irq_set_wake() local
1293 wakeups[bank] |= mask; in gpio_irq_set_wake()
1295 wakeups[bank] &= ~mask; in gpio_irq_set_wake()