Lines Matching refs:mask
220 .mask = PADS_AS_GPIO_REG0_MASK,
224 .mask = PADS_AS_GPIO_REGS_MASK,
228 .mask = PADS_AS_GPIO_REGS_MASK,
232 .mask = PADS_AS_GPIO_REGS_MASK,
236 .mask = PADS_AS_GPIO_REGS_MASK,
240 .mask = PADS_AS_GPIO_REGS_MASK,
244 .mask = PADS_AS_GPIO_REGS_MASK,
248 .mask = PADS_AS_GPIO_REG7_MASK,
281 .mask = FSMC_8BIT_REG7_MASK,
306 .mask = KBD_ROW_COL_MASK,
310 .mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
337 .mask = MCIF_MASK,
341 .mask = FSMC_PNOR_AND_MCIF_REG6_MASK,
375 .mask = KBD_ROW_COL_MASK,
379 .mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
404 .mask = KBD_COL5_MASK,
408 .mask = PWM1_AND_KBD_COL5_REG0_MASK,
441 .mask = SPDIF_IN_REG0_MASK,
473 .mask = SPDIF_OUT_REG4_MASK,
477 .mask = SPDIF_OUT_ENB_MASK,
509 .mask = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK,
513 .mask = UART0_ENH_AND_GPT_REG0_MASK |
549 .mask = SSP0_CS1_MASK,
553 .mask = PWM0_AND_SSP0_CS1_REG0_MASK,
578 .mask = KBD_COL5_MASK,
582 .mask = PWM1_AND_KBD_COL5_REG0_MASK,
607 .mask = GPT0_TMR0_CPT_MASK,
611 .mask = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK,
636 .mask = GPT0_TMR1_CLK_MASK,
640 .mask = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
673 .mask = VIP_REG1_MASK,
699 .mask = CAM0_MASK,
703 .mask = VIP_AND_CAM0_REG2_MASK,
729 .mask = CAM1_MASK,
733 .mask = VIP_AND_CAM1_REG1_MASK,
737 .mask = VIP_AND_CAM1_REG2_MASK,
763 .mask = CAM2_MASK,
767 .mask = VIP_AND_CAM2_REG1_MASK,
793 .mask = CAM3_MASK,
797 .mask = VIP_AND_CAM3_REG0_MASK,
801 .mask = VIP_AND_CAM3_REG1_MASK,
835 .mask = CAM0_MASK,
839 .mask = VIP_AND_CAM0_REG2_MASK,
872 .mask = CAM1_MASK,
876 .mask = VIP_AND_CAM1_REG1_MASK,
880 .mask = VIP_AND_CAM1_REG2_MASK,
913 .mask = CAM2_MASK,
917 .mask = VIP_AND_CAM2_REG1_MASK,
950 .mask = CAM3_MASK,
954 .mask = VIP_AND_CAM3_REG0_MASK,
958 .mask = VIP_AND_CAM3_REG1_MASK,
990 .mask = SMI_REG2_MASK,
1022 .mask = SSP0_REG2_MASK,
1047 .mask = SSP0_CS1_MASK,
1051 .mask = PWM0_AND_SSP0_CS1_REG0_MASK,
1076 .mask = SSP0_CS2_MASK,
1080 .mask = TS_AND_SSP0_CS2_REG2_MASK,
1105 .mask = SSP0_CS3_REG4_MASK,
1138 .mask = UART0_REG2_MASK,
1163 .mask = GPT_MASK,
1167 .mask = UART0_ENH_AND_GPT_REG0_MASK,
1199 .mask = UART1_REG2_MASK,
1231 .mask = I2S_IN_REG2_MASK,
1235 .mask = I2S_IN_REG3_MASK,
1260 .mask = I2S_OUT_REG3_MASK,
1294 .mask = GMAC_REG3_MASK, \
1298 .mask = GMAC_REG4_MASK, \
1307 .mask = GMAC_PHY_IF_SEL_MASK,
1332 .mask = GMAC_PHY_IF_SEL_MASK,
1357 .mask = GMAC_PHY_IF_SEL_MASK,
1382 .mask = GMAC_PHY_IF_SEL_MASK,
1415 .mask = I2C0_REG4_MASK,
1447 .mask = I2C1_REG0_MASK,
1479 .mask = CEC0_REG4_MASK,
1511 .mask = CEC1_REG4_MASK,
1546 .mask = MCIF_MASK, \
1550 .mask = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, \
1554 .mask = MCIF_REG7_MASK, \
1563 .mask = MCIF_SEL_MASK,
1595 .mask = MCIF_SEL_MASK,
1627 .mask = MCIF_SEL_MASK,
1663 .mask = ARM_TRACE_MASK | MIPHY_DBG_MASK,
1667 .mask = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK,
1671 .mask = CLCD_AND_ARM_TRACE_REG5_MASK,
1675 .mask = CLCD_AND_ARM_TRACE_REG6_MASK,
1699 .mask = ARM_TRACE_MASK | MIPHY_DBG_MASK,
1703 .mask = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK,
1707 .mask = CLCD_AND_ARM_TRACE_REG5_MASK,
1711 .mask = CLCD_AND_ARM_TRACE_REG6_MASK,
1746 .mask = ARM_TRACE_MASK,
1750 .mask = CLCD_AND_ARM_TRACE_REG4_MASK,
1754 .mask = CLCD_AND_ARM_TRACE_REG5_MASK,
1758 .mask = CLCD_AND_ARM_TRACE_REG6_MASK,
1792 .mask = MIPHY_DBG_MASK,
1796 .mask = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK,
1828 .mask = SATA_PCIE_CFG_MASK,
1860 .mask = SATA_PCIE_CFG_MASK,