Lines Matching refs:AMD_BIT
217 tmp = AMD_BIT(UDC_DEVINT_SVC) | in udc_mask_unused_interrupts()
218 AMD_BIT(UDC_DEVINT_ENUM) | in udc_mask_unused_interrupts()
219 AMD_BIT(UDC_DEVINT_US) | in udc_mask_unused_interrupts()
220 AMD_BIT(UDC_DEVINT_UR) | in udc_mask_unused_interrupts()
221 AMD_BIT(UDC_DEVINT_ES) | in udc_mask_unused_interrupts()
222 AMD_BIT(UDC_DEVINT_SI) | in udc_mask_unused_interrupts()
223 AMD_BIT(UDC_DEVINT_SOF)| in udc_mask_unused_interrupts()
224 AMD_BIT(UDC_DEVINT_SC); in udc_mask_unused_interrupts()
301 if (readl(&ep->regs->ctl) & AMD_BIT(UDC_EPCTL_NAK)) { in UDC_QUEUE_CNAK()
373 tmp |= AMD_BIT(UDC_EPCTL_F); in udc_ep_enable()
427 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in udc_ep_enable()
452 tmp |= AMD_BIT(UDC_EPCTL_SNAK); in ep_init()
458 tmp |= AMD_BIT(ep->num); in ep_init()
468 tmp |= AMD_BIT(UDC_EPSTS_IN); in ep_init()
473 tmp |= AMD_BIT(UDC_EPCTL_F); in ep_init()
584 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L); in udc_init_bna_dummy()
740 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L); in prep_dma()
804 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in prep_dma()
882 while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L))) in udc_get_last_dma_desc()
899 while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L))) { in udc_get_ppbdu_rxbytes()
1023 td->status |= AMD_BIT(UDC_DMA_IN_STS_L); in udc_create_dma_chain()
1044 tmp |= AMD_BIT(UDC_DEVCTL_RDE); in udc_set_rde()
1107 tmp |= AMD_BIT(UDC_DEVCTL_CSR_DONE); in udc_queue()
1115 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in udc_queue()
1167 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in udc_queue()
1335 tmp |= AMD_BIT(UDC_EPCTL_S); in udc_set_halt()
1357 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in udc_set_halt()
1488 tmp |= AMD_BIT(UDC_DEVCFG_CSR_PRG); in udc_basic_init()
1490 tmp |= AMD_BIT(UDC_DEVCFG_SP); in udc_basic_init()
1492 tmp |= AMD_BIT(UDC_DEVCFG_RWKP); in udc_basic_init()
1558 reg |= AMD_BIT(UDC_EPCTL_SNAK); in udc_setup_endpoints()
1685 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg); in udc_soft_reset()
1706 tmp |= AMD_BIT(UDC_DEVCTL_RDE); in udc_timer_function()
1710 & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) { in udc_timer_function()
1749 if (!(tmp & AMD_BIT(UDC_EPCTL_S))) { in udc_handle_halt_state()
1763 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in udc_handle_halt_state()
1814 tmp |= AMD_BIT(UDC_EPCTL_F); in activate_control_endpoints()
1863 AMD_BIT(UDC_DMA_OUT_STS_L); in activate_control_endpoints()
1879 tmp |= AMD_BIT(UDC_DEVCTL_MODE) in activate_control_endpoints()
1880 | AMD_BIT(UDC_DEVCTL_RDE) in activate_control_endpoints()
1881 | AMD_BIT(UDC_DEVCTL_TDE); in activate_control_endpoints()
1883 tmp |= AMD_BIT(UDC_DEVCTL_BF); in activate_control_endpoints()
1885 tmp |= AMD_BIT(UDC_DEVCTL_DU); in activate_control_endpoints()
1891 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in activate_control_endpoints()
1898 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in activate_control_endpoints()
1979 tmp |= AMD_BIT(UDC_DEVCTL_SD); in amd5536_udc_stop()
1998 reg |= AMD_BIT(UDC_EPCTL_CNAK); in udc_process_cnak_queue()
2009 reg |= AMD_BIT(UDC_EPCTL_CNAK); in udc_process_cnak_queue()
2061 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) { in udc_data_out_isr()
2065 writel(tmp | AMD_BIT(UDC_EPSTS_BNA), &ep->regs->sts); in udc_data_out_isr()
2075 if (tmp & AMD_BIT(UDC_EPSTS_HE)) { in udc_data_out_isr()
2079 writel(tmp | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts); in udc_data_out_isr()
2248 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) in udc_data_out_isr()
2275 if (epsts & AMD_BIT(UDC_EPSTS_BNA)) { in udc_data_in_isr()
2288 if (epsts & AMD_BIT(UDC_EPSTS_HE)) { in udc_data_in_isr()
2294 writel(epsts | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts); in udc_data_in_isr()
2300 if (epsts & AMD_BIT(UDC_EPSTS_TDC)) { in udc_data_in_isr()
2332 tmp |= AMD_BIT(ep->num); in udc_data_in_isr()
2344 if ((epsts & AMD_BIT(UDC_EPSTS_IN)) in udc_data_in_isr()
2345 && !(epsts & AMD_BIT(UDC_EPSTS_TDC))) { in udc_data_in_isr()
2395 tmp |= AMD_BIT(UDC_EPCTL_P); in udc_data_in_isr()
2404 tmp |= AMD_BIT(ep->num); in udc_data_in_isr()
2433 writel(AMD_BIT(UDC_EPINT_OUT_EP0), &dev->regs->ep_irqsts); in udc_control_out_isr()
2437 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) { in udc_control_out_isr()
2439 writel(AMD_BIT(UDC_EPSTS_BNA), in udc_control_out_isr()
2459 tmp |= AMD_BIT(UDC_EPCTL_SNAK); in udc_control_out_isr()
2545 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in udc_control_out_isr()
2552 tmp |= AMD_BIT(UDC_EPCTL_S); in udc_control_out_isr()
2561 tmp |= AMD_BIT(UDC_EPCTL_CNAK); in udc_control_out_isr()
2625 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) in udc_control_out_isr()
2645 writel(AMD_BIT(UDC_EPINT_IN_EP0), &dev->regs->ep_irqsts); in udc_control_in_isr()
2649 if (tmp & AMD_BIT(UDC_EPSTS_TDC)) { in udc_control_in_isr()
2654 writel(AMD_BIT(UDC_EPSTS_TDC), in udc_control_in_isr()
2658 } else if (tmp & AMD_BIT(UDC_EPSTS_IN)) { in udc_control_in_isr()
2663 writel(AMD_BIT(UDC_EPSTS_IN), in udc_control_in_isr()
2670 tmp |= AMD_BIT(UDC_EPCTL_S); in udc_control_in_isr()
2691 tmp |= AMD_BIT(UDC_EPCTL_P); in udc_control_in_isr()
2724 writel(AMD_BIT(UDC_EPSTS_IN), in udc_control_in_isr()
2746 if (dev_irq & AMD_BIT(UDC_DEVINT_SC)) { in udc_dev_isr()
2795 if (dev_irq & AMD_BIT(UDC_DEVINT_SI)) { in udc_dev_isr()
2855 if (dev_irq & AMD_BIT(UDC_DEVINT_UR)) { in udc_dev_isr()
2883 if (!(tmp & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) in udc_dev_isr()
2896 writel(tmp | AMD_BIT(UDC_DEVCFG_DMARST), &dev->regs->cfg); in udc_dev_isr()
2911 if (dev_irq & AMD_BIT(UDC_DEVINT_US)) { in udc_dev_isr()
2921 if (dev_irq & AMD_BIT(UDC_DEVINT_ENUM)) { in udc_dev_isr()
2942 if (dev_irq & AMD_BIT(UDC_DEVINT_SVC)) { in udc_dev_isr()
2948 if (!(tmp & AMD_BIT(UDC_DEVSTS_SESSVLD))) { in udc_dev_isr()
2951 tmp |= AMD_BIT(UDC_DEVINT_US); in udc_dev_isr()
2977 if (reg & AMD_BIT(UDC_EPINT_OUT_EP0)) in udc_irq()
2979 if (reg & AMD_BIT(UDC_EPINT_IN_EP0)) in udc_irq()
3070 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg); in udc_pci_remove()
3310 reg |= AMD_BIT(UDC_DEVCTL_SD); in udc_probe()
3333 tmp |= AMD_BIT(UDC_DEVCTL_RES); in udc_remote_wakeup()