775 				|| ep->num == UDC_EP0IN_IX) {  in prep_dma()
1114 				tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_queue()
1116 				writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_queue()
1117 				dev->ep[UDC_EP0IN_IX].naking = 0;  in udc_queue()
1118 				UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX],  in udc_queue()
1119 							UDC_EP0IN_IX);  in udc_queue()
1554 			if (tmp != UDC_EP0IN_IX && tmp != UDC_EP0OUT_IX  in udc_setup_endpoints()
1567 		dev->ep[UDC_EP0IN_IX].ep.maxpacket = UDC_FS_EP0IN_MAX_PKT_SIZE;  in udc_setup_endpoints()
1571 		dev->ep[UDC_EP0IN_IX].ep.maxpacket = UDC_EP0IN_MAX_PKT_SIZE;  in udc_setup_endpoints()
1579 	dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;  in udc_setup_endpoints()
1580 	dev->ep[UDC_EP0IN_IX].halted = 0;  in udc_setup_endpoints()
1648 			&dev->ep[UDC_EP0IN_IX]);  in udc_tasklet_disconnect()
1813 	tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);  in activate_control_endpoints()
1815 	writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);  in activate_control_endpoints()
1818 	dev->ep[UDC_EP0IN_IX].in = 1;  in activate_control_endpoints()
1822 	tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);  in activate_control_endpoints()
1829 	writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);  in activate_control_endpoints()
1832 	tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);  in activate_control_endpoints()
1839 	writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);  in activate_control_endpoints()
1890 	tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);  in activate_control_endpoints()
1892 	writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);  in activate_control_endpoints()
1893 	dev->ep[UDC_EP0IN_IX].naking = 0;  in activate_control_endpoints()
1894 	UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);  in activate_control_endpoints()
1930 		dev->ep[UDC_EP0IN_IX].ep.driver_data;  in amd5536_udc_start()
2458 		tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_control_out_isr()
2460 		writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_control_out_isr()
2461 		dev->ep[UDC_EP0IN_IX].naking = 1;  in udc_control_out_isr()
2483 			dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;  in udc_control_out_isr()
2540 		tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_control_out_isr()
2546 			writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_control_out_isr()
2547 			dev->ep[UDC_EP0IN_IX].naking = 0;  in udc_control_out_isr()
2548 			UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);  in udc_control_out_isr()
2553 			writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_control_out_isr()
2642 	ep = &dev->ep[UDC_EP0IN_IX];  in udc_control_in_isr()
2647 	tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->sts);  in udc_control_in_isr()
2655 				&dev->ep[UDC_EP0IN_IX].regs->sts);  in udc_control_in_isr()
2664 				&dev->ep[UDC_EP0IN_IX].regs->sts);  in udc_control_in_isr()
2690 					readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_control_in_isr()
2693 					&dev->ep[UDC_EP0IN_IX].regs->ctl);  in udc_control_in_isr()
2725 				&dev->ep[UDC_EP0IN_IX].regs->sts);  in udc_control_in_isr()
2878 		empty_req_queue(&dev->ep[UDC_EP0IN_IX]);  in udc_dev_isr()
2879 		ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);  in udc_dev_isr()
2927 		empty_req_queue(&dev->ep[UDC_EP0IN_IX]);  in udc_dev_isr()
2928 		ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);  in udc_dev_isr()
3111 	dev->ep[UDC_EP0IN_IX].dma = &dev->regs->ctl;  in init_dma_pools()