30 #define UDC_EPCTL_ADDR		0x00	/* Endpoint control */  macro
635 		pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);  in pch_udc_ep_set_stall()
636 		pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);  in pch_udc_ep_set_stall()
638 		pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);  in pch_udc_ep_set_stall()
649 	pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);  in pch_udc_ep_clear_stall()
651 	pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);  in pch_udc_ep_clear_stall()
663 				UDC_EPCTL_ET_MASK), UDC_EPCTL_ADDR);  in pch_udc_ep_set_trfr_type()
724 	pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_P);  in pch_udc_ep_set_pd()
733 	pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);  in pch_udc_ep_set_rrdy()
742 	pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);  in pch_udc_ep_clear_rrdy()
890 	return pch_udc_ep_readl(ep, UDC_EPCTL_ADDR);  in pch_udc_read_ep_control()
900 	return pch_udc_ep_writel(ep, 0, UDC_EPCTL_ADDR);  in pch_udc_clear_ep_control()
931 	pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_SNAK);  in pch_udc_ep_set_nak()
944 	if (!(pch_udc_ep_readl(ep, UDC_EPCTL_ADDR) & UDC_EPCTL_NAK))  in pch_udc_ep_clear_nak()
957 		pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);  in pch_udc_ep_clear_nak()
975 		pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);  in pch_udc_ep_fifo_flush()
1024 		pch_udc_ep_writel(ep, UDC_EPCTL_F, UDC_EPCTL_ADDR);  in pch_udc_ep_disable()
1026 		pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);  in pch_udc_ep_disable()
1030 		pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);  in pch_udc_ep_disable()