Lines Matching refs:temp
54 u16 temp; in xhci_common_hub_descriptor() local
60 temp = 0; in xhci_common_hub_descriptor()
63 temp |= HUB_CHAR_INDV_PORT_LPSM; in xhci_common_hub_descriptor()
65 temp |= HUB_CHAR_NO_LPSM; in xhci_common_hub_descriptor()
68 temp |= HUB_CHAR_INDV_PORT_OCPM; in xhci_common_hub_descriptor()
71 desc->wHubCharacteristics = cpu_to_le16(temp); in xhci_common_hub_descriptor()
79 u16 temp; in xhci_usb2_hub_descriptor() local
88 temp = 1 + (ports / 8); in xhci_usb2_hub_descriptor()
89 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; in xhci_usb2_hub_descriptor()
415 u32 temp; in xhci_set_link_state() local
417 temp = xhci_readl(xhci, port_array[port_id]); in xhci_set_link_state()
418 temp = xhci_port_state_to_neutral(temp); in xhci_set_link_state()
419 temp &= ~PORT_PLS_MASK; in xhci_set_link_state()
420 temp |= PORT_LINK_STROBE | link_state; in xhci_set_link_state()
421 xhci_writel(xhci, temp, port_array[port_id]); in xhci_set_link_state()
427 u32 temp; in xhci_set_remote_wake_mask() local
429 temp = xhci_readl(xhci, port_array[port_id]); in xhci_set_remote_wake_mask()
430 temp = xhci_port_state_to_neutral(temp); in xhci_set_remote_wake_mask()
433 temp |= PORT_WKCONN_E; in xhci_set_remote_wake_mask()
435 temp &= ~PORT_WKCONN_E; in xhci_set_remote_wake_mask()
438 temp |= PORT_WKDISC_E; in xhci_set_remote_wake_mask()
440 temp &= ~PORT_WKDISC_E; in xhci_set_remote_wake_mask()
443 temp |= PORT_WKOC_E; in xhci_set_remote_wake_mask()
445 temp &= ~PORT_WKOC_E; in xhci_set_remote_wake_mask()
447 xhci_writel(xhci, temp, port_array[port_id]); in xhci_set_remote_wake_mask()
454 u32 temp; in xhci_test_and_clear_bit() local
456 temp = xhci_readl(xhci, port_array[port_id]); in xhci_test_and_clear_bit()
457 if (temp & port_bit) { in xhci_test_and_clear_bit()
458 temp = xhci_port_state_to_neutral(temp); in xhci_test_and_clear_bit()
459 temp |= port_bit; in xhci_test_and_clear_bit()
460 xhci_writel(xhci, temp, port_array[port_id]); in xhci_test_and_clear_bit()
543 u32 temp, status; in xhci_hub_control() local
586 temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3); in xhci_hub_control()
587 buf[12] = HCS_U1_LATENCY(temp); in xhci_hub_control()
588 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]); in xhci_hub_control()
591 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params); in xhci_hub_control()
592 if (HCC_LTC(temp)) in xhci_hub_control()
602 temp = xhci_readl(xhci, port_array[wIndex]); in xhci_hub_control()
603 if (temp == 0xffffffff) { in xhci_hub_control()
607 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", wIndex, temp); in xhci_hub_control()
610 if (temp & PORT_CSC) in xhci_hub_control()
612 if (temp & PORT_PEC) in xhci_hub_control()
614 if ((temp & PORT_OCC)) in xhci_hub_control()
616 if ((temp & PORT_RC)) in xhci_hub_control()
620 if ((temp & PORT_PLC)) in xhci_hub_control()
622 if ((temp & PORT_WRC)) in xhci_hub_control()
627 if ((temp & PORT_PLS_MASK) == XDEV_U3 in xhci_hub_control()
628 && (temp & PORT_POWER)) in xhci_hub_control()
631 if ((temp & PORT_PLS_MASK) == XDEV_RESUME && in xhci_hub_control()
632 !DEV_SUPERSPEED(temp)) { in xhci_hub_control()
633 if ((temp & PORT_RESET) || !(temp & PORT_PE)) in xhci_hub_control()
664 if ((temp & PORT_PLS_MASK) == XDEV_U0 in xhci_hub_control()
665 && (temp & PORT_POWER) in xhci_hub_control()
671 if (temp & PORT_CONNECT) { in xhci_hub_control()
673 status |= xhci_port_speed(temp); in xhci_hub_control()
675 if (temp & PORT_PE) in xhci_hub_control()
677 if (temp & PORT_OC) in xhci_hub_control()
679 if (temp & PORT_RESET) in xhci_hub_control()
681 if (temp & PORT_POWER) { in xhci_hub_control()
689 xhci_hub_report_link_state(&status, temp); in xhci_hub_control()
694 xhci_del_comp_mod_timer(xhci, temp, wIndex); in xhci_hub_control()
712 temp = xhci_readl(xhci, port_array[wIndex]); in xhci_hub_control()
713 if (temp == 0xffffffff) { in xhci_hub_control()
717 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
721 temp = xhci_readl(xhci, port_array[wIndex]); in xhci_hub_control()
722 if ((temp & PORT_PLS_MASK) != XDEV_U0) { in xhci_hub_control()
734 temp = xhci_readl(xhci, port_array[wIndex]); in xhci_hub_control()
735 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) in xhci_hub_control()
736 || (temp & PORT_PLS_MASK) >= XDEV_U3) { in xhci_hub_control()
759 temp = xhci_readl(xhci, port_array[wIndex]); in xhci_hub_control()
763 temp = xhci_readl(xhci, port_array[wIndex]); in xhci_hub_control()
768 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
773 temp |= PORT_CSC | PORT_PEC | PORT_WRC | in xhci_hub_control()
776 xhci_writel(xhci, temp | PORT_PE, in xhci_hub_control()
778 temp = xhci_readl(xhci, port_array[wIndex]); in xhci_hub_control()
787 temp = xhci_readl(xhci, port_array[wIndex]); in xhci_hub_control()
795 if ((temp & PORT_PE) == 0 || in xhci_hub_control()
821 temp = xhci_readl(xhci, port_array[wIndex]); in xhci_hub_control()
832 xhci_writel(xhci, temp | PORT_POWER, in xhci_hub_control()
835 temp = xhci_readl(xhci, port_array[wIndex]); in xhci_hub_control()
836 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp); in xhci_hub_control()
839 temp = usb_acpi_power_manageable(hcd->self.root_hub, in xhci_hub_control()
841 if (temp) in xhci_hub_control()
847 temp = (temp | PORT_RESET); in xhci_hub_control()
848 xhci_writel(xhci, temp, port_array[wIndex]); in xhci_hub_control()
850 temp = xhci_readl(xhci, port_array[wIndex]); in xhci_hub_control()
851 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp); in xhci_hub_control()
856 temp = xhci_readl(xhci, port_array[wIndex]); in xhci_hub_control()
859 wIndex, temp); in xhci_hub_control()
862 temp |= PORT_WR; in xhci_hub_control()
863 xhci_writel(xhci, temp, port_array[wIndex]); in xhci_hub_control()
865 temp = xhci_readl(xhci, port_array[wIndex]); in xhci_hub_control()
870 temp = xhci_readl(xhci, port_array[wIndex] + 1); in xhci_hub_control()
871 temp &= ~PORT_U1_TIMEOUT_MASK; in xhci_hub_control()
872 temp |= PORT_U1_TIMEOUT(timeout); in xhci_hub_control()
873 xhci_writel(xhci, temp, port_array[wIndex] + 1); in xhci_hub_control()
878 temp = xhci_readl(xhci, port_array[wIndex] + 1); in xhci_hub_control()
879 temp &= ~PORT_U2_TIMEOUT_MASK; in xhci_hub_control()
880 temp |= PORT_U2_TIMEOUT(timeout); in xhci_hub_control()
881 xhci_writel(xhci, temp, port_array[wIndex] + 1); in xhci_hub_control()
887 temp = xhci_readl(xhci, port_array[wIndex]); in xhci_hub_control()
893 temp = xhci_readl(xhci, port_array[wIndex]); in xhci_hub_control()
894 if (temp == 0xffffffff) { in xhci_hub_control()
899 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
902 temp = xhci_readl(xhci, port_array[wIndex]); in xhci_hub_control()
904 xhci_dbg(xhci, "PORTSC %04x\n", temp); in xhci_hub_control()
905 if (temp & PORT_RESET) in xhci_hub_control()
907 if ((temp & PORT_PLS_MASK) == XDEV_U3) { in xhci_hub_control()
908 if ((temp & PORT_PE) == 0) in xhci_hub_control()
938 port_array[wIndex], temp); in xhci_hub_control()
942 port_array[wIndex], temp); in xhci_hub_control()
945 xhci_writel(xhci, temp & ~PORT_POWER, in xhci_hub_control()
949 temp = usb_acpi_power_manageable(hcd->self.root_hub, in xhci_hub_control()
951 if (temp) in xhci_hub_control()
980 u32 temp, status; in xhci_hub_status_data() local
1007 temp = xhci_readl(xhci, port_array[i]); in xhci_hub_status_data()
1008 if (temp == 0xffffffff) { in xhci_hub_status_data()
1012 if ((temp & mask) != 0 || in xhci_hub_status_data()
1019 if ((temp & PORT_RC)) in xhci_hub_status_data()
1122 u32 temp; in xhci_bus_resume() local
1138 temp = xhci_readl(xhci, &xhci->op_regs->command); in xhci_bus_resume()
1139 temp &= ~CMD_EIE; in xhci_bus_resume()
1140 xhci_writel(xhci, temp, &xhci->op_regs->command); in xhci_bus_resume()
1146 u32 temp; in xhci_bus_resume() local
1149 temp = xhci_readl(xhci, port_array[port_index]); in xhci_bus_resume()
1150 if (DEV_SUPERSPEED(temp)) in xhci_bus_resume()
1151 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); in xhci_bus_resume()
1153 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); in xhci_bus_resume()
1155 (temp & PORT_PLS_MASK)) { in xhci_bus_resume()
1156 if (DEV_SUPERSPEED(temp)) { in xhci_bus_resume()
1186 xhci_writel(xhci, temp, port_array[port_index]); in xhci_bus_resume()
1207 temp = xhci_readl(xhci, &xhci->op_regs->command); in xhci_bus_resume()
1208 temp |= CMD_EIE; in xhci_bus_resume()
1209 xhci_writel(xhci, temp, &xhci->op_regs->command); in xhci_bus_resume()
1210 temp = xhci_readl(xhci, &xhci->op_regs->command); in xhci_bus_resume()