514 			musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;  in ep0_rxstate()
570 		musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;  in ep0_txstate()
635 		musb->ep0_state = MUSB_EP0_STAGE_ACKWAIT;  in musb_read_setup()
637 		musb->ep0_state = MUSB_EP0_STAGE_TX;  in musb_read_setup()
644 		musb->ep0_state = MUSB_EP0_STAGE_RX;  in musb_read_setup()
679 			csr, len, decode_ep0stage(musb->ep0_state));  in musb_g_ep0_irq()
694 		musb->ep0_state = MUSB_EP0_STAGE_IDLE;  in musb_g_ep0_irq()
703 		switch (musb->ep0_state) {  in musb_g_ep0_irq()
705 			musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;  in musb_g_ep0_irq()
708 			musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;  in musb_g_ep0_irq()
712 			    decode_ep0stage(musb->ep0_state));  in musb_g_ep0_irq()
722 	switch (musb->ep0_state) {  in musb_g_ep0_irq()
783 		musb->ep0_state = MUSB_EP0_STAGE_IDLE;  in musb_g_ep0_irq()
794 		musb->ep0_state = MUSB_EP0_STAGE_SETUP;  in musb_g_ep0_irq()
823 			switch (musb->ep0_state) {  in musb_g_ep0_irq()
844 					musb->ep0_state =  in musb_g_ep0_irq()
857 					musb->ep0_state =  in musb_g_ep0_irq()
869 				decode_ep0stage(musb->ep0_state));  in musb_g_ep0_irq()
886 				musb->ep0_state = MUSB_EP0_STAGE_IDLE;  in musb_g_ep0_irq()
906 		musb->ep0_state = MUSB_EP0_STAGE_IDLE;  in musb_g_ep0_irq()
957 	switch (musb->ep0_state) {  in musb_g_ep0_queue()
965 				musb->ep0_state);  in musb_g_ep0_queue()
980 	if (musb->ep0_state == MUSB_EP0_STAGE_TX)  in musb_g_ep0_queue()
984 	else if (musb->ep0_state == MUSB_EP0_STAGE_ACKWAIT) {  in musb_g_ep0_queue()
988 			musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;  in musb_g_ep0_queue()
1043 	switch (musb->ep0_state) {  in musb_g_ep0_halt()
1062 		musb->ep0_state = MUSB_EP0_STAGE_IDLE;  in musb_g_ep0_halt()
1066 		dev_dbg(musb->controller, "ep0 can't halt in state %d\n", musb->ep0_state);  in musb_g_ep0_halt()