Lines Matching refs:dp
28 void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable) in exynos_dp_enable_video_mute() argument
33 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute()
35 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute()
37 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute()
39 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute()
43 void exynos_dp_stop_video(struct exynos_dp_device *dp) in exynos_dp_stop_video() argument
47 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_stop_video()
49 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_stop_video()
52 void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable) in exynos_dp_lane_swap() argument
63 writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP); in exynos_dp_lane_swap()
66 void exynos_dp_init_analog_param(struct exynos_dp_device *dp) in exynos_dp_init_analog_param() argument
71 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1); in exynos_dp_init_analog_param()
74 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2); in exynos_dp_init_analog_param()
77 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3); in exynos_dp_init_analog_param()
81 writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1); in exynos_dp_init_analog_param()
85 writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL); in exynos_dp_init_analog_param()
88 void exynos_dp_init_interrupt(struct exynos_dp_device *dp) in exynos_dp_init_interrupt() argument
91 writel(INT_POL1 | INT_POL0, dp->reg_base + EXYNOS_DP_INT_CTL); in exynos_dp_init_interrupt()
94 writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1); in exynos_dp_init_interrupt()
95 writel(0x4f, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_2); in exynos_dp_init_interrupt()
96 writel(0xe0, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_3); in exynos_dp_init_interrupt()
97 writel(0xe7, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4); in exynos_dp_init_interrupt()
98 writel(0x63, dp->reg_base + EXYNOS_DP_INT_STA); in exynos_dp_init_interrupt()
101 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1); in exynos_dp_init_interrupt()
102 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2); in exynos_dp_init_interrupt()
103 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3); in exynos_dp_init_interrupt()
104 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4); in exynos_dp_init_interrupt()
105 writel(0x00, dp->reg_base + EXYNOS_DP_INT_STA_MASK); in exynos_dp_init_interrupt()
108 void exynos_dp_reset(struct exynos_dp_device *dp) in exynos_dp_reset() argument
112 exynos_dp_stop_video(dp); in exynos_dp_reset()
113 exynos_dp_enable_video_mute(dp, 0); in exynos_dp_reset()
118 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1); in exynos_dp_reset()
123 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); in exynos_dp_reset()
127 exynos_dp_lane_swap(dp, 0); in exynos_dp_reset()
129 writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1); in exynos_dp_reset()
130 writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2); in exynos_dp_reset()
131 writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_3); in exynos_dp_reset()
132 writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_4); in exynos_dp_reset()
134 writel(0x0, dp->reg_base + EXYNOS_DP_PKT_SEND_CTL); in exynos_dp_reset()
135 writel(0x0, dp->reg_base + EXYNOS_DP_HDCP_CTL); in exynos_dp_reset()
137 writel(0x5e, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_L); in exynos_dp_reset()
138 writel(0x1a, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_H); in exynos_dp_reset()
140 writel(0x10, dp->reg_base + EXYNOS_DP_LINK_DEBUG_CTL); in exynos_dp_reset()
142 writel(0x0, dp->reg_base + EXYNOS_DP_PHY_TEST); in exynos_dp_reset()
144 writel(0x0, dp->reg_base + EXYNOS_DP_VIDEO_FIFO_THRD); in exynos_dp_reset()
145 writel(0x20, dp->reg_base + EXYNOS_DP_AUDIO_MARGIN); in exynos_dp_reset()
147 writel(0x4, dp->reg_base + EXYNOS_DP_M_VID_GEN_FILTER_TH); in exynos_dp_reset()
148 writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH); in exynos_dp_reset()
150 writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); in exynos_dp_reset()
153 void exynos_dp_swreset(struct exynos_dp_device *dp) in exynos_dp_swreset() argument
155 writel(RESET_DP_TX, dp->reg_base + EXYNOS_DP_TX_SW_RESET); in exynos_dp_swreset()
158 void exynos_dp_config_interrupt(struct exynos_dp_device *dp) in exynos_dp_config_interrupt() argument
164 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1); in exynos_dp_config_interrupt()
167 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2); in exynos_dp_config_interrupt()
170 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3); in exynos_dp_config_interrupt()
173 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4); in exynos_dp_config_interrupt()
176 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK); in exynos_dp_config_interrupt()
179 enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp) in exynos_dp_get_pll_lock_status() argument
183 reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL); in exynos_dp_get_pll_lock_status()
190 void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable) in exynos_dp_set_pll_power_down() argument
195 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL); in exynos_dp_set_pll_power_down()
197 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL); in exynos_dp_set_pll_power_down()
199 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL); in exynos_dp_set_pll_power_down()
201 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL); in exynos_dp_set_pll_power_down()
205 void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp, in exynos_dp_set_analog_power_down() argument
214 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
216 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
218 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
220 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
225 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
227 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
229 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
231 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
236 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
238 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
240 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
242 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
247 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
249 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
251 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
253 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
258 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
260 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
262 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
264 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
269 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
271 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
273 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
275 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
282 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
284 writel(0x00, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
292 void exynos_dp_init_analog_func(struct exynos_dp_device *dp) in exynos_dp_init_analog_func() argument
297 exynos_dp_set_analog_power_down(dp, POWER_ALL, 0); in exynos_dp_init_analog_func()
300 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1); in exynos_dp_init_analog_func()
302 reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL); in exynos_dp_init_analog_func()
304 writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL); in exynos_dp_init_analog_func()
307 if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { in exynos_dp_init_analog_func()
308 exynos_dp_set_pll_power_down(dp, 0); in exynos_dp_init_analog_func()
310 while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { in exynos_dp_init_analog_func()
313 dev_err(dp->dev, "failed to get pll lock status\n"); in exynos_dp_init_analog_func()
321 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2); in exynos_dp_init_analog_func()
324 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); in exynos_dp_init_analog_func()
327 void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp) in exynos_dp_clear_hotplug_interrupts() argument
332 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4); in exynos_dp_clear_hotplug_interrupts()
335 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA); in exynos_dp_clear_hotplug_interrupts()
338 void exynos_dp_init_hpd(struct exynos_dp_device *dp) in exynos_dp_init_hpd() argument
342 exynos_dp_clear_hotplug_interrupts(dp); in exynos_dp_init_hpd()
344 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3); in exynos_dp_init_hpd()
346 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3); in exynos_dp_init_hpd()
349 enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp) in exynos_dp_get_irq_type() argument
354 reg = readl(dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4); in exynos_dp_get_irq_type()
368 void exynos_dp_reset_aux(struct exynos_dp_device *dp) in exynos_dp_reset_aux() argument
373 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2); in exynos_dp_reset_aux()
375 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); in exynos_dp_reset_aux()
378 void exynos_dp_init_aux(struct exynos_dp_device *dp) in exynos_dp_init_aux() argument
384 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA); in exynos_dp_init_aux()
386 exynos_dp_reset_aux(dp); in exynos_dp_init_aux()
391 writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL) ; in exynos_dp_init_aux()
395 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_DEFER_CTL); in exynos_dp_init_aux()
398 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2); in exynos_dp_init_aux()
400 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); in exynos_dp_init_aux()
403 int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp) in exynos_dp_get_plug_in_status() argument
407 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3); in exynos_dp_get_plug_in_status()
414 void exynos_dp_enable_sw_function(struct exynos_dp_device *dp) in exynos_dp_enable_sw_function() argument
418 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1); in exynos_dp_enable_sw_function()
420 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1); in exynos_dp_enable_sw_function()
423 int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp) in exynos_dp_start_aux_transaction() argument
430 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2); in exynos_dp_start_aux_transaction()
432 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2); in exynos_dp_start_aux_transaction()
435 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA); in exynos_dp_start_aux_transaction()
439 dev_err(dp->dev, "AUX CH command reply failed!\n"); in exynos_dp_start_aux_transaction()
442 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA); in exynos_dp_start_aux_transaction()
447 writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA); in exynos_dp_start_aux_transaction()
450 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA); in exynos_dp_start_aux_transaction()
452 writel(AUX_ERR, dp->reg_base + EXYNOS_DP_INT_STA); in exynos_dp_start_aux_transaction()
457 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_STA); in exynos_dp_start_aux_transaction()
459 dev_err(dp->dev, "AUX CH error happens: %d\n\n", in exynos_dp_start_aux_transaction()
467 int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp, in exynos_dp_write_byte_to_dpcd() argument
478 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); in exynos_dp_write_byte_to_dpcd()
482 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); in exynos_dp_write_byte_to_dpcd()
484 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); in exynos_dp_write_byte_to_dpcd()
486 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); in exynos_dp_write_byte_to_dpcd()
490 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0); in exynos_dp_write_byte_to_dpcd()
498 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); in exynos_dp_write_byte_to_dpcd()
501 retval = exynos_dp_start_aux_transaction(dp); in exynos_dp_write_byte_to_dpcd()
505 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", in exynos_dp_write_byte_to_dpcd()
512 int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp, in exynos_dp_read_byte_from_dpcd() argument
523 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); in exynos_dp_read_byte_from_dpcd()
527 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); in exynos_dp_read_byte_from_dpcd()
529 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); in exynos_dp_read_byte_from_dpcd()
531 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); in exynos_dp_read_byte_from_dpcd()
539 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); in exynos_dp_read_byte_from_dpcd()
542 retval = exynos_dp_start_aux_transaction(dp); in exynos_dp_read_byte_from_dpcd()
546 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", in exynos_dp_read_byte_from_dpcd()
551 reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0); in exynos_dp_read_byte_from_dpcd()
557 int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp, in exynos_dp_write_bytes_to_dpcd() argument
571 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); in exynos_dp_write_bytes_to_dpcd()
584 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); in exynos_dp_write_bytes_to_dpcd()
586 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); in exynos_dp_write_bytes_to_dpcd()
588 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); in exynos_dp_write_bytes_to_dpcd()
593 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0 in exynos_dp_write_bytes_to_dpcd()
604 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); in exynos_dp_write_bytes_to_dpcd()
607 retval = exynos_dp_start_aux_transaction(dp); in exynos_dp_write_bytes_to_dpcd()
611 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", in exynos_dp_write_bytes_to_dpcd()
621 int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp, in exynos_dp_read_bytes_from_dpcd() argument
635 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); in exynos_dp_read_bytes_from_dpcd()
649 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); in exynos_dp_read_bytes_from_dpcd()
651 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); in exynos_dp_read_bytes_from_dpcd()
653 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); in exynos_dp_read_bytes_from_dpcd()
662 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); in exynos_dp_read_bytes_from_dpcd()
665 retval = exynos_dp_start_aux_transaction(dp); in exynos_dp_read_bytes_from_dpcd()
669 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", in exynos_dp_read_bytes_from_dpcd()
675 reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0 in exynos_dp_read_bytes_from_dpcd()
687 int exynos_dp_select_i2c_device(struct exynos_dp_device *dp, in exynos_dp_select_i2c_device() argument
696 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); in exynos_dp_select_i2c_device()
697 writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); in exynos_dp_select_i2c_device()
698 writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); in exynos_dp_select_i2c_device()
701 writel(reg_addr, dp->reg_base + EXYNOS_DP_BUF_DATA_0); in exynos_dp_select_i2c_device()
710 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); in exynos_dp_select_i2c_device()
713 retval = exynos_dp_start_aux_transaction(dp); in exynos_dp_select_i2c_device()
715 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__); in exynos_dp_select_i2c_device()
720 int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp, in exynos_dp_read_byte_from_i2c() argument
732 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); in exynos_dp_read_byte_from_i2c()
735 retval = exynos_dp_select_i2c_device(dp, device_addr, reg_addr); in exynos_dp_read_byte_from_i2c()
746 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); in exynos_dp_read_byte_from_i2c()
749 retval = exynos_dp_start_aux_transaction(dp); in exynos_dp_read_byte_from_i2c()
753 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", in exynos_dp_read_byte_from_i2c()
759 *data = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0); in exynos_dp_read_byte_from_i2c()
764 int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp, in exynos_dp_read_bytes_from_i2c() argument
780 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); in exynos_dp_read_bytes_from_i2c()
783 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2); in exynos_dp_read_bytes_from_i2c()
785 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2); in exynos_dp_read_bytes_from_i2c()
792 retval = exynos_dp_select_i2c_device(dp, in exynos_dp_read_bytes_from_i2c()
806 writel(reg, dp->reg_base + in exynos_dp_read_bytes_from_i2c()
810 retval = exynos_dp_start_aux_transaction(dp); in exynos_dp_read_bytes_from_i2c()
814 dev_dbg(dp->dev, in exynos_dp_read_bytes_from_i2c()
819 reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM); in exynos_dp_read_bytes_from_i2c()
822 dev_err(dp->dev, "Defer: %d\n\n", reg); in exynos_dp_read_bytes_from_i2c()
828 reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0 in exynos_dp_read_bytes_from_i2c()
837 void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype) in exynos_dp_set_link_bandwidth() argument
843 writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET); in exynos_dp_set_link_bandwidth()
846 void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype) in exynos_dp_get_link_bandwidth() argument
850 reg = readl(dp->reg_base + EXYNOS_DP_LINK_BW_SET); in exynos_dp_get_link_bandwidth()
854 void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count) in exynos_dp_set_lane_count() argument
859 writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET); in exynos_dp_set_lane_count()
862 void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count) in exynos_dp_get_lane_count() argument
866 reg = readl(dp->reg_base + EXYNOS_DP_LANE_COUNT_SET); in exynos_dp_get_lane_count()
870 void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable) in exynos_dp_enable_enhanced_mode() argument
875 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4); in exynos_dp_enable_enhanced_mode()
877 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4); in exynos_dp_enable_enhanced_mode()
879 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4); in exynos_dp_enable_enhanced_mode()
881 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4); in exynos_dp_enable_enhanced_mode()
885 void exynos_dp_set_training_pattern(struct exynos_dp_device *dp, in exynos_dp_set_training_pattern() argument
893 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); in exynos_dp_set_training_pattern()
897 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); in exynos_dp_set_training_pattern()
901 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); in exynos_dp_set_training_pattern()
905 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); in exynos_dp_set_training_pattern()
911 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); in exynos_dp_set_training_pattern()
918 void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level) in exynos_dp_set_lane0_pre_emphasis() argument
922 reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); in exynos_dp_set_lane0_pre_emphasis()
925 writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); in exynos_dp_set_lane0_pre_emphasis()
928 void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level) in exynos_dp_set_lane1_pre_emphasis() argument
932 reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); in exynos_dp_set_lane1_pre_emphasis()
935 writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); in exynos_dp_set_lane1_pre_emphasis()
938 void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level) in exynos_dp_set_lane2_pre_emphasis() argument
942 reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL); in exynos_dp_set_lane2_pre_emphasis()
945 writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL); in exynos_dp_set_lane2_pre_emphasis()
948 void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level) in exynos_dp_set_lane3_pre_emphasis() argument
952 reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL); in exynos_dp_set_lane3_pre_emphasis()
955 writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL); in exynos_dp_set_lane3_pre_emphasis()
958 void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp, in exynos_dp_set_lane0_link_training() argument
964 writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); in exynos_dp_set_lane0_link_training()
967 void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp, in exynos_dp_set_lane1_link_training() argument
973 writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); in exynos_dp_set_lane1_link_training()
976 void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp, in exynos_dp_set_lane2_link_training() argument
982 writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL); in exynos_dp_set_lane2_link_training()
985 void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp, in exynos_dp_set_lane3_link_training() argument
991 writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL); in exynos_dp_set_lane3_link_training()
994 u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp) in exynos_dp_get_lane0_link_training() argument
998 reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); in exynos_dp_get_lane0_link_training()
1002 u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp) in exynos_dp_get_lane1_link_training() argument
1006 reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); in exynos_dp_get_lane1_link_training()
1010 u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp) in exynos_dp_get_lane2_link_training() argument
1014 reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL); in exynos_dp_get_lane2_link_training()
1018 u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp) in exynos_dp_get_lane3_link_training() argument
1022 reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL); in exynos_dp_get_lane3_link_training()
1026 void exynos_dp_reset_macro(struct exynos_dp_device *dp) in exynos_dp_reset_macro() argument
1030 reg = readl(dp->reg_base + EXYNOS_DP_PHY_TEST); in exynos_dp_reset_macro()
1032 writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST); in exynos_dp_reset_macro()
1038 writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST); in exynos_dp_reset_macro()
1041 void exynos_dp_init_video(struct exynos_dp_device *dp) in exynos_dp_init_video() argument
1046 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1); in exynos_dp_init_video()
1049 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1); in exynos_dp_init_video()
1052 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2); in exynos_dp_init_video()
1055 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3); in exynos_dp_init_video()
1058 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8); in exynos_dp_init_video()
1061 void exynos_dp_set_video_color_format(struct exynos_dp_device *dp) in exynos_dp_set_video_color_format() argument
1066 reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) | in exynos_dp_set_video_color_format()
1067 (dp->video_info->color_depth << IN_BPC_SHIFT) | in exynos_dp_set_video_color_format()
1068 (dp->video_info->color_space << IN_COLOR_F_SHIFT); in exynos_dp_set_video_color_format()
1069 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2); in exynos_dp_set_video_color_format()
1072 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_3); in exynos_dp_set_video_color_format()
1074 if (dp->video_info->ycbcr_coeff) in exynos_dp_set_video_color_format()
1078 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3); in exynos_dp_set_video_color_format()
1081 int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp) in exynos_dp_is_slave_video_stream_clock_on() argument
1085 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1); in exynos_dp_is_slave_video_stream_clock_on()
1086 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1); in exynos_dp_is_slave_video_stream_clock_on()
1088 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1); in exynos_dp_is_slave_video_stream_clock_on()
1091 dev_dbg(dp->dev, "Input stream clock not detected.\n"); in exynos_dp_is_slave_video_stream_clock_on()
1095 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2); in exynos_dp_is_slave_video_stream_clock_on()
1096 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2); in exynos_dp_is_slave_video_stream_clock_on()
1098 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2); in exynos_dp_is_slave_video_stream_clock_on()
1099 dev_dbg(dp->dev, "wait SYS_CTL_2.\n"); in exynos_dp_is_slave_video_stream_clock_on()
1102 dev_dbg(dp->dev, "Input stream clk is changing\n"); in exynos_dp_is_slave_video_stream_clock_on()
1109 void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp, in exynos_dp_set_video_cr_mn() argument
1117 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4); in exynos_dp_set_video_cr_mn()
1119 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4); in exynos_dp_set_video_cr_mn()
1121 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_0); in exynos_dp_set_video_cr_mn()
1123 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_1); in exynos_dp_set_video_cr_mn()
1125 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_2); in exynos_dp_set_video_cr_mn()
1128 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_0); in exynos_dp_set_video_cr_mn()
1130 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_1); in exynos_dp_set_video_cr_mn()
1132 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_2); in exynos_dp_set_video_cr_mn()
1134 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4); in exynos_dp_set_video_cr_mn()
1136 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4); in exynos_dp_set_video_cr_mn()
1138 writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_0); in exynos_dp_set_video_cr_mn()
1139 writel(0x80, dp->reg_base + EXYNOS_DP_N_VID_1); in exynos_dp_set_video_cr_mn()
1140 writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_2); in exynos_dp_set_video_cr_mn()
1144 void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type) in exynos_dp_set_video_timing_mode() argument
1149 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_set_video_timing_mode()
1151 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_set_video_timing_mode()
1153 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_set_video_timing_mode()
1155 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_set_video_timing_mode()
1159 void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable) in exynos_dp_enable_video_master() argument
1164 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); in exynos_dp_enable_video_master()
1167 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); in exynos_dp_enable_video_master()
1169 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); in exynos_dp_enable_video_master()
1172 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); in exynos_dp_enable_video_master()
1176 void exynos_dp_start_video(struct exynos_dp_device *dp) in exynos_dp_start_video() argument
1180 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_start_video()
1182 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_start_video()
1185 int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp) in exynos_dp_is_video_stream_on() argument
1189 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3); in exynos_dp_is_video_stream_on()
1190 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3); in exynos_dp_is_video_stream_on()
1192 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3); in exynos_dp_is_video_stream_on()
1194 dev_dbg(dp->dev, "Input video stream is not detected.\n"); in exynos_dp_is_video_stream_on()
1201 void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp) in exynos_dp_config_video_slave_mode() argument
1205 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1); in exynos_dp_config_video_slave_mode()
1208 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1); in exynos_dp_config_video_slave_mode()
1210 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_config_video_slave_mode()
1212 reg |= (dp->video_info->interlaced << 2); in exynos_dp_config_video_slave_mode()
1213 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_config_video_slave_mode()
1215 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_config_video_slave_mode()
1217 reg |= (dp->video_info->v_sync_polarity << 1); in exynos_dp_config_video_slave_mode()
1218 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_config_video_slave_mode()
1220 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_config_video_slave_mode()
1222 reg |= (dp->video_info->h_sync_polarity << 0); in exynos_dp_config_video_slave_mode()
1223 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_config_video_slave_mode()
1226 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); in exynos_dp_config_video_slave_mode()
1229 void exynos_dp_enable_scrambling(struct exynos_dp_device *dp) in exynos_dp_enable_scrambling() argument
1233 reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); in exynos_dp_enable_scrambling()
1235 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); in exynos_dp_enable_scrambling()
1238 void exynos_dp_disable_scrambling(struct exynos_dp_device *dp) in exynos_dp_disable_scrambling() argument
1242 reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); in exynos_dp_disable_scrambling()
1244 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); in exynos_dp_disable_scrambling()