Lines Matching refs:reg_base
35 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST); in exynos_mipi_dsi_func_reset()
39 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST); in exynos_mipi_dsi_func_reset()
46 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST); in exynos_mipi_dsi_sw_reset()
50 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST); in exynos_mipi_dsi_sw_reset()
57 reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC); in exynos_mipi_dsi_sw_reset_release()
61 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC); in exynos_mipi_dsi_sw_reset_release()
66 return (readl(dsim->reg_base + EXYNOS_DSIM_INTSRC)) & in exynos_mipi_dsi_get_sw_reset_release()
74 reg = readl(dsim->reg_base + EXYNOS_DSIM_INTMSK); in exynos_mipi_dsi_read_interrupt_mask()
89 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTMSK); in exynos_mipi_dsi_set_interrupt_mask()
97 reg = readl(dsim->reg_base + EXYNOS_DSIM_FIFOCTRL); in exynos_mipi_dsi_init_fifo_pointer()
99 writel(reg & ~(cfg), dsim->reg_base + EXYNOS_DSIM_FIFOCTRL); in exynos_mipi_dsi_init_fifo_pointer()
103 writel(reg, dsim->reg_base + EXYNOS_DSIM_FIFOCTRL); in exynos_mipi_dsi_init_fifo_pointer()
112 writel(DSIM_AFC_CTL(value), dsim->reg_base + EXYNOS_DSIM_PHYACCHR); in exynos_mipi_dsi_set_phy_tunning()
120 reg = readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL); in exynos_mipi_dsi_set_main_stand_by()
127 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL); in exynos_mipi_dsi_set_main_stand_by()
136 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL)) & in exynos_mipi_dsi_set_main_disp_resol()
138 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL); in exynos_mipi_dsi_set_main_disp_resol()
144 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL); in exynos_mipi_dsi_set_main_disp_resol()
152 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MVPORCH)) & in exynos_mipi_dsi_set_main_disp_vporch()
160 writel(reg, dsim->reg_base + EXYNOS_DSIM_MVPORCH); in exynos_mipi_dsi_set_main_disp_vporch()
168 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MHPORCH)) & in exynos_mipi_dsi_set_main_disp_hporch()
173 writel(reg, dsim->reg_base + EXYNOS_DSIM_MHPORCH); in exynos_mipi_dsi_set_main_disp_hporch()
181 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MSYNC)) & in exynos_mipi_dsi_set_main_disp_sync_area()
187 writel(reg, dsim->reg_base + EXYNOS_DSIM_MSYNC); in exynos_mipi_dsi_set_main_disp_sync_area()
195 reg = (readl(dsim->reg_base + EXYNOS_DSIM_SDRESOL)) & in exynos_mipi_dsi_set_sub_disp_resol()
198 writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL); in exynos_mipi_dsi_set_sub_disp_resol()
203 writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL); in exynos_mipi_dsi_set_sub_disp_resol()
206 writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL); in exynos_mipi_dsi_set_sub_disp_resol()
213 unsigned int cfg = (readl(dsim->reg_base + EXYNOS_DSIM_CONFIG)) & in exynos_mipi_dsi_init_config()
225 writel(cfg, dsim->reg_base + EXYNOS_DSIM_CONFIG); in exynos_mipi_dsi_init_config()
231 u32 reg = (readl(dsim->reg_base + EXYNOS_DSIM_CONFIG)) & in exynos_mipi_dsi_display_config()
249 writel(reg, dsim->reg_base + EXYNOS_DSIM_CONFIG); in exynos_mipi_dsi_display_config()
257 reg = readl(dsim->reg_base + EXYNOS_DSIM_CONFIG); in exynos_mipi_dsi_enable_lane()
264 writel(reg, dsim->reg_base + EXYNOS_DSIM_CONFIG); in exynos_mipi_dsi_enable_lane()
276 writel(cfg, dsim->reg_base + EXYNOS_DSIM_CONFIG); in exynos_mipi_dsi_set_data_lane_number()
282 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PHYACCHR); in exynos_mipi_dsi_enable_afc()
291 writel(reg, dsim->reg_base + EXYNOS_DSIM_PHYACCHR); in exynos_mipi_dsi_enable_afc()
297 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) & in exynos_mipi_dsi_enable_pll_bypass()
302 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); in exynos_mipi_dsi_enable_pll_bypass()
308 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL); in exynos_mipi_dsi_set_pll_pms()
312 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); in exynos_mipi_dsi_set_pll_pms()
318 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) & in exynos_mipi_dsi_pll_freq_band()
323 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); in exynos_mipi_dsi_pll_freq_band()
330 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) & in exynos_mipi_dsi_pll_freq()
336 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); in exynos_mipi_dsi_pll_freq()
342 writel(lock_time, dsim->reg_base + EXYNOS_DSIM_PLLTMR); in exynos_mipi_dsi_pll_stable_time()
347 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) & in exynos_mipi_dsi_enable_pll()
352 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); in exynos_mipi_dsi_enable_pll()
358 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) & in exynos_mipi_dsi_set_byte_clock_src()
363 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); in exynos_mipi_dsi_set_byte_clock_src()
369 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) & in exynos_mipi_dsi_enable_byte_clock()
374 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); in exynos_mipi_dsi_enable_byte_clock()
380 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) & in exynos_mipi_dsi_set_esc_clk_prs()
387 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); in exynos_mipi_dsi_set_esc_clk_prs()
393 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL); in exynos_mipi_dsi_enable_esc_clk_on_lane()
401 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); in exynos_mipi_dsi_enable_esc_clk_on_lane()
407 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE)) & in exynos_mipi_dsi_force_dphy_stop_state()
412 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE); in exynos_mipi_dsi_force_dphy_stop_state()
417 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_STATUS); in exynos_mipi_dsi_is_lane_state()
436 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE)) & in exynos_mipi_dsi_set_stop_state_counter()
441 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE); in exynos_mipi_dsi_set_stop_state_counter()
447 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_TIMEOUT)) & in exynos_mipi_dsi_set_bta_timeout()
452 writel(reg, dsim->reg_base + EXYNOS_DSIM_TIMEOUT); in exynos_mipi_dsi_set_bta_timeout()
458 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_TIMEOUT)) & in exynos_mipi_dsi_set_lpdr_timeout()
463 writel(reg, dsim->reg_base + EXYNOS_DSIM_TIMEOUT); in exynos_mipi_dsi_set_lpdr_timeout()
469 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE); in exynos_mipi_dsi_set_cpu_transfer_mode()
476 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE); in exynos_mipi_dsi_set_cpu_transfer_mode()
482 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE); in exynos_mipi_dsi_set_lcdc_transfer_mode()
489 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE); in exynos_mipi_dsi_set_lcdc_transfer_mode()
495 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) & in exynos_mipi_dsi_enable_hs_clock()
500 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); in exynos_mipi_dsi_enable_hs_clock()
506 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PHYACCHR1); in exynos_mipi_dsi_dp_dn_swap()
511 writel(reg, dsim->reg_base + EXYNOS_DSIM_PHYACCHR1); in exynos_mipi_dsi_dp_dn_swap()
517 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) & in exynos_mipi_dsi_hs_zero_ctrl()
522 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); in exynos_mipi_dsi_hs_zero_ctrl()
527 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) & in exynos_mipi_dsi_prep_ctrl()
532 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); in exynos_mipi_dsi_prep_ctrl()
537 return readl(dsim->reg_base + EXYNOS_DSIM_INTSRC); in exynos_mipi_dsi_read_interrupt()
543 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC); in exynos_mipi_dsi_clear_interrupt()
547 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC); in exynos_mipi_dsi_clear_interrupt()
560 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC); in exynos_mipi_dsi_set_interrupt()
567 reg = readl(dsim->reg_base + EXYNOS_DSIM_STATUS); in exynos_mipi_dsi_is_pll_stable()
574 return readl(dsim->reg_base + EXYNOS_DSIM_FIFOCTRL) & ~(0x1f); in exynos_mipi_dsi_get_fifo_state()
582 writel(reg, dsim->reg_base + EXYNOS_DSIM_PKTHDR); in exynos_mipi_dsi_wr_tx_header()
590 writel(reg, dsim->reg_base + EXYNOS_DSIM_PKTHDR); in exynos_mipi_dsi_rd_tx_header()
595 return readl(dsim->reg_base + EXYNOS_DSIM_RXFIFO); in exynos_mipi_dsi_rd_rx_fifo()
600 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC); in _exynos_mipi_dsi_get_frame_done_status()
607 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC); in _exynos_mipi_dsi_clear_frame_done()
609 writel(reg | INTSRC_FRAME_DONE, dsim->reg_base + in _exynos_mipi_dsi_clear_frame_done()
616 writel(tx_data, dsim->reg_base + EXYNOS_DSIM_PAYLOAD); in exynos_mipi_dsi_wr_tx_data()