1355 	int regn, regn_start, regn_stop;  in dsi_pll_calc()  local
1369 	for (regn = regn_start; regn <= regn_stop; ++regn) {  in dsi_pll_calc()
1370 		fint = clkin / regn;  in dsi_pll_calc()
1381 			if (func(regn, regm, fint, pll, data))  in dsi_pll_calc()
1395 	if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)  in dsi_calc_clock_rates()
1408 	cinfo->fint = cinfo->clkin / cinfo->regn;  in dsi_calc_clock_rates()
1463 	dsi->current_cinfo.regn = cinfo->regn;  in dsi_pll_set_clock_div()
1475 			cinfo->regn,  in dsi_pll_set_clock_div()
1506 	l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);  in dsi_pll_set_clock_div()
1703 	seq_printf(s,	"Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);  in dsi_dump_dsidev_clocks()
4775 static bool dsi_cm_calc_pll_cb(int regn, int regm, unsigned long fint,  in dsi_cm_calc_pll_cb()  argument
4780 	ctx->dsi_cinfo.regn = regn;  in dsi_cm_calc_pll_cb()
5072 static bool dsi_vm_calc_pll_cb(int regn, int regm, unsigned long fint,  in dsi_vm_calc_pll_cb()  argument
5077 	ctx->dsi_cinfo.regn = regn;  in dsi_vm_calc_pll_cb()