Lines Matching refs:r
93 u32 r; in hdmi_pll_init() local
100 r = hdmi_read_reg(pll_base, PLLCTRL_CFG1); in hdmi_pll_init()
101 r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */ in hdmi_pll_init()
102 r = FLD_MOD(r, fmt->regn - 1, 8, 1); /* CFG1_PLL_REGN */ in hdmi_pll_init()
104 hdmi_write_reg(pll_base, PLLCTRL_CFG1, r); in hdmi_pll_init()
106 r = hdmi_read_reg(pll_base, PLLCTRL_CFG2); in hdmi_pll_init()
108 r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */ in hdmi_pll_init()
109 r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */ in hdmi_pll_init()
110 r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */ in hdmi_pll_init()
111 r = FLD_MOD(r, fmt->refsel, 22, 21); /* REFSEL */ in hdmi_pll_init()
116 r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */ in hdmi_pll_init()
118 r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */ in hdmi_pll_init()
121 hdmi_write_reg(pll_base, PLLCTRL_CFG2, r); in hdmi_pll_init()
123 r = hdmi_read_reg(pll_base, PLLCTRL_CFG4); in hdmi_pll_init()
124 r = FLD_MOD(r, fmt->regm2, 24, 18); in hdmi_pll_init()
125 r = FLD_MOD(r, fmt->regmf, 17, 0); in hdmi_pll_init()
127 hdmi_write_reg(pll_base, PLLCTRL_CFG4, r); in hdmi_pll_init()
210 u16 r = 0; in ti_hdmi_4xxx_pll_enable() local
212 r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF); in ti_hdmi_4xxx_pll_enable()
213 if (r) in ti_hdmi_4xxx_pll_enable()
214 return r; in ti_hdmi_4xxx_pll_enable()
216 r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_BOTHON_ALLCLKS); in ti_hdmi_4xxx_pll_enable()
217 if (r) in ti_hdmi_4xxx_pll_enable()
218 return r; in ti_hdmi_4xxx_pll_enable()
220 r = hdmi_pll_reset(ip_data); in ti_hdmi_4xxx_pll_enable()
221 if (r) in ti_hdmi_4xxx_pll_enable()
222 return r; in ti_hdmi_4xxx_pll_enable()
224 r = hdmi_pll_init(ip_data); in ti_hdmi_4xxx_pll_enable()
225 if (r) in ti_hdmi_4xxx_pll_enable()
226 return r; in ti_hdmi_4xxx_pll_enable()
239 int r; in hdmi_check_hpd_state() local
246 r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_TXON); in hdmi_check_hpd_state()
248 r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON); in hdmi_check_hpd_state()
250 if (r) { in hdmi_check_hpd_state()
258 return r; in hdmi_check_hpd_state()
272 u16 r = 0; in ti_hdmi_4xxx_phy_enable() local
275 r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON); in ti_hdmi_4xxx_phy_enable()
276 if (r) in ti_hdmi_4xxx_phy_enable()
277 return r; in ti_hdmi_4xxx_phy_enable()
300 r = request_threaded_irq(gpio_to_irq(ip_data->hpd_gpio), in ti_hdmi_4xxx_phy_enable()
304 if (r) { in ti_hdmi_4xxx_phy_enable()
307 return r; in ti_hdmi_4xxx_phy_enable()
310 r = hdmi_check_hpd_state(ip_data); in ti_hdmi_4xxx_phy_enable()
311 if (r) { in ti_hdmi_4xxx_phy_enable()
314 return r; in ti_hdmi_4xxx_phy_enable()
454 int r, l; in ti_hdmi_4xxx_read_edid() local
459 r = hdmi_core_ddc_init(ip_data); in ti_hdmi_4xxx_read_edid()
460 if (r) in ti_hdmi_4xxx_read_edid()
461 return r; in ti_hdmi_4xxx_read_edid()
463 r = hdmi_core_ddc_edid(ip_data, edid, 0); in ti_hdmi_4xxx_read_edid()
464 if (r) in ti_hdmi_4xxx_read_edid()
465 return r; in ti_hdmi_4xxx_read_edid()
470 r = hdmi_core_ddc_edid(ip_data, edid + 0x80, 1); in ti_hdmi_4xxx_read_edid()
471 if (r) in ti_hdmi_4xxx_read_edid()
472 return r; in ti_hdmi_4xxx_read_edid()
550 u32 r = 0; in hdmi_core_video_config() local
554 r = hdmi_read_reg(core_sys_base, HDMI_CORE_CTRL1); in hdmi_core_video_config()
555 r = FLD_MOD(r, HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC, 5, 5); in hdmi_core_video_config()
556 r = FLD_MOD(r, HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC, 4, 4); in hdmi_core_video_config()
557 r = FLD_MOD(r, HDMI_CORE_CTRL1_BSEL_24BITBUS, 2, 2); in hdmi_core_video_config()
558 r = FLD_MOD(r, HDMI_CORE_CTRL1_EDGE_RISINGEDGE, 1, 1); in hdmi_core_video_config()
559 hdmi_write_reg(core_sys_base, HDMI_CORE_CTRL1, r); in hdmi_core_video_config()
565 r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE); in hdmi_core_video_config()
569 r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6); in hdmi_core_video_config()
570 r = FLD_MOD(r, 1, 5, 5); in hdmi_core_video_config()
572 r = FLD_MOD(r, cfg->op_dither_truc, 7, 6); in hdmi_core_video_config()
573 r = FLD_MOD(r, 0, 5, 5); in hdmi_core_video_config()
575 hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r); in hdmi_core_video_config()
578 r = hdmi_read_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL); in hdmi_core_video_config()
579 r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6); in hdmi_core_video_config()
580 r = FLD_MOD(r, cfg->pkt_mode, 5, 3); in hdmi_core_video_config()
581 r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0); in hdmi_core_video_config()
582 hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL, r); in hdmi_core_video_config()
743 u32 r; in hdmi_wp_video_config_interface() local
750 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG); in hdmi_wp_video_config_interface()
751 r = FLD_MOD(r, vsync_pol, 7, 7); in hdmi_wp_video_config_interface()
752 r = FLD_MOD(r, hsync_pol, 6, 6); in hdmi_wp_video_config_interface()
753 r = FLD_MOD(r, ip_data->cfg.timings.interlace, 3, 3); in hdmi_wp_video_config_interface()
754 r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */ in hdmi_wp_video_config_interface()
755 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, r); in hdmi_wp_video_config_interface()
858 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r,\ in ti_hdmi_4xxx_wp_dump() argument
859 hdmi_read_reg(hdmi_wp_base(ip_data), r)) in ti_hdmi_4xxx_wp_dump()
880 #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\ in ti_hdmi_4xxx_pll_dump() argument
881 hdmi_read_reg(hdmi_pll_base(ip_data), r)) in ti_hdmi_4xxx_pll_dump()
897 #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\ in ti_hdmi_4xxx_core_dump() argument
898 hdmi_read_reg(hdmi_core_sys_base(ip_data), r)) in ti_hdmi_4xxx_core_dump()
899 #define DUMPCOREAV(r) seq_printf(s, "%-35s %08x\n", #r,\ in ti_hdmi_4xxx_core_dump() argument
900 hdmi_read_reg(hdmi_av_base(ip_data), r)) in ti_hdmi_4xxx_core_dump()
901 #define DUMPCOREAV2(i, r) seq_printf(s, "%s[%d]%*s %08x\n", #r, i, \ in ti_hdmi_4xxx_core_dump() argument
902 (i < 10) ? 32 - (int)strlen(#r) : 31 - (int)strlen(#r), " ", \ in ti_hdmi_4xxx_core_dump()
903 hdmi_read_reg(hdmi_av_base(ip_data), CORE_REG(i, r))) in ti_hdmi_4xxx_core_dump()
1017 #define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\ in ti_hdmi_4xxx_phy_dump() argument
1018 hdmi_read_reg(hdmi_phy_base(ip_data), r)) in ti_hdmi_4xxx_phy_dump()
1030 u32 r; in ti_hdmi_4xxx_wp_audio_config_format() local
1034 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG); in ti_hdmi_4xxx_wp_audio_config_format()
1035 r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24); in ti_hdmi_4xxx_wp_audio_config_format()
1036 r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16); in ti_hdmi_4xxx_wp_audio_config_format()
1037 r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5); in ti_hdmi_4xxx_wp_audio_config_format()
1038 r = FLD_MOD(r, aud_fmt->type, 4, 4); in ti_hdmi_4xxx_wp_audio_config_format()
1039 r = FLD_MOD(r, aud_fmt->justification, 3, 3); in ti_hdmi_4xxx_wp_audio_config_format()
1040 r = FLD_MOD(r, aud_fmt->sample_order, 2, 2); in ti_hdmi_4xxx_wp_audio_config_format()
1041 r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1); in ti_hdmi_4xxx_wp_audio_config_format()
1042 r = FLD_MOD(r, aud_fmt->sample_size, 0, 0); in ti_hdmi_4xxx_wp_audio_config_format()
1043 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG, r); in ti_hdmi_4xxx_wp_audio_config_format()
1049 u32 r; in ti_hdmi_4xxx_wp_audio_config_dma() local
1053 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2); in ti_hdmi_4xxx_wp_audio_config_dma()
1054 r = FLD_MOD(r, aud_dma->transfer_size, 15, 8); in ti_hdmi_4xxx_wp_audio_config_dma()
1055 r = FLD_MOD(r, aud_dma->block_size, 7, 0); in ti_hdmi_4xxx_wp_audio_config_dma()
1056 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2, r); in ti_hdmi_4xxx_wp_audio_config_dma()
1058 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL); in ti_hdmi_4xxx_wp_audio_config_dma()
1059 r = FLD_MOD(r, aud_dma->mode, 9, 9); in ti_hdmi_4xxx_wp_audio_config_dma()
1060 r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0); in ti_hdmi_4xxx_wp_audio_config_dma()
1061 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL, r); in ti_hdmi_4xxx_wp_audio_config_dma()
1067 u32 r; in ti_hdmi_4xxx_core_audio_config() local
1096 r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL); in ti_hdmi_4xxx_core_audio_config()
1101 r = FLD_MOD(r, 0, 2, 2); in ti_hdmi_4xxx_core_audio_config()
1103 r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1); in ti_hdmi_4xxx_core_audio_config()
1104 r = FLD_MOD(r, cfg->cts_mode, 0, 0); in ti_hdmi_4xxx_core_audio_config()
1105 hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r); in ti_hdmi_4xxx_core_audio_config()
1134 r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL); in ti_hdmi_4xxx_core_audio_config()
1135 r = FLD_MOD(r, cfg->i2s_cfg.sck_edge_mode, 6, 6); in ti_hdmi_4xxx_core_audio_config()
1136 r = FLD_MOD(r, cfg->i2s_cfg.vbit, 4, 4); in ti_hdmi_4xxx_core_audio_config()
1137 r = FLD_MOD(r, cfg->i2s_cfg.justification, 2, 2); in ti_hdmi_4xxx_core_audio_config()
1138 r = FLD_MOD(r, cfg->i2s_cfg.direction, 1, 1); in ti_hdmi_4xxx_core_audio_config()
1139 r = FLD_MOD(r, cfg->i2s_cfg.shift, 0, 0); in ti_hdmi_4xxx_core_audio_config()
1140 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL, r); in ti_hdmi_4xxx_core_audio_config()
1147 r = hdmi_read_reg(av_base, HDMI_CORE_AV_AUD_MODE); in ti_hdmi_4xxx_core_audio_config()
1148 r = FLD_MOD(r, cfg->i2s_cfg.active_sds, 7, 4); in ti_hdmi_4xxx_core_audio_config()
1149 r = FLD_MOD(r, cfg->en_dsd_audio, 3, 3); in ti_hdmi_4xxx_core_audio_config()
1150 r = FLD_MOD(r, cfg->en_parallel_aud_input, 2, 2); in ti_hdmi_4xxx_core_audio_config()
1151 r = FLD_MOD(r, cfg->en_spdif, 1, 1); in ti_hdmi_4xxx_core_audio_config()
1152 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_MODE, r); in ti_hdmi_4xxx_core_audio_config()