119 #define K0		26  macro
144 	uasm_i_dmtc0(&p, K0, C0_DESAVE);  in octeon_wdt_build_stage1()
146 	uasm_i_mfc0(&p, K0, C0_STATUS);  in octeon_wdt_build_stage1()
148 	uasm_il_bbit0(&p, &r, K0, ilog2(ST0_NMI), label_enter_bootloader);  in octeon_wdt_build_stage1()
151 	uasm_i_ori(&p, K0, K0, ST0_UX | ST0_SX | ST0_KX);  in octeon_wdt_build_stage1()
152 	uasm_i_mtc0(&p, K0, C0_STATUS);  in octeon_wdt_build_stage1()
155 	uasm_i_mfc0(&p, K0, C0_EBASE);  in octeon_wdt_build_stage1()
157 	uasm_i_andi(&p, K0, K0, 0xf);  in octeon_wdt_build_stage1()
159 	uasm_i_dsll_safe(&p, K0, K0, 3 + 16);  in octeon_wdt_build_stage1()
160 	uasm_i_ori(&p, K0, K0, 0x8001);  in octeon_wdt_build_stage1()
161 	uasm_i_dsll_safe(&p, K0, K0, 16);  in octeon_wdt_build_stage1()
162 	uasm_i_ori(&p, K0, K0, 0x0700);  in octeon_wdt_build_stage1()
163 	uasm_i_drotr_safe(&p, K0, K0, 32);  in octeon_wdt_build_stage1()
170 	uasm_i_ld(&p, K0, 0x500, K0);  in octeon_wdt_build_stage1()
175 	uasm_il_bbit0(&p, &r, K0, 1, label_enter_bootloader);  in octeon_wdt_build_stage1()
183 	uasm_i_dmfc0(&p, K0, C0_CVMMEMCTL);  in octeon_wdt_build_stage1()
185 	uasm_i_dins(&p, K0, 0, 0, 6);  in octeon_wdt_build_stage1()
187 	uasm_i_ori(&p, K0, K0, 0x1c0 | 54);  in octeon_wdt_build_stage1()
189 	uasm_i_dmtc0(&p, K0, C0_CVMMEMCTL);  in octeon_wdt_build_stage1()
192 	UASM_i_LA(&p, K0, (long)octeon_wdt_nmi_stage2);  in octeon_wdt_build_stage1()
193 	uasm_i_jr(&p, K0);  in octeon_wdt_build_stage1()
194 	uasm_i_dmfc0(&p, K0, C0_DESAVE);  in octeon_wdt_build_stage1()
199 	UASM_i_LA(&p, K0, (long)octeon_bootloader_entry_addr);  in octeon_wdt_build_stage1()
200 	uasm_i_jr(&p, K0);  in octeon_wdt_build_stage1()
201 	uasm_i_dmfc0(&p, K0, C0_DESAVE);  in octeon_wdt_build_stage1()