Lines Matching refs:V4L2_DV_VSYNC_POS_POL
80 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
89 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
97 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
105 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
113 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
121 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
129 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
137 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
145 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
153 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
161 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
170 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
188 V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \
195 V4L2_INIT_BT_TIMINGS(720, 400, 0, V4L2_DV_VSYNC_POS_POL, \
228 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
236 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
244 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
252 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
260 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
276 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
284 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
307 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
315 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
332 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
350 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
357 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
364 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
387 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
394 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
401 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
417 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
425 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
442 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
450 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
458 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
474 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
490 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
498 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
514 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
521 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
528 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
552 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
559 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
566 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
582 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
591 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
599 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
607 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
615 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
623 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
647 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
654 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
661 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
676 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
683 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
698 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
705 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
731 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
738 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
745 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
760 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
767 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
783 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
799 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
806 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
813 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
829 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \