38 	outb(((unsigned char) addr), 0x390);	/* MT-0002-PC ASIC address */  in trix_read()
44 	outb(((unsigned char) addr), 0x390);	/* MT-0002-PC ASIC address */  in trix_write()
45 	outb(((unsigned char) data), 0x391);	/* MT-0002-PC ASIC data */  in trix_write()
56 	outb((0x01), base + 6);	/* Clear the internal data pointer */  in download_boot()
57 	outb((0x00), base + 6);	/* Restart */  in download_boot()
63 	outb((0x01), base + 6);	/* Clear the internal data pointer */  in download_boot()
64 	outb((0x1A), 0x390);	/* Select RAM download/upload port */  in download_boot()
67 		outb((trix_boot[i]), 0x391);  in download_boot()
69 		outb((0x00), 0x391);  in download_boot()
70 	outb((0x00), base + 6);	/* Reset */  in download_boot()
71 	outb((0x50), 0x390);	/* ?????? */  in download_boot()
228 	outb((bits | 0x40), config_port);  in init_trix_wss()
246 	outb((bits), config_port);	/* Write IRQ+DMA setup */  in init_trix_wss()