Lines Matching refs:data
32 int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate, in tegra_asoc_utils_set_rate() argument
44 if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20) in tegra_asoc_utils_set_rate()
46 else if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA30) in tegra_asoc_utils_set_rate()
57 if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20) in tegra_asoc_utils_set_rate()
59 else if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA30) in tegra_asoc_utils_set_rate()
68 clk_change = ((new_baseclock != data->set_baseclock) || in tegra_asoc_utils_set_rate()
69 (mclk != data->set_mclk)); in tegra_asoc_utils_set_rate()
73 data->set_baseclock = 0; in tegra_asoc_utils_set_rate()
74 data->set_mclk = 0; in tegra_asoc_utils_set_rate()
76 clk_disable_unprepare(data->clk_cdev1); in tegra_asoc_utils_set_rate()
77 clk_disable_unprepare(data->clk_pll_a_out0); in tegra_asoc_utils_set_rate()
78 clk_disable_unprepare(data->clk_pll_a); in tegra_asoc_utils_set_rate()
80 err = clk_set_rate(data->clk_pll_a, new_baseclock); in tegra_asoc_utils_set_rate()
82 dev_err(data->dev, "Can't set pll_a rate: %d\n", err); in tegra_asoc_utils_set_rate()
86 err = clk_set_rate(data->clk_pll_a_out0, mclk); in tegra_asoc_utils_set_rate()
88 dev_err(data->dev, "Can't set pll_a_out0 rate: %d\n", err); in tegra_asoc_utils_set_rate()
94 err = clk_prepare_enable(data->clk_pll_a); in tegra_asoc_utils_set_rate()
96 dev_err(data->dev, "Can't enable pll_a: %d\n", err); in tegra_asoc_utils_set_rate()
100 err = clk_prepare_enable(data->clk_pll_a_out0); in tegra_asoc_utils_set_rate()
102 dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err); in tegra_asoc_utils_set_rate()
106 err = clk_prepare_enable(data->clk_cdev1); in tegra_asoc_utils_set_rate()
108 dev_err(data->dev, "Can't enable cdev1: %d\n", err); in tegra_asoc_utils_set_rate()
112 data->set_baseclock = new_baseclock; in tegra_asoc_utils_set_rate()
113 data->set_mclk = mclk; in tegra_asoc_utils_set_rate()
119 int tegra_asoc_utils_set_ac97_rate(struct tegra_asoc_utils_data *data) in tegra_asoc_utils_set_ac97_rate() argument
125 clk_disable_unprepare(data->clk_cdev1); in tegra_asoc_utils_set_ac97_rate()
126 clk_disable_unprepare(data->clk_pll_a_out0); in tegra_asoc_utils_set_ac97_rate()
127 clk_disable_unprepare(data->clk_pll_a); in tegra_asoc_utils_set_ac97_rate()
133 err = clk_set_rate(data->clk_pll_a, pll_rate); in tegra_asoc_utils_set_ac97_rate()
135 dev_err(data->dev, "Can't set pll_a rate: %d\n", err); in tegra_asoc_utils_set_ac97_rate()
139 err = clk_set_rate(data->clk_pll_a_out0, ac97_rate); in tegra_asoc_utils_set_ac97_rate()
141 dev_err(data->dev, "Can't set pll_a_out0 rate: %d\n", err); in tegra_asoc_utils_set_ac97_rate()
147 err = clk_prepare_enable(data->clk_pll_a); in tegra_asoc_utils_set_ac97_rate()
149 dev_err(data->dev, "Can't enable pll_a: %d\n", err); in tegra_asoc_utils_set_ac97_rate()
153 err = clk_prepare_enable(data->clk_pll_a_out0); in tegra_asoc_utils_set_ac97_rate()
155 dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err); in tegra_asoc_utils_set_ac97_rate()
159 err = clk_prepare_enable(data->clk_cdev1); in tegra_asoc_utils_set_ac97_rate()
161 dev_err(data->dev, "Can't enable cdev1: %d\n", err); in tegra_asoc_utils_set_ac97_rate()
165 data->set_baseclock = pll_rate; in tegra_asoc_utils_set_ac97_rate()
166 data->set_mclk = ac97_rate; in tegra_asoc_utils_set_ac97_rate()
172 int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data, in tegra_asoc_utils_init() argument
178 data->dev = dev; in tegra_asoc_utils_init()
181 data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA20; in tegra_asoc_utils_init()
183 data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA30; in tegra_asoc_utils_init()
185 data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA114; in tegra_asoc_utils_init()
188 dev_err(data->dev, "SoC unknown to Tegra ASoC utils\n"); in tegra_asoc_utils_init()
193 data->clk_pll_a = clk_get(dev, "pll_a"); in tegra_asoc_utils_init()
195 data->clk_pll_a = clk_get_sys(NULL, "pll_a"); in tegra_asoc_utils_init()
196 if (IS_ERR(data->clk_pll_a)) { in tegra_asoc_utils_init()
197 dev_err(data->dev, "Can't retrieve clk pll_a\n"); in tegra_asoc_utils_init()
198 ret = PTR_ERR(data->clk_pll_a); in tegra_asoc_utils_init()
203 data->clk_pll_a_out0 = clk_get(dev, "pll_a_out0"); in tegra_asoc_utils_init()
205 data->clk_pll_a_out0 = clk_get_sys(NULL, "pll_a_out0"); in tegra_asoc_utils_init()
206 if (IS_ERR(data->clk_pll_a_out0)) { in tegra_asoc_utils_init()
207 dev_err(data->dev, "Can't retrieve clk pll_a_out0\n"); in tegra_asoc_utils_init()
208 ret = PTR_ERR(data->clk_pll_a_out0); in tegra_asoc_utils_init()
213 data->clk_cdev1 = clk_get(dev, "mclk"); in tegra_asoc_utils_init()
214 else if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20) in tegra_asoc_utils_init()
215 data->clk_cdev1 = clk_get_sys(NULL, "cdev1"); in tegra_asoc_utils_init()
217 data->clk_cdev1 = clk_get_sys("extern1", NULL); in tegra_asoc_utils_init()
218 if (IS_ERR(data->clk_cdev1)) { in tegra_asoc_utils_init()
219 dev_err(data->dev, "Can't retrieve clk cdev1\n"); in tegra_asoc_utils_init()
220 ret = PTR_ERR(data->clk_cdev1); in tegra_asoc_utils_init()
224 ret = tegra_asoc_utils_set_rate(data, 44100, 256 * 44100); in tegra_asoc_utils_init()
231 clk_put(data->clk_cdev1); in tegra_asoc_utils_init()
233 clk_put(data->clk_pll_a_out0); in tegra_asoc_utils_init()
235 clk_put(data->clk_pll_a); in tegra_asoc_utils_init()
241 void tegra_asoc_utils_fini(struct tegra_asoc_utils_data *data) in tegra_asoc_utils_fini() argument
243 clk_put(data->clk_cdev1); in tegra_asoc_utils_fini()
244 clk_put(data->clk_pll_a_out0); in tegra_asoc_utils_fini()
245 clk_put(data->clk_pll_a); in tegra_asoc_utils_fini()