1 /*
2 * AM33XX CM offset macros
3 *
4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
5 * Vaibhav Hiremath <hvaibhav@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
18 #define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
19
20 #include "common.h"
21
22 #include "cm.h"
23 #include "cm-regbits-33xx.h"
24 #include "iomap.h"
25
26 /* CM base address */
27 #define AM33XX_CM_BASE 0x44e00000
28
29 #define AM33XX_CM_REGADDR(inst, reg) \
30 AM33XX_L4_WK_IO_ADDRESS(AM33XX_CM_BASE + (inst) + (reg))
31
32 /* CM instances */
33 #define AM33XX_CM_PER_MOD 0x0000
34 #define AM33XX_CM_WKUP_MOD 0x0400
35 #define AM33XX_CM_DPLL_MOD 0x0500
36 #define AM33XX_CM_MPU_MOD 0x0600
37 #define AM33XX_CM_DEVICE_MOD 0x0700
38 #define AM33XX_CM_RTC_MOD 0x0800
39 #define AM33XX_CM_GFX_MOD 0x0900
40 #define AM33XX_CM_CEFUSE_MOD 0x0A00
41
42 /* CM */
43
44 /* CM.PER_CM register offsets */
45 #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000
46 #define AM33XX_CM_PER_L4LS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000)
47 #define AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET 0x0004
48 #define AM33XX_CM_PER_L3S_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0004)
49 #define AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET 0x0008
50 #define AM33XX_CM_PER_L4FW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008)
51 #define AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET 0x000c
52 #define AM33XX_CM_PER_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c)
53 #define AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET 0x0014
54 #define AM33XX_CM_PER_CPGMAC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0014)
55 #define AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET 0x0018
56 #define AM33XX_CM_PER_LCDC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0018)
57 #define AM33XX_CM_PER_USB0_CLKCTRL_OFFSET 0x001c
58 #define AM33XX_CM_PER_USB0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x001c)
59 #define AM33XX_CM_PER_MLB_CLKCTRL_OFFSET 0x0020
60 #define AM33XX_CM_PER_MLB_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0020)
61 #define AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET 0x0024
62 #define AM33XX_CM_PER_TPTC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0024)
63 #define AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET 0x0028
64 #define AM33XX_CM_PER_EMIF_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028)
65 #define AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x002c
66 #define AM33XX_CM_PER_OCMCRAM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x002c)
67 #define AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET 0x0030
68 #define AM33XX_CM_PER_GPMC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0030)
69 #define AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET 0x0034
70 #define AM33XX_CM_PER_MCASP0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0034)
71 #define AM33XX_CM_PER_UART5_CLKCTRL_OFFSET 0x0038
72 #define AM33XX_CM_PER_UART5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0038)
73 #define AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x003c
74 #define AM33XX_CM_PER_MMC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x003c)
75 #define AM33XX_CM_PER_ELM_CLKCTRL_OFFSET 0x0040
76 #define AM33XX_CM_PER_ELM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0040)
77 #define AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET 0x0044
78 #define AM33XX_CM_PER_I2C2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0044)
79 #define AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET 0x0048
80 #define AM33XX_CM_PER_I2C1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0048)
81 #define AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x004c
82 #define AM33XX_CM_PER_SPI0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x004c)
83 #define AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0050
84 #define AM33XX_CM_PER_SPI1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0050)
85 #define AM33XX_CM_PER_SPI2_CLKCTRL_OFFSET 0x0054
86 #define AM33XX_CM_PER_SPI2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0054)
87 #define AM33XX_CM_PER_SPI3_CLKCTRL_OFFSET 0x0058
88 #define AM33XX_CM_PER_SPI3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0058)
89 #define AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET 0x0060
90 #define AM33XX_CM_PER_L4LS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0060)
91 #define AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET 0x0064
92 #define AM33XX_CM_PER_L4FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0064)
93 #define AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET 0x0068
94 #define AM33XX_CM_PER_MCASP1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0068)
95 #define AM33XX_CM_PER_UART1_CLKCTRL_OFFSET 0x006c
96 #define AM33XX_CM_PER_UART1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x006c)
97 #define AM33XX_CM_PER_UART2_CLKCTRL_OFFSET 0x0070
98 #define AM33XX_CM_PER_UART2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0070)
99 #define AM33XX_CM_PER_UART3_CLKCTRL_OFFSET 0x0074
100 #define AM33XX_CM_PER_UART3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0074)
101 #define AM33XX_CM_PER_UART4_CLKCTRL_OFFSET 0x0078
102 #define AM33XX_CM_PER_UART4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0078)
103 #define AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET 0x007c
104 #define AM33XX_CM_PER_TIMER7_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x007c)
105 #define AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET 0x0080
106 #define AM33XX_CM_PER_TIMER2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0080)
107 #define AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET 0x0084
108 #define AM33XX_CM_PER_TIMER3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0084)
109 #define AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET 0x0088
110 #define AM33XX_CM_PER_TIMER4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0088)
111 #define AM33XX_CM_PER_MCASP2_CLKCTRL_OFFSET 0x008c
112 #define AM33XX_CM_PER_MCASP2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x008c)
113 #define AM33XX_CM_PER_RNG_CLKCTRL_OFFSET 0x0090
114 #define AM33XX_CM_PER_RNG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0090)
115 #define AM33XX_CM_PER_AES0_CLKCTRL_OFFSET 0x0094
116 #define AM33XX_CM_PER_AES0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0094)
117 #define AM33XX_CM_PER_AES1_CLKCTRL_OFFSET 0x0098
118 #define AM33XX_CM_PER_AES1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0098)
119 #define AM33XX_CM_PER_DES_CLKCTRL_OFFSET 0x009c
120 #define AM33XX_CM_PER_DES_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x009c)
121 #define AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET 0x00a0
122 #define AM33XX_CM_PER_SHA0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a0)
123 #define AM33XX_CM_PER_PKA_CLKCTRL_OFFSET 0x00a4
124 #define AM33XX_CM_PER_PKA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a4)
125 #define AM33XX_CM_PER_GPIO6_CLKCTRL_OFFSET 0x00a8
126 #define AM33XX_CM_PER_GPIO6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a8)
127 #define AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET 0x00ac
128 #define AM33XX_CM_PER_GPIO1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ac)
129 #define AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET 0x00b0
130 #define AM33XX_CM_PER_GPIO2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b0)
131 #define AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET 0x00b4
132 #define AM33XX_CM_PER_GPIO3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b4)
133 #define AM33XX_CM_PER_GPIO4_CLKCTRL_OFFSET 0x00b8
134 #define AM33XX_CM_PER_GPIO4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b8)
135 #define AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET 0x00bc
136 #define AM33XX_CM_PER_TPCC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00bc)
137 #define AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET 0x00c0
138 #define AM33XX_CM_PER_DCAN0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c0)
139 #define AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET 0x00c4
140 #define AM33XX_CM_PER_DCAN1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c4)
141 #define AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET 0x00cc
142 #define AM33XX_CM_PER_EPWMSS1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00cc)
143 #define AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET 0x00d0
144 #define AM33XX_CM_PER_EMIF_FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d0)
145 #define AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET 0x00d4
146 #define AM33XX_CM_PER_EPWMSS0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d4)
147 #define AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET 0x00d8
148 #define AM33XX_CM_PER_EPWMSS2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d8)
149 #define AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET 0x00dc
150 #define AM33XX_CM_PER_L3_INSTR_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00dc)
151 #define AM33XX_CM_PER_L3_CLKCTRL_OFFSET 0x00e0
152 #define AM33XX_CM_PER_L3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e0)
153 #define AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET 0x00e4
154 #define AM33XX_CM_PER_IEEE5000_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e4)
155 #define AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET 0x00e8
156 #define AM33XX_CM_PER_PRUSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e8)
157 #define AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET 0x00ec
158 #define AM33XX_CM_PER_TIMER5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ec)
159 #define AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET 0x00f0
160 #define AM33XX_CM_PER_TIMER6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f0)
161 #define AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET 0x00f4
162 #define AM33XX_CM_PER_MMC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f4)
163 #define AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET 0x00f8
164 #define AM33XX_CM_PER_MMC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f8)
165 #define AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET 0x00fc
166 #define AM33XX_CM_PER_TPTC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00fc)
167 #define AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET 0x0100
168 #define AM33XX_CM_PER_TPTC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0100)
169 #define AM33XX_CM_PER_GPIO5_CLKCTRL_OFFSET 0x0104
170 #define AM33XX_CM_PER_GPIO5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0104)
171 #define AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x010c
172 #define AM33XX_CM_PER_SPINLOCK_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x010c)
173 #define AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x0110
174 #define AM33XX_CM_PER_MAILBOX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0110)
175 #define AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET 0x011c
176 #define AM33XX_CM_PER_L4HS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x011c)
177 #define AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET 0x0120
178 #define AM33XX_CM_PER_L4HS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0120)
179 #define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL_OFFSET 0x0124
180 #define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0124)
181 #define AM33XX_CM_PER_SLV_EXPS_CLKCTRL_OFFSET 0x0128
182 #define AM33XX_CM_PER_SLV_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0128)
183 #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET 0x012c
184 #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x012c)
185 #define AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET 0x0130
186 #define AM33XX_CM_PER_OCPWP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0130)
187 #define AM33XX_CM_PER_MAILBOX1_CLKCTRL_OFFSET 0x0134
188 #define AM33XX_CM_PER_MAILBOX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0134)
189 #define AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET 0x0140
190 #define AM33XX_CM_PER_PRUSS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0140)
191 #define AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET 0x0144
192 #define AM33XX_CM_PER_CPSW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0144)
193 #define AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET 0x0148
194 #define AM33XX_CM_PER_LCDC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0148)
195 #define AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET 0x014c
196 #define AM33XX_CM_PER_CLKDIV32K_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x014c)
197 #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET 0x0150
198 #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0150)
199
200 /* CM.WKUP_CM register offsets */
201 #define AM33XX_CM_WKUP_CLKSTCTRL_OFFSET 0x0000
202 #define AM33XX_CM_WKUP_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0000)
203 #define AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET 0x0004
204 #define AM33XX_CM_WKUP_CONTROL_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0004)
205 #define AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET 0x0008
206 #define AM33XX_CM_WKUP_GPIO0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0008)
207 #define AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x000c
208 #define AM33XX_CM_WKUP_L4WKUP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x000c)
209 #define AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET 0x0010
210 #define AM33XX_CM_WKUP_TIMER0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0010)
211 #define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET 0x0014
212 #define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0014)
213 #define AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET 0x0018
214 #define AM33XX_CM_L3_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0018)
215 #define AM33XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x001c
216 #define AM33XX_CM_AUTOIDLE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x001c)
217 #define AM33XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0020
218 #define AM33XX_CM_IDLEST_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0020)
219 #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0024
220 #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0024)
221 #define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x0028
222 #define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0028)
223 #define AM33XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x002c
224 #define AM33XX_CM_CLKSEL_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x002c)
225 #define AM33XX_CM_AUTOIDLE_DPLL_DDR_OFFSET 0x0030
226 #define AM33XX_CM_AUTOIDLE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0030)
227 #define AM33XX_CM_IDLEST_DPLL_DDR_OFFSET 0x0034
228 #define AM33XX_CM_IDLEST_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0034)
229 #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET 0x0038
230 #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0038)
231 #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET 0x003c
232 #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x003c)
233 #define AM33XX_CM_CLKSEL_DPLL_DDR_OFFSET 0x0040
234 #define AM33XX_CM_CLKSEL_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0040)
235 #define AM33XX_CM_AUTOIDLE_DPLL_DISP_OFFSET 0x0044
236 #define AM33XX_CM_AUTOIDLE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0044)
237 #define AM33XX_CM_IDLEST_DPLL_DISP_OFFSET 0x0048
238 #define AM33XX_CM_IDLEST_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0048)
239 #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP_OFFSET 0x004c
240 #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x004c)
241 #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP_OFFSET 0x0050
242 #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0050)
243 #define AM33XX_CM_CLKSEL_DPLL_DISP_OFFSET 0x0054
244 #define AM33XX_CM_CLKSEL_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0054)
245 #define AM33XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0058
246 #define AM33XX_CM_AUTOIDLE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0058)
247 #define AM33XX_CM_IDLEST_DPLL_CORE_OFFSET 0x005c
248 #define AM33XX_CM_IDLEST_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x005c)
249 #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0060
250 #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0060)
251 #define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x0064
252 #define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0064)
253 #define AM33XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x0068
254 #define AM33XX_CM_CLKSEL_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0068)
255 #define AM33XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x006c
256 #define AM33XX_CM_AUTOIDLE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x006c)
257 #define AM33XX_CM_IDLEST_DPLL_PER_OFFSET 0x0070
258 #define AM33XX_CM_IDLEST_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0070)
259 #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0074
260 #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0074)
261 #define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x0078
262 #define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0078)
263 #define AM33XX_CM_CLKDCOLDO_DPLL_PER_OFFSET 0x007c
264 #define AM33XX_CM_CLKDCOLDO_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x007c)
265 #define AM33XX_CM_DIV_M4_DPLL_CORE_OFFSET 0x0080
266 #define AM33XX_CM_DIV_M4_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0080)
267 #define AM33XX_CM_DIV_M5_DPLL_CORE_OFFSET 0x0084
268 #define AM33XX_CM_DIV_M5_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0084)
269 #define AM33XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0088
270 #define AM33XX_CM_CLKMODE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0088)
271 #define AM33XX_CM_CLKMODE_DPLL_PER_OFFSET 0x008c
272 #define AM33XX_CM_CLKMODE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x008c)
273 #define AM33XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0090
274 #define AM33XX_CM_CLKMODE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0090)
275 #define AM33XX_CM_CLKMODE_DPLL_DDR_OFFSET 0x0094
276 #define AM33XX_CM_CLKMODE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0094)
277 #define AM33XX_CM_CLKMODE_DPLL_DISP_OFFSET 0x0098
278 #define AM33XX_CM_CLKMODE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0098)
279 #define AM33XX_CM_CLKSEL_DPLL_PERIPH_OFFSET 0x009c
280 #define AM33XX_CM_CLKSEL_DPLL_PERIPH AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x009c)
281 #define AM33XX_CM_DIV_M2_DPLL_DDR_OFFSET 0x00a0
282 #define AM33XX_CM_DIV_M2_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a0)
283 #define AM33XX_CM_DIV_M2_DPLL_DISP_OFFSET 0x00a4
284 #define AM33XX_CM_DIV_M2_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a4)
285 #define AM33XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x00a8
286 #define AM33XX_CM_DIV_M2_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a8)
287 #define AM33XX_CM_DIV_M2_DPLL_PER_OFFSET 0x00ac
288 #define AM33XX_CM_DIV_M2_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00ac)
289 #define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET 0x00b0
290 #define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b0)
291 #define AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET 0x00b4
292 #define AM33XX_CM_WKUP_UART0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b4)
293 #define AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET 0x00b8
294 #define AM33XX_CM_WKUP_I2C0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b8)
295 #define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET 0x00bc
296 #define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00bc)
297 #define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET 0x00c0
298 #define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c0)
299 #define AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x00c4
300 #define AM33XX_CM_WKUP_TIMER1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c4)
301 #define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET 0x00c8
302 #define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c8)
303 #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET 0x00cc
304 #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00cc)
305 #define AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET 0x00d0
306 #define AM33XX_CM_WKUP_WDT0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d0)
307 #define AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x00d4
308 #define AM33XX_CM_WKUP_WDT1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d4)
309 #define AM33XX_CM_DIV_M6_DPLL_CORE_OFFSET 0x00d8
310 #define AM33XX_CM_DIV_M6_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d8)
311
312 /* CM.DPLL_CM register offsets */
313 #define AM33XX_CLKSEL_TIMER7_CLK_OFFSET 0x0004
314 #define AM33XX_CLKSEL_TIMER7_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0004)
315 #define AM33XX_CLKSEL_TIMER2_CLK_OFFSET 0x0008
316 #define AM33XX_CLKSEL_TIMER2_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0008)
317 #define AM33XX_CLKSEL_TIMER3_CLK_OFFSET 0x000c
318 #define AM33XX_CLKSEL_TIMER3_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x000c)
319 #define AM33XX_CLKSEL_TIMER4_CLK_OFFSET 0x0010
320 #define AM33XX_CLKSEL_TIMER4_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0010)
321 #define AM33XX_CM_MAC_CLKSEL_OFFSET 0x0014
322 #define AM33XX_CM_MAC_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0014)
323 #define AM33XX_CLKSEL_TIMER5_CLK_OFFSET 0x0018
324 #define AM33XX_CLKSEL_TIMER5_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0018)
325 #define AM33XX_CLKSEL_TIMER6_CLK_OFFSET 0x001c
326 #define AM33XX_CLKSEL_TIMER6_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x001c)
327 #define AM33XX_CM_CPTS_RFT_CLKSEL_OFFSET 0x0020
328 #define AM33XX_CM_CPTS_RFT_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0020)
329 #define AM33XX_CLKSEL_TIMER1MS_CLK_OFFSET 0x0028
330 #define AM33XX_CLKSEL_TIMER1MS_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0028)
331 #define AM33XX_CLKSEL_GFX_FCLK_OFFSET 0x002c
332 #define AM33XX_CLKSEL_GFX_FCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x002c)
333 #define AM33XX_CLKSEL_PRUSS_OCP_CLK_OFFSET 0x0030
334 #define AM33XX_CLKSEL_PRUSS_OCP_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0030)
335 #define AM33XX_CLKSEL_LCDC_PIXEL_CLK_OFFSET 0x0034
336 #define AM33XX_CLKSEL_LCDC_PIXEL_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0034)
337 #define AM33XX_CLKSEL_WDT1_CLK_OFFSET 0x0038
338 #define AM33XX_CLKSEL_WDT1_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0038)
339 #define AM33XX_CLKSEL_GPIO0_DBCLK_OFFSET 0x003c
340 #define AM33XX_CLKSEL_GPIO0_DBCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x003c)
341
342 /* CM.MPU_CM register offsets */
343 #define AM33XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000
344 #define AM33XX_CM_MPU_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0000)
345 #define AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0004
346 #define AM33XX_CM_MPU_MPU_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0004)
347
348 /* CM.DEVICE_CM register offsets */
349 #define AM33XX_CM_CLKOUT_CTRL_OFFSET 0x0000
350 #define AM33XX_CM_CLKOUT_CTRL AM33XX_CM_REGADDR(AM33XX_CM_DEVICE_MOD, 0x0000)
351
352 /* CM.RTC_CM register offsets */
353 #define AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET 0x0000
354 #define AM33XX_CM_RTC_RTC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0000)
355 #define AM33XX_CM_RTC_CLKSTCTRL_OFFSET 0x0004
356 #define AM33XX_CM_RTC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0004)
357
358 /* CM.GFX_CM register offsets */
359 #define AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET 0x0000
360 #define AM33XX_CM_GFX_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0000)
361 #define AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET 0x0004
362 #define AM33XX_CM_GFX_GFX_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0004)
363 #define AM33XX_CM_GFX_BITBLT_CLKCTRL_OFFSET 0x0008
364 #define AM33XX_CM_GFX_BITBLT_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0008)
365 #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET 0x000c
366 #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1 AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x000c)
367 #define AM33XX_CM_GFX_MMUCFG_CLKCTRL_OFFSET 0x0010
368 #define AM33XX_CM_GFX_MMUCFG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0010)
369 #define AM33XX_CM_GFX_MMUDATA_CLKCTRL_OFFSET 0x0014
370 #define AM33XX_CM_GFX_MMUDATA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0014)
371
372 /* CM.CEFUSE_CM register offsets */
373 #define AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000
374 #define AM33XX_CM_CEFUSE_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0000)
375 #define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
376 #define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020)
377
378
379 #ifndef __ASSEMBLER__
380 extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs);
381 extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs);
382 extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
383 extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs);
384 extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs);
385
386 #ifdef CONFIG_SOC_AM33XX
387 extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
388 u16 clkctrl_offs);
389 extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
390 u16 clkctrl_offs);
391 extern void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
392 u16 clkctrl_offs);
393 extern int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
394 u16 clkctrl_offs);
395 #else
am33xx_cm_wait_module_idle(u16 inst,s16 cdoffs,u16 clkctrl_offs)396 static inline int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
397 u16 clkctrl_offs)
398 {
399 return 0;
400 }
am33xx_cm_module_enable(u8 mode,u16 inst,s16 cdoffs,u16 clkctrl_offs)401 static inline void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
402 u16 clkctrl_offs)
403 {
404 }
am33xx_cm_module_disable(u16 inst,s16 cdoffs,u16 clkctrl_offs)405 static inline void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
406 u16 clkctrl_offs)
407 {
408 }
am33xx_cm_wait_module_ready(u16 inst,s16 cdoffs,u16 clkctrl_offs)409 static inline int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
410 u16 clkctrl_offs)
411 {
412 return 0;
413 }
414 #endif
415
416 #endif /* ASSEMBLER */
417 #endif
418