1 #ifndef B43_H_
2 #define B43_H_
3
4 #include <linux/kernel.h>
5 #include <linux/spinlock.h>
6 #include <linux/interrupt.h>
7 #include <linux/hw_random.h>
8 #include <linux/bcma/bcma.h>
9 #include <linux/ssb/ssb.h>
10 #include <linux/completion.h>
11 #include <net/mac80211.h>
12
13 #include "debugfs.h"
14 #include "leds.h"
15 #include "rfkill.h"
16 #include "bus.h"
17 #include "lo.h"
18 #include "phy_common.h"
19
20
21 #ifdef CONFIG_B43_DEBUG
22 # define B43_DEBUG 1
23 #else
24 # define B43_DEBUG 0
25 #endif
26
27 /* MMIO offsets */
28 #define B43_MMIO_DMA0_REASON 0x20
29 #define B43_MMIO_DMA0_IRQ_MASK 0x24
30 #define B43_MMIO_DMA1_REASON 0x28
31 #define B43_MMIO_DMA1_IRQ_MASK 0x2C
32 #define B43_MMIO_DMA2_REASON 0x30
33 #define B43_MMIO_DMA2_IRQ_MASK 0x34
34 #define B43_MMIO_DMA3_REASON 0x38
35 #define B43_MMIO_DMA3_IRQ_MASK 0x3C
36 #define B43_MMIO_DMA4_REASON 0x40
37 #define B43_MMIO_DMA4_IRQ_MASK 0x44
38 #define B43_MMIO_DMA5_REASON 0x48
39 #define B43_MMIO_DMA5_IRQ_MASK 0x4C
40 #define B43_MMIO_MACCTL 0x120 /* MAC control */
41 #define B43_MMIO_MACCMD 0x124 /* MAC command */
42 #define B43_MMIO_GEN_IRQ_REASON 0x128
43 #define B43_MMIO_GEN_IRQ_MASK 0x12C
44 #define B43_MMIO_RAM_CONTROL 0x130
45 #define B43_MMIO_RAM_DATA 0x134
46 #define B43_MMIO_PS_STATUS 0x140
47 #define B43_MMIO_RADIO_HWENABLED_HI 0x158
48 #define B43_MMIO_SHM_CONTROL 0x160
49 #define B43_MMIO_SHM_DATA 0x164
50 #define B43_MMIO_SHM_DATA_UNALIGNED 0x166
51 #define B43_MMIO_XMITSTAT_0 0x170
52 #define B43_MMIO_XMITSTAT_1 0x174
53 #define B43_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
54 #define B43_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */
55 #define B43_MMIO_TSF_CFP_REP 0x188
56 #define B43_MMIO_TSF_CFP_START 0x18C
57 #define B43_MMIO_TSF_CFP_MAXDUR 0x190
58
59 /* 32-bit DMA */
60 #define B43_MMIO_DMA32_BASE0 0x200
61 #define B43_MMIO_DMA32_BASE1 0x220
62 #define B43_MMIO_DMA32_BASE2 0x240
63 #define B43_MMIO_DMA32_BASE3 0x260
64 #define B43_MMIO_DMA32_BASE4 0x280
65 #define B43_MMIO_DMA32_BASE5 0x2A0
66 /* 64-bit DMA */
67 #define B43_MMIO_DMA64_BASE0 0x200
68 #define B43_MMIO_DMA64_BASE1 0x240
69 #define B43_MMIO_DMA64_BASE2 0x280
70 #define B43_MMIO_DMA64_BASE3 0x2C0
71 #define B43_MMIO_DMA64_BASE4 0x300
72 #define B43_MMIO_DMA64_BASE5 0x340
73
74 /* PIO on core rev < 11 */
75 #define B43_MMIO_PIO_BASE0 0x300
76 #define B43_MMIO_PIO_BASE1 0x310
77 #define B43_MMIO_PIO_BASE2 0x320
78 #define B43_MMIO_PIO_BASE3 0x330
79 #define B43_MMIO_PIO_BASE4 0x340
80 #define B43_MMIO_PIO_BASE5 0x350
81 #define B43_MMIO_PIO_BASE6 0x360
82 #define B43_MMIO_PIO_BASE7 0x370
83 /* PIO on core rev >= 11 */
84 #define B43_MMIO_PIO11_BASE0 0x200
85 #define B43_MMIO_PIO11_BASE1 0x240
86 #define B43_MMIO_PIO11_BASE2 0x280
87 #define B43_MMIO_PIO11_BASE3 0x2C0
88 #define B43_MMIO_PIO11_BASE4 0x300
89 #define B43_MMIO_PIO11_BASE5 0x340
90
91 #define B43_MMIO_RADIO24_CONTROL 0x3D8 /* core rev >= 24 only */
92 #define B43_MMIO_RADIO24_DATA 0x3DA /* core rev >= 24 only */
93 #define B43_MMIO_PHY_VER 0x3E0
94 #define B43_MMIO_PHY_RADIO 0x3E2
95 #define B43_MMIO_PHY0 0x3E6
96 #define B43_MMIO_ANTENNA 0x3E8
97 #define B43_MMIO_CHANNEL 0x3F0
98 #define B43_MMIO_CHANNEL_EXT 0x3F4
99 #define B43_MMIO_RADIO_CONTROL 0x3F6
100 #define B43_MMIO_RADIO_DATA_HIGH 0x3F8
101 #define B43_MMIO_RADIO_DATA_LOW 0x3FA
102 #define B43_MMIO_PHY_CONTROL 0x3FC
103 #define B43_MMIO_PHY_DATA 0x3FE
104 #define B43_MMIO_MACFILTER_CONTROL 0x420
105 #define B43_MMIO_MACFILTER_DATA 0x422
106 #define B43_MMIO_RCMTA_COUNT 0x43C
107 #define B43_MMIO_PSM_PHY_HDR 0x492
108 #define B43_MMIO_RADIO_HWENABLED_LO 0x49A
109 #define B43_MMIO_GPIO_CONTROL 0x49C
110 #define B43_MMIO_GPIO_MASK 0x49E
111 #define B43_MMIO_TXE0_CTL 0x500
112 #define B43_MMIO_TXE0_AUX 0x502
113 #define B43_MMIO_TXE0_TS_LOC 0x504
114 #define B43_MMIO_TXE0_TIME_OUT 0x506
115 #define B43_MMIO_TXE0_WM_0 0x508
116 #define B43_MMIO_TXE0_WM_1 0x50A
117 #define B43_MMIO_TXE0_PHYCTL 0x50C
118 #define B43_MMIO_TXE0_STATUS 0x50E
119 #define B43_MMIO_TXE0_MMPLCP0 0x510
120 #define B43_MMIO_TXE0_MMPLCP1 0x512
121 #define B43_MMIO_TXE0_PHYCTL1 0x514
122 #define B43_MMIO_XMTFIFODEF 0x520
123 #define B43_MMIO_XMTFIFO_FRAME_CNT 0x522 /* core rev>= 16 only */
124 #define B43_MMIO_XMTFIFO_BYTE_CNT 0x524 /* core rev>= 16 only */
125 #define B43_MMIO_XMTFIFO_HEAD 0x526 /* core rev>= 16 only */
126 #define B43_MMIO_XMTFIFO_RD_PTR 0x528 /* core rev>= 16 only */
127 #define B43_MMIO_XMTFIFO_WR_PTR 0x52A /* core rev>= 16 only */
128 #define B43_MMIO_XMTFIFODEF1 0x52C /* core rev>= 16 only */
129 #define B43_MMIO_XMTFIFOCMD 0x540
130 #define B43_MMIO_XMTFIFOFLUSH 0x542
131 #define B43_MMIO_XMTFIFOTHRESH 0x544
132 #define B43_MMIO_XMTFIFORDY 0x546
133 #define B43_MMIO_XMTFIFOPRIRDY 0x548
134 #define B43_MMIO_XMTFIFORQPRI 0x54A
135 #define B43_MMIO_XMTTPLATETXPTR 0x54C
136 #define B43_MMIO_XMTTPLATEPTR 0x550
137 #define B43_MMIO_SMPL_CLCT_STRPTR 0x552 /* core rev>= 22 only */
138 #define B43_MMIO_SMPL_CLCT_STPPTR 0x554 /* core rev>= 22 only */
139 #define B43_MMIO_SMPL_CLCT_CURPTR 0x556 /* core rev>= 22 only */
140 #define B43_MMIO_XMTTPLATEDATALO 0x560
141 #define B43_MMIO_XMTTPLATEDATAHI 0x562
142 #define B43_MMIO_XMTSEL 0x568
143 #define B43_MMIO_XMTTXCNT 0x56A
144 #define B43_MMIO_XMTTXSHMADDR 0x56C
145 #define B43_MMIO_TSF_CFP_START_LOW 0x604
146 #define B43_MMIO_TSF_CFP_START_HIGH 0x606
147 #define B43_MMIO_TSF_CFP_PRETBTT 0x612
148 #define B43_MMIO_TSF_CLK_FRAC_LOW 0x62E
149 #define B43_MMIO_TSF_CLK_FRAC_HIGH 0x630
150 #define B43_MMIO_TSF_0 0x632 /* core rev < 3 only */
151 #define B43_MMIO_TSF_1 0x634 /* core rev < 3 only */
152 #define B43_MMIO_TSF_2 0x636 /* core rev < 3 only */
153 #define B43_MMIO_TSF_3 0x638 /* core rev < 3 only */
154 #define B43_MMIO_RNG 0x65A
155 #define B43_MMIO_IFSSLOT 0x684 /* Interframe slot time */
156 #define B43_MMIO_IFSCTL 0x688 /* Interframe space control */
157 #define B43_MMIO_IFSSTAT 0x690
158 #define B43_MMIO_IFSMEDBUSYCTL 0x692
159 #define B43_MMIO_IFTXDUR 0x694
160 #define B43_MMIO_IFSCTL_USE_EDCF 0x0004
161 #define B43_MMIO_POWERUP_DELAY 0x6A8
162 #define B43_MMIO_BTCOEX_CTL 0x6B4 /* Bluetooth Coexistence Control */
163 #define B43_MMIO_BTCOEX_STAT 0x6B6 /* Bluetooth Coexistence Status */
164 #define B43_MMIO_BTCOEX_TXCTL 0x6B8 /* Bluetooth Coexistence Transmit Control */
165 #define B43_MMIO_WEPCTL 0x7C0
166
167 /* SPROM boardflags_lo values */
168 #define B43_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
169 #define B43_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
170 #define B43_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
171 #define B43_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
172 #define B43_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
173 #define B43_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
174 #define B43_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
175 #define B43_BFL_ENETADM 0x0080 /* has ADMtek switch */
176 #define B43_BFL_ENETVLAN 0x0100 /* can do vlan */
177 #define B43_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
178 #define B43_BFL_NOPCI 0x0400 /* leaves PCI floating */
179 #define B43_BFL_FEM 0x0800 /* supports the Front End Module */
180 #define B43_BFL_EXTLNA 0x1000 /* has an external LNA */
181 #define B43_BFL_HGPA 0x2000 /* had high gain PA */
182 #define B43_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
183 #define B43_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
184
185 /* SPROM boardflags_hi values */
186 #define B43_BFH_NOPA 0x0001 /* has no PA */
187 #define B43_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
188 #define B43_BFH_PAREF 0x0004 /* uses the PARef LDO */
189 #define B43_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared
190 * with bluetooth */
191 #define B43_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
192 #define B43_BFH_BUCKBOOST 0x0020 /* has buck/booster */
193 #define B43_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna
194 * with bluetooth */
195 #define B43_BFH_NOCBUCK 0x0080
196 #define B43_BFH_PALDO 0x0200
197 #define B43_BFH_EXTLNA_5GHZ 0x1000 /* has an external LNA (5GHz mode) */
198
199 /* SPROM boardflags2_lo values */
200 #define B43_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */
201 #define B43_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
202 #define B43_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */
203 #define B43_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */
204 #define B43_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
205 #define B43_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
206 #define B43_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */
207 #define B43_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
208 #define B43_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */
209 #define B43_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
210 #define B43_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
211 #define B43_BFL2_SINGLEANT_CCK 0x1000
212 #define B43_BFL2_2G_SPUR_WAR 0x2000
213
214 /* SPROM boardflags2_hi values */
215 #define B43_BFH2_GPLL_WAR2 0x0001
216 #define B43_BFH2_IPALVLSHIFT_3P3 0x0002
217 #define B43_BFH2_INTERNDET_TXIQCAL 0x0004
218 #define B43_BFH2_XTALBUFOUTEN 0x0008
219
220 /* GPIO register offset, in both ChipCommon and PCI core. */
221 #define B43_GPIO_CONTROL 0x6c
222
223 /* SHM Routing */
224 enum {
225 B43_SHM_UCODE, /* Microcode memory */
226 B43_SHM_SHARED, /* Shared memory */
227 B43_SHM_SCRATCH, /* Scratch memory */
228 B43_SHM_HW, /* Internal hardware register */
229 B43_SHM_RCMTA, /* Receive match transmitter address (rev >= 5 only) */
230 };
231 /* SHM Routing modifiers */
232 #define B43_SHM_AUTOINC_R 0x0200 /* Auto-increment address on read */
233 #define B43_SHM_AUTOINC_W 0x0100 /* Auto-increment address on write */
234 #define B43_SHM_AUTOINC_RW (B43_SHM_AUTOINC_R | \
235 B43_SHM_AUTOINC_W)
236
237 /* Misc SHM_SHARED offsets */
238 #define B43_SHM_SH_WLCOREREV 0x0016 /* 802.11 core revision */
239 #define B43_SHM_SH_PCTLWDPOS 0x0008
240 #define B43_SHM_SH_RXPADOFF 0x0034 /* RX Padding data offset (PIO only) */
241 #define B43_SHM_SH_FWCAPA 0x0042 /* Firmware capabilities (Opensource firmware only) */
242 #define B43_SHM_SH_PHYVER 0x0050 /* PHY version */
243 #define B43_SHM_SH_PHYTYPE 0x0052 /* PHY type */
244 #define B43_SHM_SH_ANTSWAP 0x005C /* Antenna swap threshold */
245 #define B43_SHM_SH_HOSTF1 0x005E /* Hostflags 1 for ucode options */
246 #define B43_SHM_SH_HOSTF2 0x0060 /* Hostflags 2 for ucode options */
247 #define B43_SHM_SH_HOSTF3 0x0062 /* Hostflags 3 for ucode options */
248 #define B43_SHM_SH_RFATT 0x0064 /* Current radio attenuation value */
249 #define B43_SHM_SH_RADAR 0x0066 /* Radar register */
250 #define B43_SHM_SH_PHYTXNOI 0x006E /* PHY noise directly after TX (lower 8bit only) */
251 #define B43_SHM_SH_RFRXSP1 0x0072 /* RF RX SP Register 1 */
252 #define B43_SHM_SH_HOSTF4 0x0078 /* Hostflags 4 for ucode options */
253 #define B43_SHM_SH_CHAN 0x00A0 /* Current channel (low 8bit only) */
254 #define B43_SHM_SH_CHAN_5GHZ 0x0100 /* Bit set, if 5 Ghz channel */
255 #define B43_SHM_SH_CHAN_40MHZ 0x0200 /* Bit set, if 40 Mhz channel width */
256 #define B43_SHM_SH_HOSTF5 0x00D4 /* Hostflags 5 for ucode options */
257 #define B43_SHM_SH_BCMCFIFOID 0x0108 /* Last posted cookie to the bcast/mcast FIFO */
258 /* TSSI information */
259 #define B43_SHM_SH_TSSI_CCK 0x0058 /* TSSI for last 4 CCK frames (32bit) */
260 #define B43_SHM_SH_TSSI_OFDM_A 0x0068 /* TSSI for last 4 OFDM frames (32bit) */
261 #define B43_SHM_SH_TSSI_OFDM_G 0x0070 /* TSSI for last 4 OFDM frames (32bit) */
262 #define B43_TSSI_MAX 0x7F /* Max value for one TSSI value */
263 /* SHM_SHARED TX FIFO variables */
264 #define B43_SHM_SH_SIZE01 0x0098 /* TX FIFO size for FIFO 0 (low) and 1 (high) */
265 #define B43_SHM_SH_SIZE23 0x009A /* TX FIFO size for FIFO 2 and 3 */
266 #define B43_SHM_SH_SIZE45 0x009C /* TX FIFO size for FIFO 4 and 5 */
267 #define B43_SHM_SH_SIZE67 0x009E /* TX FIFO size for FIFO 6 and 7 */
268 /* SHM_SHARED background noise */
269 #define B43_SHM_SH_JSSI0 0x0088 /* Measure JSSI 0 */
270 #define B43_SHM_SH_JSSI1 0x008A /* Measure JSSI 1 */
271 #define B43_SHM_SH_JSSIAUX 0x008C /* Measure JSSI AUX */
272 /* SHM_SHARED crypto engine */
273 #define B43_SHM_SH_DEFAULTIV 0x003C /* Default IV location */
274 #define B43_SHM_SH_NRRXTRANS 0x003E /* # of soft RX transmitter addresses (max 8) */
275 #define B43_SHM_SH_KTP 0x0056 /* Key table pointer */
276 #define B43_SHM_SH_TKIPTSCTTAK 0x0318
277 #define B43_SHM_SH_KEYIDXBLOCK 0x05D4 /* Key index/algorithm block (v4 firmware) */
278 #define B43_SHM_SH_PSM 0x05F4 /* PSM transmitter address match block (rev < 5) */
279 /* SHM_SHARED WME variables */
280 #define B43_SHM_SH_EDCFSTAT 0x000E /* EDCF status */
281 #define B43_SHM_SH_TXFCUR 0x0030 /* TXF current index */
282 #define B43_SHM_SH_EDCFQ 0x0240 /* EDCF Q info */
283 /* SHM_SHARED powersave mode related */
284 #define B43_SHM_SH_SLOTT 0x0010 /* Slot time */
285 #define B43_SHM_SH_DTIMPER 0x0012 /* DTIM period */
286 #define B43_SHM_SH_NOSLPZNATDTIM 0x004C /* NOSLPZNAT DTIM */
287 /* SHM_SHARED beacon/AP variables */
288 #define B43_SHM_SH_BT_BASE0 0x0068 /* Beacon template base 0 */
289 #define B43_SHM_SH_BTL0 0x0018 /* Beacon template length 0 */
290 #define B43_SHM_SH_BT_BASE1 0x0468 /* Beacon template base 1 */
291 #define B43_SHM_SH_BTL1 0x001A /* Beacon template length 1 */
292 #define B43_SHM_SH_BTSFOFF 0x001C /* Beacon TSF offset */
293 #define B43_SHM_SH_TIMBPOS 0x001E /* TIM B position in beacon */
294 #define B43_SHM_SH_DTIMP 0x0012 /* DTIP period */
295 #define B43_SHM_SH_MCASTCOOKIE 0x00A8 /* Last bcast/mcast frame ID */
296 #define B43_SHM_SH_SFFBLIM 0x0044 /* Short frame fallback retry limit */
297 #define B43_SHM_SH_LFFBLIM 0x0046 /* Long frame fallback retry limit */
298 #define B43_SHM_SH_BEACPHYCTL 0x0054 /* Beacon PHY TX control word (see PHY TX control) */
299 #define B43_SHM_SH_EXTNPHYCTL 0x00B0 /* Extended bytes for beacon PHY control (N) */
300 /* SHM_SHARED ACK/CTS control */
301 #define B43_SHM_SH_ACKCTSPHYCTL 0x0022 /* ACK/CTS PHY control word (see PHY TX control) */
302 /* SHM_SHARED probe response variables */
303 #define B43_SHM_SH_PRSSID 0x0160 /* Probe Response SSID */
304 #define B43_SHM_SH_PRSSIDLEN 0x0048 /* Probe Response SSID length */
305 #define B43_SHM_SH_PRTLEN 0x004A /* Probe Response template length */
306 #define B43_SHM_SH_PRMAXTIME 0x0074 /* Probe Response max time */
307 #define B43_SHM_SH_PRPHYCTL 0x0188 /* Probe Response PHY TX control word */
308 /* SHM_SHARED rate tables */
309 #define B43_SHM_SH_OFDMDIRECT 0x01C0 /* Pointer to OFDM direct map */
310 #define B43_SHM_SH_OFDMBASIC 0x01E0 /* Pointer to OFDM basic rate map */
311 #define B43_SHM_SH_CCKDIRECT 0x0200 /* Pointer to CCK direct map */
312 #define B43_SHM_SH_CCKBASIC 0x0220 /* Pointer to CCK basic rate map */
313 /* SHM_SHARED microcode soft registers */
314 #define B43_SHM_SH_UCODEREV 0x0000 /* Microcode revision */
315 #define B43_SHM_SH_UCODEPATCH 0x0002 /* Microcode patchlevel */
316 #define B43_SHM_SH_UCODEDATE 0x0004 /* Microcode date */
317 #define B43_SHM_SH_UCODETIME 0x0006 /* Microcode time */
318 #define B43_SHM_SH_UCODESTAT 0x0040 /* Microcode debug status code */
319 #define B43_SHM_SH_UCODESTAT_INVALID 0
320 #define B43_SHM_SH_UCODESTAT_INIT 1
321 #define B43_SHM_SH_UCODESTAT_ACTIVE 2
322 #define B43_SHM_SH_UCODESTAT_SUSP 3 /* suspended */
323 #define B43_SHM_SH_UCODESTAT_SLEEP 4 /* asleep (PS) */
324 #define B43_SHM_SH_MAXBFRAMES 0x0080 /* Maximum number of frames in a burst */
325 #define B43_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */
326 #define B43_SHM_SH_PRETBTT 0x0096 /* pre-TBTT in us */
327 /* SHM_SHARED tx iq workarounds */
328 #define B43_SHM_SH_NPHY_TXIQW0 0x0700
329 #define B43_SHM_SH_NPHY_TXIQW1 0x0702
330 #define B43_SHM_SH_NPHY_TXIQW2 0x0704
331 #define B43_SHM_SH_NPHY_TXIQW3 0x0706
332 /* SHM_SHARED tx pwr ctrl */
333 #define B43_SHM_SH_NPHY_TXPWR_INDX0 0x0708
334 #define B43_SHM_SH_NPHY_TXPWR_INDX1 0x070E
335
336 /* SHM_SCRATCH offsets */
337 #define B43_SHM_SC_MINCONT 0x0003 /* Minimum contention window */
338 #define B43_SHM_SC_MAXCONT 0x0004 /* Maximum contention window */
339 #define B43_SHM_SC_CURCONT 0x0005 /* Current contention window */
340 #define B43_SHM_SC_SRLIMIT 0x0006 /* Short retry count limit */
341 #define B43_SHM_SC_LRLIMIT 0x0007 /* Long retry count limit */
342 #define B43_SHM_SC_DTIMC 0x0008 /* Current DTIM count */
343 #define B43_SHM_SC_BTL0LEN 0x0015 /* Beacon 0 template length */
344 #define B43_SHM_SC_BTL1LEN 0x0016 /* Beacon 1 template length */
345 #define B43_SHM_SC_SCFB 0x0017 /* Short frame transmit count threshold for rate fallback */
346 #define B43_SHM_SC_LCFB 0x0018 /* Long frame transmit count threshold for rate fallback */
347
348 /* Hardware Radio Enable masks */
349 #define B43_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
350 #define B43_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
351
352 /* HostFlags. See b43_hf_read/write() */
353 #define B43_HF_ANTDIVHELP 0x000000000001ULL /* ucode antenna div helper */
354 #define B43_HF_SYMW 0x000000000002ULL /* G-PHY SYM workaround */
355 #define B43_HF_RXPULLW 0x000000000004ULL /* RX pullup workaround */
356 #define B43_HF_CCKBOOST 0x000000000008ULL /* 4dB CCK power boost (exclusive with OFDM boost) */
357 #define B43_HF_BTCOEX 0x000000000010ULL /* Bluetooth coexistance */
358 #define B43_HF_GDCW 0x000000000020ULL /* G-PHY DC canceller filter bw workaround */
359 #define B43_HF_OFDMPABOOST 0x000000000040ULL /* Enable PA gain boost for OFDM */
360 #define B43_HF_ACPR 0x000000000080ULL /* Disable for Japan, channel 14 */
361 #define B43_HF_EDCF 0x000000000100ULL /* on if WME and MAC suspended */
362 #define B43_HF_TSSIRPSMW 0x000000000200ULL /* TSSI reset PSM ucode workaround */
363 #define B43_HF_20IN40IQW 0x000000000200ULL /* 20 in 40 MHz I/Q workaround (rev >= 13 only) */
364 #define B43_HF_DSCRQ 0x000000000400ULL /* Disable slow clock request in ucode */
365 #define B43_HF_ACIW 0x000000000800ULL /* ACI workaround: shift bits by 2 on PHY CRS */
366 #define B43_HF_2060W 0x000000001000ULL /* 2060 radio workaround */
367 #define B43_HF_RADARW 0x000000002000ULL /* Radar workaround */
368 #define B43_HF_USEDEFKEYS 0x000000004000ULL /* Enable use of default keys */
369 #define B43_HF_AFTERBURNER 0x000000008000ULL /* Afterburner enabled */
370 #define B43_HF_BT4PRIOCOEX 0x000000010000ULL /* Bluetooth 4-priority coexistance */
371 #define B43_HF_FWKUP 0x000000020000ULL /* Fast wake-up ucode */
372 #define B43_HF_VCORECALC 0x000000040000ULL /* Force VCO recalculation when powering up synthpu */
373 #define B43_HF_PCISCW 0x000000080000ULL /* PCI slow clock workaround */
374 #define B43_HF_4318TSSI 0x000000200000ULL /* 4318 TSSI */
375 #define B43_HF_FBCMCFIFO 0x000000400000ULL /* Flush bcast/mcast FIFO immediately */
376 #define B43_HF_HWPCTL 0x000000800000ULL /* Enable hardwarre power control */
377 #define B43_HF_BTCOEXALT 0x000001000000ULL /* Bluetooth coexistance in alternate pins */
378 #define B43_HF_TXBTCHECK 0x000002000000ULL /* Bluetooth check during transmission */
379 #define B43_HF_SKCFPUP 0x000004000000ULL /* Skip CFP update */
380 #define B43_HF_N40W 0x000008000000ULL /* N PHY 40 MHz workaround (rev >= 13 only) */
381 #define B43_HF_ANTSEL 0x000020000000ULL /* Antenna selection (for testing antenna div.) */
382 #define B43_HF_BT3COEXT 0x000020000000ULL /* Bluetooth 3-wire coexistence (rev >= 13 only) */
383 #define B43_HF_BTCANT 0x000040000000ULL /* Bluetooth coexistence (antenna mode) (rev >= 13 only) */
384 #define B43_HF_ANTSELEN 0x000100000000ULL /* Antenna selection enabled (rev >= 13 only) */
385 #define B43_HF_ANTSELMODE 0x000200000000ULL /* Antenna selection mode (rev >= 13 only) */
386 #define B43_HF_MLADVW 0x001000000000ULL /* N PHY ML ADV workaround (rev >= 13 only) */
387 #define B43_HF_PR45960W 0x080000000000ULL /* PR 45960 workaround (rev >= 13 only) */
388
389 /* Firmware capabilities field in SHM (Opensource firmware only) */
390 #define B43_FWCAPA_HWCRYPTO 0x0001
391 #define B43_FWCAPA_QOS 0x0002
392
393 /* MacFilter offsets. */
394 #define B43_MACFILTER_SELF 0x0000
395 #define B43_MACFILTER_BSSID 0x0003
396
397 /* PowerControl */
398 #define B43_PCTL_IN 0xB0
399 #define B43_PCTL_OUT 0xB4
400 #define B43_PCTL_OUTENABLE 0xB8
401 #define B43_PCTL_XTAL_POWERUP 0x40
402 #define B43_PCTL_PLL_POWERDOWN 0x80
403
404 /* PowerControl Clock Modes */
405 #define B43_PCTL_CLK_FAST 0x00
406 #define B43_PCTL_CLK_SLOW 0x01
407 #define B43_PCTL_CLK_DYNAMIC 0x02
408
409 #define B43_PCTL_FORCE_SLOW 0x0800
410 #define B43_PCTL_FORCE_PLL 0x1000
411 #define B43_PCTL_DYN_XTAL 0x2000
412
413 /* PHYVersioning */
414 #define B43_PHYTYPE_A 0x00
415 #define B43_PHYTYPE_B 0x01
416 #define B43_PHYTYPE_G 0x02
417 #define B43_PHYTYPE_N 0x04
418 #define B43_PHYTYPE_LP 0x05
419 #define B43_PHYTYPE_SSLPN 0x06
420 #define B43_PHYTYPE_HT 0x07
421 #define B43_PHYTYPE_LCN 0x08
422 #define B43_PHYTYPE_LCNXN 0x09
423 #define B43_PHYTYPE_LCN40 0x0a
424 #define B43_PHYTYPE_AC 0x0b
425
426 /* PHYRegisters */
427 #define B43_PHY_ILT_A_CTRL 0x0072
428 #define B43_PHY_ILT_A_DATA1 0x0073
429 #define B43_PHY_ILT_A_DATA2 0x0074
430 #define B43_PHY_G_LO_CONTROL 0x0810
431 #define B43_PHY_ILT_G_CTRL 0x0472
432 #define B43_PHY_ILT_G_DATA1 0x0473
433 #define B43_PHY_ILT_G_DATA2 0x0474
434 #define B43_PHY_A_PCTL 0x007B
435 #define B43_PHY_G_PCTL 0x0029
436 #define B43_PHY_A_CRS 0x0029
437 #define B43_PHY_RADIO_BITFIELD 0x0401
438 #define B43_PHY_G_CRS 0x0429
439 #define B43_PHY_NRSSILT_CTRL 0x0803
440 #define B43_PHY_NRSSILT_DATA 0x0804
441
442 /* RadioRegisters */
443 #define B43_RADIOCTL_ID 0x01
444
445 /* MAC Control bitfield */
446 #define B43_MACCTL_ENABLED 0x00000001 /* MAC Enabled */
447 #define B43_MACCTL_PSM_RUN 0x00000002 /* Run Microcode */
448 #define B43_MACCTL_PSM_JMP0 0x00000004 /* Microcode jump to 0 */
449 #define B43_MACCTL_SHM_ENABLED 0x00000100 /* SHM Enabled */
450 #define B43_MACCTL_SHM_UPPER 0x00000200 /* SHM Upper */
451 #define B43_MACCTL_IHR_ENABLED 0x00000400 /* IHR Region Enabled */
452 #define B43_MACCTL_PSM_DBG 0x00002000 /* Microcode debugging enabled */
453 #define B43_MACCTL_GPOUTSMSK 0x0000C000 /* GPOUT Select Mask */
454 #define B43_MACCTL_BE 0x00010000 /* Big Endian mode */
455 #define B43_MACCTL_INFRA 0x00020000 /* Infrastructure mode */
456 #define B43_MACCTL_AP 0x00040000 /* AccessPoint mode */
457 #define B43_MACCTL_RADIOLOCK 0x00080000 /* Radio lock */
458 #define B43_MACCTL_BEACPROMISC 0x00100000 /* Beacon Promiscuous */
459 #define B43_MACCTL_KEEP_BADPLCP 0x00200000 /* Keep frames with bad PLCP */
460 #define B43_MACCTL_KEEP_CTL 0x00400000 /* Keep control frames */
461 #define B43_MACCTL_KEEP_BAD 0x00800000 /* Keep bad frames (FCS) */
462 #define B43_MACCTL_PROMISC 0x01000000 /* Promiscuous mode */
463 #define B43_MACCTL_HWPS 0x02000000 /* Hardware Power Saving */
464 #define B43_MACCTL_AWAKE 0x04000000 /* Device is awake */
465 #define B43_MACCTL_CLOSEDNET 0x08000000 /* Closed net (no SSID bcast) */
466 #define B43_MACCTL_TBTTHOLD 0x10000000 /* TBTT Hold */
467 #define B43_MACCTL_DISCTXSTAT 0x20000000 /* Discard TX status */
468 #define B43_MACCTL_DISCPMQ 0x40000000 /* Discard Power Management Queue */
469 #define B43_MACCTL_GMODE 0x80000000 /* G Mode */
470
471 /* MAC Command bitfield */
472 #define B43_MACCMD_BEACON0_VALID 0x00000001 /* Beacon 0 in template RAM is busy/valid */
473 #define B43_MACCMD_BEACON1_VALID 0x00000002 /* Beacon 1 in template RAM is busy/valid */
474 #define B43_MACCMD_DFQ_VALID 0x00000004 /* Directed frame queue valid (IBSS PS mode, ATIM) */
475 #define B43_MACCMD_CCA 0x00000008 /* Clear channel assessment */
476 #define B43_MACCMD_BGNOISE 0x00000010 /* Background noise */
477
478 /* See BCMA_CLKCTLST_EXTRESREQ and BCMA_CLKCTLST_EXTRESST */
479 #define B43_BCMA_CLKCTLST_80211_PLL_REQ 0x00000100
480 #define B43_BCMA_CLKCTLST_PHY_PLL_REQ 0x00000200
481 #define B43_BCMA_CLKCTLST_80211_PLL_ST 0x01000000
482 #define B43_BCMA_CLKCTLST_PHY_PLL_ST 0x02000000
483
484 /* BCMA 802.11 core specific IO Control (BCMA_IOCTL) flags */
485 #define B43_BCMA_IOCTL_PHY_CLKEN 0x00000004 /* PHY Clock Enable */
486 #define B43_BCMA_IOCTL_PHY_RESET 0x00000008 /* PHY Reset */
487 #define B43_BCMA_IOCTL_MACPHYCLKEN 0x00000010 /* MAC PHY Clock Control Enable */
488 #define B43_BCMA_IOCTL_PLLREFSEL 0x00000020 /* PLL Frequency Reference Select */
489 #define B43_BCMA_IOCTL_PHY_BW 0x000000C0 /* PHY band width and clock speed mask (N-PHY+ only?) */
490 #define B43_BCMA_IOCTL_PHY_BW_10MHZ 0x00000000 /* 10 MHz bandwidth, 40 MHz PHY */
491 #define B43_BCMA_IOCTL_PHY_BW_20MHZ 0x00000040 /* 20 MHz bandwidth, 80 MHz PHY */
492 #define B43_BCMA_IOCTL_PHY_BW_40MHZ 0x00000080 /* 40 MHz bandwidth, 160 MHz PHY */
493 #define B43_BCMA_IOCTL_GMODE 0x00002000 /* G Mode Enable */
494
495 /* BCMA 802.11 core specific IO status (BCMA_IOST) flags */
496 #define B43_BCMA_IOST_2G_PHY 0x00000001 /* 2.4G capable phy */
497 #define B43_BCMA_IOST_5G_PHY 0x00000002 /* 5G capable phy */
498 #define B43_BCMA_IOST_FASTCLKA 0x00000004 /* Fast Clock Available */
499 #define B43_BCMA_IOST_DUALB_PHY 0x00000008 /* Dualband phy */
500
501 /* 802.11 core specific TM State Low (SSB_TMSLOW) flags */
502 #define B43_TMSLOW_GMODE 0x20000000 /* G Mode Enable */
503 #define B43_TMSLOW_PHY_BANDWIDTH 0x00C00000 /* PHY band width and clock speed mask (N-PHY only) */
504 #define B43_TMSLOW_PHY_BANDWIDTH_10MHZ 0x00000000 /* 10 MHz bandwidth, 40 MHz PHY */
505 #define B43_TMSLOW_PHY_BANDWIDTH_20MHZ 0x00400000 /* 20 MHz bandwidth, 80 MHz PHY */
506 #define B43_TMSLOW_PHY_BANDWIDTH_40MHZ 0x00800000 /* 40 MHz bandwidth, 160 MHz PHY */
507 #define B43_TMSLOW_PLLREFSEL 0x00200000 /* PLL Frequency Reference Select (rev >= 5) */
508 #define B43_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Control Enable (rev >= 5) */
509 #define B43_TMSLOW_PHYRESET 0x00080000 /* PHY Reset */
510 #define B43_TMSLOW_PHYCLKEN 0x00040000 /* PHY Clock Enable */
511
512 /* 802.11 core specific TM State High (SSB_TMSHIGH) flags */
513 #define B43_TMSHIGH_DUALBAND_PHY 0x00080000 /* Dualband PHY available */
514 #define B43_TMSHIGH_FCLOCK 0x00040000 /* Fast Clock Available (rev >= 5) */
515 #define B43_TMSHIGH_HAVE_5GHZ_PHY 0x00020000 /* 5 GHz PHY available (rev >= 5) */
516 #define B43_TMSHIGH_HAVE_2GHZ_PHY 0x00010000 /* 2.4 GHz PHY available (rev >= 5) */
517
518 /* Generic-Interrupt reasons. */
519 #define B43_IRQ_MAC_SUSPENDED 0x00000001
520 #define B43_IRQ_BEACON 0x00000002
521 #define B43_IRQ_TBTT_INDI 0x00000004
522 #define B43_IRQ_BEACON_TX_OK 0x00000008
523 #define B43_IRQ_BEACON_CANCEL 0x00000010
524 #define B43_IRQ_ATIM_END 0x00000020
525 #define B43_IRQ_PMQ 0x00000040
526 #define B43_IRQ_PIO_WORKAROUND 0x00000100
527 #define B43_IRQ_MAC_TXERR 0x00000200
528 #define B43_IRQ_PHY_TXERR 0x00000800
529 #define B43_IRQ_PMEVENT 0x00001000
530 #define B43_IRQ_TIMER0 0x00002000
531 #define B43_IRQ_TIMER1 0x00004000
532 #define B43_IRQ_DMA 0x00008000
533 #define B43_IRQ_TXFIFO_FLUSH_OK 0x00010000
534 #define B43_IRQ_CCA_MEASURE_OK 0x00020000
535 #define B43_IRQ_NOISESAMPLE_OK 0x00040000
536 #define B43_IRQ_UCODE_DEBUG 0x08000000
537 #define B43_IRQ_RFKILL 0x10000000
538 #define B43_IRQ_TX_OK 0x20000000
539 #define B43_IRQ_PHY_G_CHANGED 0x40000000
540 #define B43_IRQ_TIMEOUT 0x80000000
541
542 #define B43_IRQ_ALL 0xFFFFFFFF
543 #define B43_IRQ_MASKTEMPLATE (B43_IRQ_TBTT_INDI | \
544 B43_IRQ_ATIM_END | \
545 B43_IRQ_PMQ | \
546 B43_IRQ_MAC_TXERR | \
547 B43_IRQ_PHY_TXERR | \
548 B43_IRQ_DMA | \
549 B43_IRQ_TXFIFO_FLUSH_OK | \
550 B43_IRQ_NOISESAMPLE_OK | \
551 B43_IRQ_UCODE_DEBUG | \
552 B43_IRQ_RFKILL | \
553 B43_IRQ_TX_OK)
554
555 /* The firmware register to fetch the debug-IRQ reason from. */
556 #define B43_DEBUGIRQ_REASON_REG 63
557 /* Debug-IRQ reasons. */
558 #define B43_DEBUGIRQ_PANIC 0 /* The firmware panic'ed */
559 #define B43_DEBUGIRQ_DUMP_SHM 1 /* Dump shared SHM */
560 #define B43_DEBUGIRQ_DUMP_REGS 2 /* Dump the microcode registers */
561 #define B43_DEBUGIRQ_MARKER 3 /* A "marker" was thrown by the firmware. */
562 #define B43_DEBUGIRQ_ACK 0xFFFF /* The host writes that to ACK the IRQ */
563
564 /* The firmware register that contains the "marker" line. */
565 #define B43_MARKER_ID_REG 2
566 #define B43_MARKER_LINE_REG 3
567
568 /* The firmware register to fetch the panic reason from. */
569 #define B43_FWPANIC_REASON_REG 3
570 /* Firmware panic reason codes */
571 #define B43_FWPANIC_DIE 0 /* Firmware died. Don't auto-restart it. */
572 #define B43_FWPANIC_RESTART 1 /* Firmware died. Schedule a controller reset. */
573
574 /* The firmware register that contains the watchdog counter. */
575 #define B43_WATCHDOG_REG 1
576
577 /* Device specific rate values.
578 * The actual values defined here are (rate_in_mbps * 2).
579 * Some code depends on this. Don't change it. */
580 #define B43_CCK_RATE_1MB 0x02
581 #define B43_CCK_RATE_2MB 0x04
582 #define B43_CCK_RATE_5MB 0x0B
583 #define B43_CCK_RATE_11MB 0x16
584 #define B43_OFDM_RATE_6MB 0x0C
585 #define B43_OFDM_RATE_9MB 0x12
586 #define B43_OFDM_RATE_12MB 0x18
587 #define B43_OFDM_RATE_18MB 0x24
588 #define B43_OFDM_RATE_24MB 0x30
589 #define B43_OFDM_RATE_36MB 0x48
590 #define B43_OFDM_RATE_48MB 0x60
591 #define B43_OFDM_RATE_54MB 0x6C
592 /* Convert a b43 rate value to a rate in 100kbps */
593 #define B43_RATE_TO_BASE100KBPS(rate) (((rate) * 10) / 2)
594
595 #define B43_DEFAULT_SHORT_RETRY_LIMIT 7
596 #define B43_DEFAULT_LONG_RETRY_LIMIT 4
597
598 #define B43_PHY_TX_BADNESS_LIMIT 1000
599
600 /* Max size of a security key */
601 #define B43_SEC_KEYSIZE 16
602 /* Max number of group keys */
603 #define B43_NR_GROUP_KEYS 4
604 /* Max number of pairwise keys */
605 #define B43_NR_PAIRWISE_KEYS 50
606 /* Security algorithms. */
607 enum {
608 B43_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */
609 B43_SEC_ALGO_WEP40,
610 B43_SEC_ALGO_TKIP,
611 B43_SEC_ALGO_AES,
612 B43_SEC_ALGO_WEP104,
613 B43_SEC_ALGO_AES_LEGACY,
614 };
615
616 struct b43_dmaring;
617
618 /* The firmware file header */
619 #define B43_FW_TYPE_UCODE 'u'
620 #define B43_FW_TYPE_PCM 'p'
621 #define B43_FW_TYPE_IV 'i'
622 struct b43_fw_header {
623 /* File type */
624 u8 type;
625 /* File format version */
626 u8 ver;
627 u8 __padding[2];
628 /* Size of the data. For ucode and PCM this is in bytes.
629 * For IV this is number-of-ivs. */
630 __be32 size;
631 } __packed;
632
633 /* Initial Value file format */
634 #define B43_IV_OFFSET_MASK 0x7FFF
635 #define B43_IV_32BIT 0x8000
636 struct b43_iv {
637 __be16 offset_size;
638 union {
639 __be16 d16;
640 __be32 d32;
641 } data __packed;
642 } __packed;
643
644
645 /* Data structures for DMA transmission, per 80211 core. */
646 struct b43_dma {
647 struct b43_dmaring *tx_ring_AC_BK; /* Background */
648 struct b43_dmaring *tx_ring_AC_BE; /* Best Effort */
649 struct b43_dmaring *tx_ring_AC_VI; /* Video */
650 struct b43_dmaring *tx_ring_AC_VO; /* Voice */
651 struct b43_dmaring *tx_ring_mcast; /* Multicast */
652
653 struct b43_dmaring *rx_ring;
654
655 u32 translation; /* Routing bits */
656 bool translation_in_low; /* Should translation bit go into low addr? */
657 bool parity; /* Check for parity */
658 };
659
660 struct b43_pio_txqueue;
661 struct b43_pio_rxqueue;
662
663 /* Data structures for PIO transmission, per 80211 core. */
664 struct b43_pio {
665 struct b43_pio_txqueue *tx_queue_AC_BK; /* Background */
666 struct b43_pio_txqueue *tx_queue_AC_BE; /* Best Effort */
667 struct b43_pio_txqueue *tx_queue_AC_VI; /* Video */
668 struct b43_pio_txqueue *tx_queue_AC_VO; /* Voice */
669 struct b43_pio_txqueue *tx_queue_mcast; /* Multicast */
670
671 struct b43_pio_rxqueue *rx_queue;
672 };
673
674 /* Context information for a noise calculation (Link Quality). */
675 struct b43_noise_calculation {
676 bool calculation_running;
677 u8 nr_samples;
678 s8 samples[8][4];
679 };
680
681 struct b43_stats {
682 u8 link_noise;
683 };
684
685 struct b43_key {
686 /* If keyconf is NULL, this key is disabled.
687 * keyconf is a cookie. Don't derefenrence it outside of the set_key
688 * path, because b43 doesn't own it. */
689 struct ieee80211_key_conf *keyconf;
690 u8 algorithm;
691 };
692
693 /* SHM offsets to the QOS data structures for the 4 different queues. */
694 #define B43_QOS_QUEUE_NUM 4
695 #define B43_QOS_PARAMS(queue) (B43_SHM_SH_EDCFQ + \
696 (B43_NR_QOSPARAMS * sizeof(u16) * (queue)))
697 #define B43_QOS_BACKGROUND B43_QOS_PARAMS(0)
698 #define B43_QOS_BESTEFFORT B43_QOS_PARAMS(1)
699 #define B43_QOS_VIDEO B43_QOS_PARAMS(2)
700 #define B43_QOS_VOICE B43_QOS_PARAMS(3)
701
702 /* QOS parameter hardware data structure offsets. */
703 #define B43_NR_QOSPARAMS 16
704 enum {
705 B43_QOSPARAM_TXOP = 0,
706 B43_QOSPARAM_CWMIN,
707 B43_QOSPARAM_CWMAX,
708 B43_QOSPARAM_CWCUR,
709 B43_QOSPARAM_AIFS,
710 B43_QOSPARAM_BSLOTS,
711 B43_QOSPARAM_REGGAP,
712 B43_QOSPARAM_STATUS,
713 };
714
715 /* QOS parameters for a queue. */
716 struct b43_qos_params {
717 /* The QOS parameters */
718 struct ieee80211_tx_queue_params p;
719 };
720
721 struct b43_wl;
722
723 /* The type of the firmware file. */
724 enum b43_firmware_file_type {
725 B43_FWTYPE_PROPRIETARY,
726 B43_FWTYPE_OPENSOURCE,
727 B43_NR_FWTYPES,
728 };
729
730 /* Context data for fetching firmware. */
731 struct b43_request_fw_context {
732 /* The device we are requesting the fw for. */
733 struct b43_wldev *dev;
734 /* a completion event structure needed if this call is asynchronous */
735 struct completion fw_load_complete;
736 /* a pointer to the firmware object */
737 const struct firmware *blob;
738 /* The type of firmware to request. */
739 enum b43_firmware_file_type req_type;
740 /* Error messages for each firmware type. */
741 char errors[B43_NR_FWTYPES][128];
742 /* Temporary buffer for storing the firmware name. */
743 char fwname[64];
744 /* A fatal error occurred while requesting. Firmware request
745 * can not continue, as any other request will also fail. */
746 int fatal_failure;
747 };
748
749 /* In-memory representation of a cached microcode file. */
750 struct b43_firmware_file {
751 const char *filename;
752 const struct firmware *data;
753 /* Type of the firmware file name. Note that this does only indicate
754 * the type by the firmware name. NOT the file contents.
755 * If you want to check for proprietary vs opensource, use (struct b43_firmware)->opensource
756 * instead! The (struct b43_firmware)->opensource flag is derived from the actual firmware
757 * binary code, not just the filename.
758 */
759 enum b43_firmware_file_type type;
760 };
761
762 enum b43_firmware_hdr_format {
763 B43_FW_HDR_598,
764 B43_FW_HDR_410,
765 B43_FW_HDR_351,
766 };
767
768 /* Pointers to the firmware data and meta information about it. */
769 struct b43_firmware {
770 /* Microcode */
771 struct b43_firmware_file ucode;
772 /* PCM code */
773 struct b43_firmware_file pcm;
774 /* Initial MMIO values for the firmware */
775 struct b43_firmware_file initvals;
776 /* Initial MMIO values for the firmware, band-specific */
777 struct b43_firmware_file initvals_band;
778
779 /* Firmware revision */
780 u16 rev;
781 /* Firmware patchlevel */
782 u16 patch;
783
784 /* Format of header used by firmware */
785 enum b43_firmware_hdr_format hdr_format;
786
787 /* Set to true, if we are using an opensource firmware.
788 * Use this to check for proprietary vs opensource. */
789 bool opensource;
790 /* Set to true, if the core needs a PCM firmware, but
791 * we failed to load one. This is always false for
792 * core rev > 10, as these don't need PCM firmware. */
793 bool pcm_request_failed;
794 };
795
796 /* Device (802.11 core) initialization status. */
797 enum {
798 B43_STAT_UNINIT = 0, /* Uninitialized. */
799 B43_STAT_INITIALIZED = 1, /* Initialized, but not started, yet. */
800 B43_STAT_STARTED = 2, /* Up and running. */
801 };
802 #define b43_status(wldev) atomic_read(&(wldev)->__init_status)
803 #define b43_set_status(wldev, stat) do { \
804 atomic_set(&(wldev)->__init_status, (stat)); \
805 smp_wmb(); \
806 } while (0)
807
808 /* Data structure for one wireless device (802.11 core) */
809 struct b43_wldev {
810 struct b43_bus_dev *dev;
811 struct b43_wl *wl;
812
813 /* The device initialization status.
814 * Use b43_status() to query. */
815 atomic_t __init_status;
816
817 bool bad_frames_preempt; /* Use "Bad Frames Preemption" (default off) */
818 bool dfq_valid; /* Directed frame queue valid (IBSS PS mode, ATIM) */
819 bool radio_hw_enable; /* saved state of radio hardware enabled state */
820 bool qos_enabled; /* TRUE, if QoS is used. */
821 bool hwcrypto_enabled; /* TRUE, if HW crypto acceleration is enabled. */
822 bool use_pio; /* TRUE if next init should use PIO */
823
824 /* PHY/Radio device. */
825 struct b43_phy phy;
826
827 union {
828 /* DMA engines. */
829 struct b43_dma dma;
830 /* PIO engines. */
831 struct b43_pio pio;
832 };
833 /* Use b43_using_pio_transfers() to check whether we are using
834 * DMA or PIO data transfers. */
835 bool __using_pio_transfers;
836
837 /* Various statistics about the physical device. */
838 struct b43_stats stats;
839
840 /* Reason code of the last interrupt. */
841 u32 irq_reason;
842 u32 dma_reason[6];
843 /* The currently active generic-interrupt mask. */
844 u32 irq_mask;
845
846 /* Link Quality calculation context. */
847 struct b43_noise_calculation noisecalc;
848 /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
849 int mac_suspended;
850
851 /* Periodic tasks */
852 struct delayed_work periodic_work;
853 unsigned int periodic_state;
854
855 struct work_struct restart_work;
856
857 /* encryption/decryption */
858 u16 ktp; /* Key table pointer */
859 struct b43_key key[B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS];
860
861 /* Firmware data */
862 struct b43_firmware fw;
863
864 /* Devicelist in struct b43_wl (all 802.11 cores) */
865 struct list_head list;
866
867 /* Debugging stuff follows. */
868 #ifdef CONFIG_B43_DEBUG
869 struct b43_dfsentry *dfsentry;
870 unsigned int irq_count;
871 unsigned int irq_bit_count[32];
872 unsigned int tx_count;
873 unsigned int rx_count;
874 #endif
875 };
876
877 /* Data structure for the WLAN parts (802.11 cores) of the b43 chip. */
878 struct b43_wl {
879 /* Pointer to the active wireless device on this chip */
880 struct b43_wldev *current_dev;
881 /* Pointer to the ieee80211 hardware data structure */
882 struct ieee80211_hw *hw;
883
884 /* Global driver mutex. Every operation must run with this mutex locked. */
885 struct mutex mutex;
886 /* Hard-IRQ spinlock. This lock protects things used in the hard-IRQ
887 * handler, only. This basically is just the IRQ mask register. */
888 spinlock_t hardirq_lock;
889
890 /* Set this if we call ieee80211_register_hw() and check if we call
891 * ieee80211_unregister_hw(). */
892 bool hw_registred;
893
894 /* We can only have one operating interface (802.11 core)
895 * at a time. General information about this interface follows.
896 */
897
898 struct ieee80211_vif *vif;
899 /* The MAC address of the operating interface. */
900 u8 mac_addr[ETH_ALEN];
901 /* Current BSSID */
902 u8 bssid[ETH_ALEN];
903 /* Interface type. (NL80211_IFTYPE_XXX) */
904 int if_type;
905 /* Is the card operating in AP, STA or IBSS mode? */
906 bool operating;
907 /* filter flags */
908 unsigned int filter_flags;
909 /* Stats about the wireless interface */
910 struct ieee80211_low_level_stats ieee_stats;
911
912 #ifdef CONFIG_B43_HWRNG
913 struct hwrng rng;
914 bool rng_initialized;
915 char rng_name[30 + 1];
916 #endif /* CONFIG_B43_HWRNG */
917
918 /* List of all wireless devices on this chip */
919 struct list_head devlist;
920 u8 nr_devs;
921
922 bool radiotap_enabled;
923 bool radio_enabled;
924
925 /* The beacon we are currently using (AP or IBSS mode). */
926 struct sk_buff *current_beacon;
927 bool beacon0_uploaded;
928 bool beacon1_uploaded;
929 bool beacon_templates_virgin; /* Never wrote the templates? */
930 struct work_struct beacon_update_trigger;
931
932 /* The current QOS parameters for the 4 queues. */
933 struct b43_qos_params qos_params[B43_QOS_QUEUE_NUM];
934
935 /* Work for adjustment of the transmission power.
936 * This is scheduled when we determine that the actual TX output
937 * power doesn't match what we want. */
938 struct work_struct txpower_adjust_work;
939
940 /* Packet transmit work */
941 struct work_struct tx_work;
942
943 /* Queue of packets to be transmitted. */
944 struct sk_buff_head tx_queue[B43_QOS_QUEUE_NUM];
945
946 /* Flag that implement the queues stopping. */
947 bool tx_queue_stopped[B43_QOS_QUEUE_NUM];
948
949 /* firmware loading work */
950 struct work_struct firmware_load;
951
952 /* The device LEDs. */
953 struct b43_leds leds;
954
955 /* Kmalloc'ed scratch space for PIO TX/RX. Protected by wl->mutex. */
956 u8 pio_scratchspace[118] __attribute__((__aligned__(8)));
957 u8 pio_tailspace[4] __attribute__((__aligned__(8)));
958 };
959
hw_to_b43_wl(struct ieee80211_hw * hw)960 static inline struct b43_wl *hw_to_b43_wl(struct ieee80211_hw *hw)
961 {
962 return hw->priv;
963 }
964
dev_to_b43_wldev(struct device * dev)965 static inline struct b43_wldev *dev_to_b43_wldev(struct device *dev)
966 {
967 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
968 return ssb_get_drvdata(ssb_dev);
969 }
970
971 /* Is the device operating in a specified mode (NL80211_IFTYPE_XXX). */
b43_is_mode(struct b43_wl * wl,int type)972 static inline int b43_is_mode(struct b43_wl *wl, int type)
973 {
974 return (wl->operating && wl->if_type == type);
975 }
976
977 /**
978 * b43_current_band - Returns the currently used band.
979 * Returns one of IEEE80211_BAND_2GHZ and IEEE80211_BAND_5GHZ.
980 */
b43_current_band(struct b43_wl * wl)981 static inline enum ieee80211_band b43_current_band(struct b43_wl *wl)
982 {
983 return wl->hw->conf.chandef.chan->band;
984 }
985
b43_bus_may_powerdown(struct b43_wldev * wldev)986 static inline int b43_bus_may_powerdown(struct b43_wldev *wldev)
987 {
988 return wldev->dev->bus_may_powerdown(wldev->dev);
989 }
b43_bus_powerup(struct b43_wldev * wldev,bool dynamic_pctl)990 static inline int b43_bus_powerup(struct b43_wldev *wldev, bool dynamic_pctl)
991 {
992 return wldev->dev->bus_powerup(wldev->dev, dynamic_pctl);
993 }
b43_device_is_enabled(struct b43_wldev * wldev)994 static inline int b43_device_is_enabled(struct b43_wldev *wldev)
995 {
996 return wldev->dev->device_is_enabled(wldev->dev);
997 }
b43_device_enable(struct b43_wldev * wldev,u32 core_specific_flags)998 static inline void b43_device_enable(struct b43_wldev *wldev,
999 u32 core_specific_flags)
1000 {
1001 wldev->dev->device_enable(wldev->dev, core_specific_flags);
1002 }
b43_device_disable(struct b43_wldev * wldev,u32 core_specific_flags)1003 static inline void b43_device_disable(struct b43_wldev *wldev,
1004 u32 core_specific_flags)
1005 {
1006 wldev->dev->device_disable(wldev->dev, core_specific_flags);
1007 }
1008
b43_read16(struct b43_wldev * dev,u16 offset)1009 static inline u16 b43_read16(struct b43_wldev *dev, u16 offset)
1010 {
1011 return dev->dev->read16(dev->dev, offset);
1012 }
1013
b43_write16(struct b43_wldev * dev,u16 offset,u16 value)1014 static inline void b43_write16(struct b43_wldev *dev, u16 offset, u16 value)
1015 {
1016 dev->dev->write16(dev->dev, offset, value);
1017 }
1018
b43_maskset16(struct b43_wldev * dev,u16 offset,u16 mask,u16 set)1019 static inline void b43_maskset16(struct b43_wldev *dev, u16 offset, u16 mask,
1020 u16 set)
1021 {
1022 b43_write16(dev, offset, (b43_read16(dev, offset) & mask) | set);
1023 }
1024
b43_read32(struct b43_wldev * dev,u16 offset)1025 static inline u32 b43_read32(struct b43_wldev *dev, u16 offset)
1026 {
1027 return dev->dev->read32(dev->dev, offset);
1028 }
1029
b43_write32(struct b43_wldev * dev,u16 offset,u32 value)1030 static inline void b43_write32(struct b43_wldev *dev, u16 offset, u32 value)
1031 {
1032 dev->dev->write32(dev->dev, offset, value);
1033 }
1034
b43_maskset32(struct b43_wldev * dev,u16 offset,u32 mask,u32 set)1035 static inline void b43_maskset32(struct b43_wldev *dev, u16 offset, u32 mask,
1036 u32 set)
1037 {
1038 b43_write32(dev, offset, (b43_read32(dev, offset) & mask) | set);
1039 }
1040
b43_block_read(struct b43_wldev * dev,void * buffer,size_t count,u16 offset,u8 reg_width)1041 static inline void b43_block_read(struct b43_wldev *dev, void *buffer,
1042 size_t count, u16 offset, u8 reg_width)
1043 {
1044 dev->dev->block_read(dev->dev, buffer, count, offset, reg_width);
1045 }
1046
b43_block_write(struct b43_wldev * dev,const void * buffer,size_t count,u16 offset,u8 reg_width)1047 static inline void b43_block_write(struct b43_wldev *dev, const void *buffer,
1048 size_t count, u16 offset, u8 reg_width)
1049 {
1050 dev->dev->block_write(dev->dev, buffer, count, offset, reg_width);
1051 }
1052
b43_using_pio_transfers(struct b43_wldev * dev)1053 static inline bool b43_using_pio_transfers(struct b43_wldev *dev)
1054 {
1055 return dev->__using_pio_transfers;
1056 }
1057
1058 /* Message printing */
1059 __printf(2, 3) void b43info(struct b43_wl *wl, const char *fmt, ...);
1060 __printf(2, 3) void b43err(struct b43_wl *wl, const char *fmt, ...);
1061 __printf(2, 3) void b43warn(struct b43_wl *wl, const char *fmt, ...);
1062 __printf(2, 3) void b43dbg(struct b43_wl *wl, const char *fmt, ...);
1063
1064
1065 /* A WARN_ON variant that vanishes when b43 debugging is disabled.
1066 * This _also_ evaluates the arg with debugging disabled. */
1067 #if B43_DEBUG
1068 # define B43_WARN_ON(x) WARN_ON(x)
1069 #else
__b43_warn_on_dummy(bool x)1070 static inline bool __b43_warn_on_dummy(bool x) { return x; }
1071 # define B43_WARN_ON(x) __b43_warn_on_dummy(unlikely(!!(x)))
1072 #endif
1073
1074 /* Convert an integer to a Q5.2 value */
1075 #define INT_TO_Q52(i) ((i) << 2)
1076 /* Convert a Q5.2 value to an integer (precision loss!) */
1077 #define Q52_TO_INT(q52) ((q52) >> 2)
1078 /* Macros for printing a value in Q5.2 format */
1079 #define Q52_FMT "%u.%u"
1080 #define Q52_ARG(q52) Q52_TO_INT(q52), ((((q52) & 0x3) * 100) / 4)
1081
1082 #endif /* B43_H_ */
1083