1config MMU 2 def_bool n 3 4config FPU 5 def_bool n 6 7config RWSEM_GENERIC_SPINLOCK 8 def_bool y 9 10config RWSEM_XCHGADD_ALGORITHM 11 def_bool n 12 13config BLACKFIN 14 def_bool y 15 select HAVE_ARCH_KGDB 16 select HAVE_ARCH_TRACEHOOK 17 select HAVE_DYNAMIC_FTRACE 18 select HAVE_FTRACE_MCOUNT_RECORD 19 select HAVE_FUNCTION_GRAPH_TRACER 20 select HAVE_FUNCTION_TRACER 21 select HAVE_FUNCTION_TRACE_MCOUNT_TEST 22 select HAVE_IDE 23 select HAVE_KERNEL_GZIP if RAMKERNEL 24 select HAVE_KERNEL_BZIP2 if RAMKERNEL 25 select HAVE_KERNEL_LZMA if RAMKERNEL 26 select HAVE_KERNEL_LZO if RAMKERNEL 27 select HAVE_OPROFILE 28 select HAVE_PERF_EVENTS 29 select ARCH_HAVE_CUSTOM_GPIO_H 30 select ARCH_REQUIRE_GPIOLIB 31 select HAVE_UID16 32 select HAVE_UNDERSCORE_SYMBOL_PREFIX 33 select VIRT_TO_BUS 34 select ARCH_WANT_IPC_PARSE_VERSION 35 select HAVE_GENERIC_HARDIRQS 36 select GENERIC_ATOMIC64 37 select GENERIC_IRQ_PROBE 38 select USE_GENERIC_SMP_HELPERS if SMP 39 select HAVE_NMI_WATCHDOG if NMI_WATCHDOG 40 select GENERIC_SMP_IDLE_THREAD 41 select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS 42 select HAVE_MOD_ARCH_SPECIFIC 43 select MODULES_USE_ELF_RELA 44 45config GENERIC_CSUM 46 def_bool y 47 48config GENERIC_BUG 49 def_bool y 50 depends on BUG 51 52config ZONE_DMA 53 def_bool y 54 55config FORCE_MAX_ZONEORDER 56 int 57 default "14" 58 59config GENERIC_CALIBRATE_DELAY 60 def_bool y 61 62config LOCKDEP_SUPPORT 63 def_bool y 64 65config STACKTRACE_SUPPORT 66 def_bool y 67 68config TRACE_IRQFLAGS_SUPPORT 69 def_bool y 70 71source "init/Kconfig" 72 73source "kernel/Kconfig.preempt" 74 75source "kernel/Kconfig.freezer" 76 77menu "Blackfin Processor Options" 78 79comment "Processor and Board Settings" 80 81choice 82 prompt "CPU" 83 default BF533 84 85config BF512 86 bool "BF512" 87 help 88 BF512 Processor Support. 89 90config BF514 91 bool "BF514" 92 help 93 BF514 Processor Support. 94 95config BF516 96 bool "BF516" 97 help 98 BF516 Processor Support. 99 100config BF518 101 bool "BF518" 102 help 103 BF518 Processor Support. 104 105config BF522 106 bool "BF522" 107 help 108 BF522 Processor Support. 109 110config BF523 111 bool "BF523" 112 help 113 BF523 Processor Support. 114 115config BF524 116 bool "BF524" 117 help 118 BF524 Processor Support. 119 120config BF525 121 bool "BF525" 122 help 123 BF525 Processor Support. 124 125config BF526 126 bool "BF526" 127 help 128 BF526 Processor Support. 129 130config BF527 131 bool "BF527" 132 help 133 BF527 Processor Support. 134 135config BF531 136 bool "BF531" 137 help 138 BF531 Processor Support. 139 140config BF532 141 bool "BF532" 142 help 143 BF532 Processor Support. 144 145config BF533 146 bool "BF533" 147 help 148 BF533 Processor Support. 149 150config BF534 151 bool "BF534" 152 help 153 BF534 Processor Support. 154 155config BF536 156 bool "BF536" 157 help 158 BF536 Processor Support. 159 160config BF537 161 bool "BF537" 162 help 163 BF537 Processor Support. 164 165config BF538 166 bool "BF538" 167 help 168 BF538 Processor Support. 169 170config BF539 171 bool "BF539" 172 help 173 BF539 Processor Support. 174 175config BF542_std 176 bool "BF542" 177 help 178 BF542 Processor Support. 179 180config BF542M 181 bool "BF542m" 182 help 183 BF542 Processor Support. 184 185config BF544_std 186 bool "BF544" 187 help 188 BF544 Processor Support. 189 190config BF544M 191 bool "BF544m" 192 help 193 BF544 Processor Support. 194 195config BF547_std 196 bool "BF547" 197 help 198 BF547 Processor Support. 199 200config BF547M 201 bool "BF547m" 202 help 203 BF547 Processor Support. 204 205config BF548_std 206 bool "BF548" 207 help 208 BF548 Processor Support. 209 210config BF548M 211 bool "BF548m" 212 help 213 BF548 Processor Support. 214 215config BF549_std 216 bool "BF549" 217 help 218 BF549 Processor Support. 219 220config BF549M 221 bool "BF549m" 222 help 223 BF549 Processor Support. 224 225config BF561 226 bool "BF561" 227 help 228 BF561 Processor Support. 229 230config BF609 231 bool "BF609" 232 select CLKDEV_LOOKUP 233 help 234 BF609 Processor Support. 235 236endchoice 237 238config SMP 239 depends on BF561 240 select TICKSOURCE_CORETMR 241 bool "Symmetric multi-processing support" 242 ---help--- 243 This enables support for systems with more than one CPU, 244 like the dual core BF561. If you have a system with only one 245 CPU, say N. If you have a system with more than one CPU, say Y. 246 247 If you don't know what to do here, say N. 248 249config NR_CPUS 250 int 251 depends on SMP 252 default 2 if BF561 253 254config HOTPLUG_CPU 255 bool "Support for hot-pluggable CPUs" 256 depends on SMP && HOTPLUG 257 default y 258 259config BF_REV_MIN 260 int 261 default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x 262 default 2 if (BF537 || BF536 || BF534) 263 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM) 264 default 4 if (BF538 || BF539) 265 266config BF_REV_MAX 267 int 268 default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x 269 default 3 if (BF537 || BF536 || BF534 || BF54xM) 270 default 5 if (BF561 || BF538 || BF539) 271 default 6 if (BF533 || BF532 || BF531) 272 273choice 274 prompt "Silicon Rev" 275 default BF_REV_0_0 if (BF51x || BF52x || BF60x) 276 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM)) 277 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) 278 279config BF_REV_0_0 280 bool "0.0" 281 depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x) 282 283config BF_REV_0_1 284 bool "0.1" 285 depends on (BF51x || BF52x || (BF54x && !BF54xM)) 286 287config BF_REV_0_2 288 bool "0.2" 289 depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM)) 290 291config BF_REV_0_3 292 bool "0.3" 293 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) 294 295config BF_REV_0_4 296 bool "0.4" 297 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539 || BF54x) 298 299config BF_REV_0_5 300 bool "0.5" 301 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) 302 303config BF_REV_0_6 304 bool "0.6" 305 depends on (BF533 || BF532 || BF531) 306 307config BF_REV_ANY 308 bool "any" 309 310config BF_REV_NONE 311 bool "none" 312 313endchoice 314 315config BF53x 316 bool 317 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) 318 default y 319 320config MEM_MT48LC64M4A2FB_7E 321 bool 322 depends on (BFIN533_STAMP) 323 default y 324 325config MEM_MT48LC16M16A2TG_75 326 bool 327 depends on (BFIN533_EZKIT || BFIN561_EZKIT \ 328 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \ 329 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \ 330 || BFIN527_BLUETECHNIX_CM) 331 default y 332 333config MEM_MT48LC32M8A2_75 334 bool 335 depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) 336 default y 337 338config MEM_MT48LC8M32B2B5_7 339 bool 340 depends on (BFIN561_BLUETECHNIX_CM) 341 default y 342 343config MEM_MT48LC32M16A2TG_75 344 bool 345 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL) 346 default y 347 348config MEM_MT48H32M16LFCJ_75 349 bool 350 depends on (BFIN526_EZBRD) 351 default y 352 353config MEM_MT47H64M16 354 bool 355 depends on (BFIN609_EZKIT) 356 default y 357 358source "arch/blackfin/mach-bf518/Kconfig" 359source "arch/blackfin/mach-bf527/Kconfig" 360source "arch/blackfin/mach-bf533/Kconfig" 361source "arch/blackfin/mach-bf561/Kconfig" 362source "arch/blackfin/mach-bf537/Kconfig" 363source "arch/blackfin/mach-bf538/Kconfig" 364source "arch/blackfin/mach-bf548/Kconfig" 365source "arch/blackfin/mach-bf609/Kconfig" 366 367menu "Board customizations" 368 369config CMDLINE_BOOL 370 bool "Default bootloader kernel arguments" 371 372config CMDLINE 373 string "Initial kernel command string" 374 depends on CMDLINE_BOOL 375 default "console=ttyBF0,57600" 376 help 377 If you don't have a boot loader capable of passing a command line string 378 to the kernel, you may specify one here. As a minimum, you should specify 379 the memory size and the root device (e.g., mem=8M, root=/dev/nfs). 380 381config BOOT_LOAD 382 hex "Kernel load address for booting" 383 default "0x1000" 384 range 0x1000 0x20000000 385 help 386 This option allows you to set the load address of the kernel. 387 This can be useful if you are on a board which has a small amount 388 of memory or you wish to reserve some memory at the beginning of 389 the address space. 390 391 Note that you need to keep this value above 4k (0x1000) as this 392 memory region is used to capture NULL pointer references as well 393 as some core kernel functions. 394 395config PHY_RAM_BASE_ADDRESS 396 hex "Physical RAM Base" 397 default 0x0 398 help 399 set BF609 FPGA physical SRAM base address 400 401config ROM_BASE 402 hex "Kernel ROM Base" 403 depends on ROMKERNEL 404 default "0x20040040" 405 range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x) 406 range 0x20000000 0x30000000 if (BF54x || BF561) 407 range 0xB0000000 0xC0000000 if (BF60x) 408 help 409 Make sure your ROM base does not include any file-header 410 information that is prepended to the kernel. 411 412 For example, the bootable U-Boot format (created with 413 mkimage) has a 64 byte header (0x40). So while the image 414 you write to flash might start at say 0x20080000, you have 415 to add 0x40 to get the kernel's ROM base as it will come 416 after the header. 417 418comment "Clock/PLL Setup" 419 420config CLKIN_HZ 421 int "Frequency of the crystal on the board in Hz" 422 default "10000000" if BFIN532_IP0X 423 default "11059200" if BFIN533_STAMP 424 default "24576000" if PNAV10 425 default "25000000" # most people use this 426 default "27000000" if BFIN533_EZKIT 427 default "30000000" if BFIN561_EZKIT 428 default "24000000" if BFIN527_AD7160EVAL 429 help 430 The frequency of CLKIN crystal oscillator on the board in Hz. 431 Warning: This value should match the crystal on the board. Otherwise, 432 peripherals won't work properly. 433 434config BFIN_KERNEL_CLOCK 435 bool "Re-program Clocks while Kernel boots?" 436 default n 437 help 438 This option decides if kernel clocks are re-programed from the 439 bootloader settings. If the clocks are not set, the SDRAM settings 440 are also not changed, and the Bootloader does 100% of the hardware 441 configuration. 442 443config PLL_BYPASS 444 bool "Bypass PLL" 445 depends on BFIN_KERNEL_CLOCK && (!BF60x) 446 default n 447 448config CLKIN_HALF 449 bool "Half Clock In" 450 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) 451 default n 452 help 453 If this is set the clock will be divided by 2, before it goes to the PLL. 454 455config VCO_MULT 456 int "VCO Multiplier" 457 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) 458 range 1 64 459 default "22" if BFIN533_EZKIT 460 default "45" if BFIN533_STAMP 461 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) 462 default "22" if BFIN533_BLUETECHNIX_CM 463 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) 464 default "20" if (BFIN561_EZKIT || BF609) 465 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) 466 default "25" if BFIN527_AD7160EVAL 467 help 468 This controls the frequency of the on-chip PLL. This can be between 1 and 64. 469 PLL Frequency = (Crystal Frequency) * (this setting) 470 471choice 472 prompt "Core Clock Divider" 473 depends on BFIN_KERNEL_CLOCK 474 default CCLK_DIV_1 475 help 476 This sets the frequency of the core. It can be 1, 2, 4 or 8 477 Core Frequency = (PLL frequency) / (this setting) 478 479config CCLK_DIV_1 480 bool "1" 481 482config CCLK_DIV_2 483 bool "2" 484 485config CCLK_DIV_4 486 bool "4" 487 488config CCLK_DIV_8 489 bool "8" 490endchoice 491 492config SCLK_DIV 493 int "System Clock Divider" 494 depends on BFIN_KERNEL_CLOCK 495 range 1 15 496 default 4 497 help 498 This sets the frequency of the system clock (including SDRAM or DDR) on 499 !BF60x else it set the clock for system buses and provides the 500 source from which SCLK0 and SCLK1 are derived. 501 This can be between 1 and 15 502 System Clock = (PLL frequency) / (this setting) 503 504config SCLK0_DIV 505 int "System Clock0 Divider" 506 depends on BFIN_KERNEL_CLOCK && BF60x 507 range 1 15 508 default 1 509 help 510 This sets the frequency of the system clock0 for PVP and all other 511 peripherals not clocked by SCLK1. 512 This can be between 1 and 15 513 System Clock0 = (System Clock) / (this setting) 514 515config SCLK1_DIV 516 int "System Clock1 Divider" 517 depends on BFIN_KERNEL_CLOCK && BF60x 518 range 1 15 519 default 1 520 help 521 This sets the frequency of the system clock1 (including SPORT, SPI and ACM). 522 This can be between 1 and 15 523 System Clock1 = (System Clock) / (this setting) 524 525config DCLK_DIV 526 int "DDR Clock Divider" 527 depends on BFIN_KERNEL_CLOCK && BF60x 528 range 1 15 529 default 2 530 help 531 This sets the frequency of the DDR memory. 532 This can be between 1 and 15 533 DDR Clock = (PLL frequency) / (this setting) 534 535choice 536 prompt "DDR SDRAM Chip Type" 537 depends on BFIN_KERNEL_CLOCK 538 depends on BF54x 539 default MEM_MT46V32M16_5B 540 541config MEM_MT46V32M16_6T 542 bool "MT46V32M16_6T" 543 544config MEM_MT46V32M16_5B 545 bool "MT46V32M16_5B" 546endchoice 547 548choice 549 prompt "DDR/SDRAM Timing" 550 depends on BFIN_KERNEL_CLOCK && !BF60x 551 default BFIN_KERNEL_CLOCK_MEMINIT_CALC 552 help 553 This option allows you to specify Blackfin SDRAM/DDR Timing parameters 554 The calculated SDRAM timing parameters may not be 100% 555 accurate - This option is therefore marked experimental. 556 557config BFIN_KERNEL_CLOCK_MEMINIT_CALC 558 bool "Calculate Timings" 559 560config BFIN_KERNEL_CLOCK_MEMINIT_SPEC 561 bool "Provide accurate Timings based on target SCLK" 562 help 563 Please consult the Blackfin Hardware Reference Manuals as well 564 as the memory device datasheet. 565 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram 566endchoice 567 568menu "Memory Init Control" 569 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC 570 571config MEM_DDRCTL0 572 depends on BF54x 573 hex "DDRCTL0" 574 default 0x0 575 576config MEM_DDRCTL1 577 depends on BF54x 578 hex "DDRCTL1" 579 default 0x0 580 581config MEM_DDRCTL2 582 depends on BF54x 583 hex "DDRCTL2" 584 default 0x0 585 586config MEM_EBIU_DDRQUE 587 depends on BF54x 588 hex "DDRQUE" 589 default 0x0 590 591config MEM_SDRRC 592 depends on !BF54x 593 hex "SDRRC" 594 default 0x0 595 596config MEM_SDGCTL 597 depends on !BF54x 598 hex "SDGCTL" 599 default 0x0 600endmenu 601 602# 603# Max & Min Speeds for various Chips 604# 605config MAX_VCO_HZ 606 int 607 default 400000000 if BF512 608 default 400000000 if BF514 609 default 400000000 if BF516 610 default 400000000 if BF518 611 default 400000000 if BF522 612 default 600000000 if BF523 613 default 400000000 if BF524 614 default 600000000 if BF525 615 default 400000000 if BF526 616 default 600000000 if BF527 617 default 400000000 if BF531 618 default 400000000 if BF532 619 default 750000000 if BF533 620 default 500000000 if BF534 621 default 400000000 if BF536 622 default 600000000 if BF537 623 default 533333333 if BF538 624 default 533333333 if BF539 625 default 600000000 if BF542 626 default 533333333 if BF544 627 default 600000000 if BF547 628 default 600000000 if BF548 629 default 533333333 if BF549 630 default 600000000 if BF561 631 default 800000000 if BF609 632 633config MIN_VCO_HZ 634 int 635 default 50000000 636 637config MAX_SCLK_HZ 638 int 639 default 200000000 if BF609 640 default 133333333 641 642config MIN_SCLK_HZ 643 int 644 default 27000000 645 646comment "Kernel Timer/Scheduler" 647 648source kernel/Kconfig.hz 649 650config SET_GENERIC_CLOCKEVENTS 651 bool "Generic clock events" 652 default y 653 select GENERIC_CLOCKEVENTS 654 655menu "Clock event device" 656 depends on GENERIC_CLOCKEVENTS 657config TICKSOURCE_GPTMR0 658 bool "GPTimer0" 659 depends on !SMP 660 select BFIN_GPTIMERS 661 662config TICKSOURCE_CORETMR 663 bool "Core timer" 664 default y 665endmenu 666 667menu "Clock souce" 668 depends on GENERIC_CLOCKEVENTS 669config CYCLES_CLOCKSOURCE 670 bool "CYCLES" 671 default y 672 depends on !BFIN_SCRATCH_REG_CYCLES 673 depends on !SMP 674 help 675 If you say Y here, you will enable support for using the 'cycles' 676 registers as a clock source. Doing so means you will be unable to 677 safely write to the 'cycles' register during runtime. You will 678 still be able to read it (such as for performance monitoring), but 679 writing the registers will most likely crash the kernel. 680 681config GPTMR0_CLOCKSOURCE 682 bool "GPTimer0" 683 select BFIN_GPTIMERS 684 depends on !TICKSOURCE_GPTMR0 685endmenu 686 687comment "Misc" 688 689choice 690 prompt "Blackfin Exception Scratch Register" 691 default BFIN_SCRATCH_REG_RETN 692 help 693 Select the resource to reserve for the Exception handler: 694 - RETN: Non-Maskable Interrupt (NMI) 695 - RETE: Exception Return (JTAG/ICE) 696 - CYCLES: Performance counter 697 698 If you are unsure, please select "RETN". 699 700config BFIN_SCRATCH_REG_RETN 701 bool "RETN" 702 help 703 Use the RETN register in the Blackfin exception handler 704 as a stack scratch register. This means you cannot 705 safely use NMI on the Blackfin while running Linux, but 706 you can debug the system with a JTAG ICE and use the 707 CYCLES performance registers. 708 709 If you are unsure, please select "RETN". 710 711config BFIN_SCRATCH_REG_RETE 712 bool "RETE" 713 help 714 Use the RETE register in the Blackfin exception handler 715 as a stack scratch register. This means you cannot 716 safely use a JTAG ICE while debugging a Blackfin board, 717 but you can safely use the CYCLES performance registers 718 and the NMI. 719 720 If you are unsure, please select "RETN". 721 722config BFIN_SCRATCH_REG_CYCLES 723 bool "CYCLES" 724 help 725 Use the CYCLES register in the Blackfin exception handler 726 as a stack scratch register. This means you cannot 727 safely use the CYCLES performance registers on a Blackfin 728 board at anytime, but you can debug the system with a JTAG 729 ICE and use the NMI. 730 731 If you are unsure, please select "RETN". 732 733endchoice 734 735endmenu 736 737 738menu "Blackfin Kernel Optimizations" 739 740comment "Memory Optimizations" 741 742config I_ENTRY_L1 743 bool "Locate interrupt entry code in L1 Memory" 744 default y 745 depends on !SMP 746 help 747 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked 748 into L1 instruction memory. (less latency) 749 750config EXCPT_IRQ_SYSC_L1 751 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" 752 default y 753 depends on !SMP 754 help 755 If enabled, the entire ASM lowlevel exception and interrupt entry code 756 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. 757 (less latency) 758 759config DO_IRQ_L1 760 bool "Locate frequently called do_irq dispatcher function in L1 Memory" 761 default y 762 depends on !SMP 763 help 764 If enabled, the frequently called do_irq dispatcher function is linked 765 into L1 instruction memory. (less latency) 766 767config CORE_TIMER_IRQ_L1 768 bool "Locate frequently called timer_interrupt() function in L1 Memory" 769 default y 770 depends on !SMP 771 help 772 If enabled, the frequently called timer_interrupt() function is linked 773 into L1 instruction memory. (less latency) 774 775config IDLE_L1 776 bool "Locate frequently idle function in L1 Memory" 777 default y 778 depends on !SMP 779 help 780 If enabled, the frequently called idle function is linked 781 into L1 instruction memory. (less latency) 782 783config SCHEDULE_L1 784 bool "Locate kernel schedule function in L1 Memory" 785 default y 786 depends on !SMP 787 help 788 If enabled, the frequently called kernel schedule is linked 789 into L1 instruction memory. (less latency) 790 791config ARITHMETIC_OPS_L1 792 bool "Locate kernel owned arithmetic functions in L1 Memory" 793 default y 794 depends on !SMP 795 help 796 If enabled, arithmetic functions are linked 797 into L1 instruction memory. (less latency) 798 799config ACCESS_OK_L1 800 bool "Locate access_ok function in L1 Memory" 801 default y 802 depends on !SMP 803 help 804 If enabled, the access_ok function is linked 805 into L1 instruction memory. (less latency) 806 807config MEMSET_L1 808 bool "Locate memset function in L1 Memory" 809 default y 810 depends on !SMP 811 help 812 If enabled, the memset function is linked 813 into L1 instruction memory. (less latency) 814 815config MEMCPY_L1 816 bool "Locate memcpy function in L1 Memory" 817 default y 818 depends on !SMP 819 help 820 If enabled, the memcpy function is linked 821 into L1 instruction memory. (less latency) 822 823config STRCMP_L1 824 bool "locate strcmp function in L1 Memory" 825 default y 826 depends on !SMP 827 help 828 If enabled, the strcmp function is linked 829 into L1 instruction memory (less latency). 830 831config STRNCMP_L1 832 bool "locate strncmp function in L1 Memory" 833 default y 834 depends on !SMP 835 help 836 If enabled, the strncmp function is linked 837 into L1 instruction memory (less latency). 838 839config STRCPY_L1 840 bool "locate strcpy function in L1 Memory" 841 default y 842 depends on !SMP 843 help 844 If enabled, the strcpy function is linked 845 into L1 instruction memory (less latency). 846 847config STRNCPY_L1 848 bool "locate strncpy function in L1 Memory" 849 default y 850 depends on !SMP 851 help 852 If enabled, the strncpy function is linked 853 into L1 instruction memory (less latency). 854 855config SYS_BFIN_SPINLOCK_L1 856 bool "Locate sys_bfin_spinlock function in L1 Memory" 857 default y 858 depends on !SMP 859 help 860 If enabled, sys_bfin_spinlock function is linked 861 into L1 instruction memory. (less latency) 862 863config IP_CHECKSUM_L1 864 bool "Locate IP Checksum function in L1 Memory" 865 default n 866 depends on !SMP 867 help 868 If enabled, the IP Checksum function is linked 869 into L1 instruction memory. (less latency) 870 871config CACHELINE_ALIGNED_L1 872 bool "Locate cacheline_aligned data to L1 Data Memory" 873 default y if !BF54x 874 default n if BF54x 875 depends on !SMP && !BF531 && !CRC32 876 help 877 If enabled, cacheline_aligned data is linked 878 into L1 data memory. (less latency) 879 880config SYSCALL_TAB_L1 881 bool "Locate Syscall Table L1 Data Memory" 882 default n 883 depends on !SMP && !BF531 884 help 885 If enabled, the Syscall LUT is linked 886 into L1 data memory. (less latency) 887 888config CPLB_SWITCH_TAB_L1 889 bool "Locate CPLB Switch Tables L1 Data Memory" 890 default n 891 depends on !SMP && !BF531 892 help 893 If enabled, the CPLB Switch Tables are linked 894 into L1 data memory. (less latency) 895 896config ICACHE_FLUSH_L1 897 bool "Locate icache flush funcs in L1 Inst Memory" 898 default y 899 help 900 If enabled, the Blackfin icache flushing functions are linked 901 into L1 instruction memory. 902 903 Note that this might be required to address anomalies, but 904 these functions are pretty small, so it shouldn't be too bad. 905 If you are using a processor affected by an anomaly, the build 906 system will double check for you and prevent it. 907 908config DCACHE_FLUSH_L1 909 bool "Locate dcache flush funcs in L1 Inst Memory" 910 default y 911 depends on !SMP 912 help 913 If enabled, the Blackfin dcache flushing functions are linked 914 into L1 instruction memory. 915 916config APP_STACK_L1 917 bool "Support locating application stack in L1 Scratch Memory" 918 default y 919 depends on !SMP 920 help 921 If enabled the application stack can be located in L1 922 scratch memory (less latency). 923 924 Currently only works with FLAT binaries. 925 926config EXCEPTION_L1_SCRATCH 927 bool "Locate exception stack in L1 Scratch Memory" 928 default n 929 depends on !SMP && !APP_STACK_L1 930 help 931 Whenever an exception occurs, use the L1 Scratch memory for 932 stack storage. You cannot place the stacks of FLAT binaries 933 in L1 when using this option. 934 935 If you don't use L1 Scratch, then you should say Y here. 936 937comment "Speed Optimizations" 938config BFIN_INS_LOWOVERHEAD 939 bool "ins[bwl] low overhead, higher interrupt latency" 940 default y 941 depends on !SMP 942 help 943 Reads on the Blackfin are speculative. In Blackfin terms, this means 944 they can be interrupted at any time (even after they have been issued 945 on to the external bus), and re-issued after the interrupt occurs. 946 For memory - this is not a big deal, since memory does not change if 947 it sees a read. 948 949 If a FIFO is sitting on the end of the read, it will see two reads, 950 when the core only sees one since the FIFO receives both the read 951 which is cancelled (and not delivered to the core) and the one which 952 is re-issued (which is delivered to the core). 953 954 To solve this, interrupts are turned off before reads occur to 955 I/O space. This option controls which the overhead/latency of 956 controlling interrupts during this time 957 "n" turns interrupts off every read 958 (higher overhead, but lower interrupt latency) 959 "y" turns interrupts off every loop 960 (low overhead, but longer interrupt latency) 961 962 default behavior is to leave this set to on (type "Y"). If you are experiencing 963 interrupt latency issues, it is safe and OK to turn this off. 964 965endmenu 966 967choice 968 prompt "Kernel executes from" 969 help 970 Choose the memory type that the kernel will be running in. 971 972config RAMKERNEL 973 bool "RAM" 974 help 975 The kernel will be resident in RAM when running. 976 977config ROMKERNEL 978 bool "ROM" 979 help 980 The kernel will be resident in FLASH/ROM when running. 981 982endchoice 983 984# Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both 985config XIP_KERNEL 986 bool 987 default y 988 depends on ROMKERNEL 989 990source "mm/Kconfig" 991 992config BFIN_GPTIMERS 993 tristate "Enable Blackfin General Purpose Timers API" 994 default n 995 help 996 Enable support for the General Purpose Timers API. If you 997 are unsure, say N. 998 999 To compile this driver as a module, choose M here: the module 1000 will be called gptimers. 1001 1002choice 1003 prompt "Uncached DMA region" 1004 default DMA_UNCACHED_1M 1005config DMA_UNCACHED_32M 1006 bool "Enable 32M DMA region" 1007config DMA_UNCACHED_16M 1008 bool "Enable 16M DMA region" 1009config DMA_UNCACHED_8M 1010 bool "Enable 8M DMA region" 1011config DMA_UNCACHED_4M 1012 bool "Enable 4M DMA region" 1013config DMA_UNCACHED_2M 1014 bool "Enable 2M DMA region" 1015config DMA_UNCACHED_1M 1016 bool "Enable 1M DMA region" 1017config DMA_UNCACHED_512K 1018 bool "Enable 512K DMA region" 1019config DMA_UNCACHED_256K 1020 bool "Enable 256K DMA region" 1021config DMA_UNCACHED_128K 1022 bool "Enable 128K DMA region" 1023config DMA_UNCACHED_NONE 1024 bool "Disable DMA region" 1025endchoice 1026 1027 1028comment "Cache Support" 1029 1030config BFIN_ICACHE 1031 bool "Enable ICACHE" 1032 default y 1033config BFIN_EXTMEM_ICACHEABLE 1034 bool "Enable ICACHE for external memory" 1035 depends on BFIN_ICACHE 1036 default y 1037config BFIN_L2_ICACHEABLE 1038 bool "Enable ICACHE for L2 SRAM" 1039 depends on BFIN_ICACHE 1040 depends on (BF54x || BF561 || BF60x) && !SMP 1041 default n 1042 1043config BFIN_DCACHE 1044 bool "Enable DCACHE" 1045 default y 1046config BFIN_DCACHE_BANKA 1047 bool "Enable only 16k BankA DCACHE - BankB is SRAM" 1048 depends on BFIN_DCACHE && !BF531 1049 default n 1050config BFIN_EXTMEM_DCACHEABLE 1051 bool "Enable DCACHE for external memory" 1052 depends on BFIN_DCACHE 1053 default y 1054choice 1055 prompt "External memory DCACHE policy" 1056 depends on BFIN_EXTMEM_DCACHEABLE 1057 default BFIN_EXTMEM_WRITEBACK if !SMP 1058 default BFIN_EXTMEM_WRITETHROUGH if SMP 1059config BFIN_EXTMEM_WRITEBACK 1060 bool "Write back" 1061 depends on !SMP 1062 help 1063 Write Back Policy: 1064 Cached data will be written back to SDRAM only when needed. 1065 This can give a nice increase in performance, but beware of 1066 broken drivers that do not properly invalidate/flush their 1067 cache. 1068 1069 Write Through Policy: 1070 Cached data will always be written back to SDRAM when the 1071 cache is updated. This is a completely safe setting, but 1072 performance is worse than Write Back. 1073 1074 If you are unsure of the options and you want to be safe, 1075 then go with Write Through. 1076 1077config BFIN_EXTMEM_WRITETHROUGH 1078 bool "Write through" 1079 help 1080 Write Back Policy: 1081 Cached data will be written back to SDRAM only when needed. 1082 This can give a nice increase in performance, but beware of 1083 broken drivers that do not properly invalidate/flush their 1084 cache. 1085 1086 Write Through Policy: 1087 Cached data will always be written back to SDRAM when the 1088 cache is updated. This is a completely safe setting, but 1089 performance is worse than Write Back. 1090 1091 If you are unsure of the options and you want to be safe, 1092 then go with Write Through. 1093 1094endchoice 1095 1096config BFIN_L2_DCACHEABLE 1097 bool "Enable DCACHE for L2 SRAM" 1098 depends on BFIN_DCACHE 1099 depends on (BF54x || BF561 || BF60x) && !SMP 1100 default n 1101choice 1102 prompt "L2 SRAM DCACHE policy" 1103 depends on BFIN_L2_DCACHEABLE 1104 default BFIN_L2_WRITEBACK 1105config BFIN_L2_WRITEBACK 1106 bool "Write back" 1107 1108config BFIN_L2_WRITETHROUGH 1109 bool "Write through" 1110endchoice 1111 1112 1113comment "Memory Protection Unit" 1114config MPU 1115 bool "Enable the memory protection unit" 1116 default n 1117 help 1118 Use the processor's MPU to protect applications from accessing 1119 memory they do not own. This comes at a performance penalty 1120 and is recommended only for debugging. 1121 1122comment "Asynchronous Memory Configuration" 1123 1124menu "EBIU_AMGCTL Global Control" 1125 depends on !BF60x 1126config C_AMCKEN 1127 bool "Enable CLKOUT" 1128 default y 1129 1130config C_CDPRIO 1131 bool "DMA has priority over core for ext. accesses" 1132 default n 1133 1134config C_B0PEN 1135 depends on BF561 1136 bool "Bank 0 16 bit packing enable" 1137 default y 1138 1139config C_B1PEN 1140 depends on BF561 1141 bool "Bank 1 16 bit packing enable" 1142 default y 1143 1144config C_B2PEN 1145 depends on BF561 1146 bool "Bank 2 16 bit packing enable" 1147 default y 1148 1149config C_B3PEN 1150 depends on BF561 1151 bool "Bank 3 16 bit packing enable" 1152 default n 1153 1154choice 1155 prompt "Enable Asynchronous Memory Banks" 1156 default C_AMBEN_ALL 1157 1158config C_AMBEN 1159 bool "Disable All Banks" 1160 1161config C_AMBEN_B0 1162 bool "Enable Bank 0" 1163 1164config C_AMBEN_B0_B1 1165 bool "Enable Bank 0 & 1" 1166 1167config C_AMBEN_B0_B1_B2 1168 bool "Enable Bank 0 & 1 & 2" 1169 1170config C_AMBEN_ALL 1171 bool "Enable All Banks" 1172endchoice 1173endmenu 1174 1175menu "EBIU_AMBCTL Control" 1176 depends on !BF60x 1177config BANK_0 1178 hex "Bank 0 (AMBCTL0.L)" 1179 default 0x7BB0 1180 help 1181 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are 1182 used to control the Asynchronous Memory Bank 0 settings. 1183 1184config BANK_1 1185 hex "Bank 1 (AMBCTL0.H)" 1186 default 0x7BB0 1187 default 0x5558 if BF54x 1188 help 1189 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are 1190 used to control the Asynchronous Memory Bank 1 settings. 1191 1192config BANK_2 1193 hex "Bank 2 (AMBCTL1.L)" 1194 default 0x7BB0 1195 help 1196 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are 1197 used to control the Asynchronous Memory Bank 2 settings. 1198 1199config BANK_3 1200 hex "Bank 3 (AMBCTL1.H)" 1201 default 0x99B3 1202 help 1203 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are 1204 used to control the Asynchronous Memory Bank 3 settings. 1205 1206endmenu 1207 1208config EBIU_MBSCTLVAL 1209 hex "EBIU Bank Select Control Register" 1210 depends on BF54x 1211 default 0 1212 1213config EBIU_MODEVAL 1214 hex "Flash Memory Mode Control Register" 1215 depends on BF54x 1216 default 1 1217 1218config EBIU_FCTLVAL 1219 hex "Flash Memory Bank Control Register" 1220 depends on BF54x 1221 default 6 1222endmenu 1223 1224############################################################################# 1225menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" 1226 1227config PCI 1228 bool "PCI support" 1229 depends on BROKEN 1230 help 1231 Support for PCI bus. 1232 1233source "drivers/pci/Kconfig" 1234 1235source "drivers/pcmcia/Kconfig" 1236 1237source "drivers/pci/hotplug/Kconfig" 1238 1239endmenu 1240 1241menu "Executable file formats" 1242 1243source "fs/Kconfig.binfmt" 1244 1245endmenu 1246 1247menu "Power management options" 1248 1249source "kernel/power/Kconfig" 1250 1251config ARCH_SUSPEND_POSSIBLE 1252 def_bool y 1253 1254choice 1255 prompt "Standby Power Saving Mode" 1256 depends on PM && !BF60x 1257 default PM_BFIN_SLEEP_DEEPER 1258config PM_BFIN_SLEEP_DEEPER 1259 bool "Sleep Deeper" 1260 help 1261 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic 1262 power dissipation by disabling the clock to the processor core (CCLK). 1263 Furthermore, Standby sets the internal power supply voltage (VDDINT) 1264 to 0.85 V to provide the greatest power savings, while preserving the 1265 processor state. 1266 The PLL and system clock (SCLK) continue to operate at a very low 1267 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, 1268 the SDRAM is put into Self Refresh Mode. Typically an external event 1269 such as GPIO interrupt or RTC activity wakes up the processor. 1270 Various Peripherals such as UART, SPORT, PPI may not function as 1271 normal during Sleep Deeper, due to the reduced SCLK frequency. 1272 When in the sleep mode, system DMA access to L1 memory is not supported. 1273 1274 If unsure, select "Sleep Deeper". 1275 1276config PM_BFIN_SLEEP 1277 bool "Sleep" 1278 help 1279 Sleep Mode (High Power Savings) - The sleep mode reduces power 1280 dissipation by disabling the clock to the processor core (CCLK). 1281 The PLL and system clock (SCLK), however, continue to operate in 1282 this mode. Typically an external event or RTC activity will wake 1283 up the processor. When in the sleep mode, system DMA access to L1 1284 memory is not supported. 1285 1286 If unsure, select "Sleep Deeper". 1287endchoice 1288 1289comment "Possible Suspend Mem / Hibernate Wake-Up Sources" 1290 depends on PM 1291 1292config PM_BFIN_WAKE_PH6 1293 bool "Allow Wake-Up from on-chip PHY or PH6 GP" 1294 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537) 1295 default n 1296 help 1297 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) 1298 1299config PM_BFIN_WAKE_GP 1300 bool "Allow Wake-Up from GPIOs" 1301 depends on PM && BF54x 1302 default n 1303 help 1304 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) 1305 (all processors, except ADSP-BF549). This option sets 1306 the general-purpose wake-up enable (GPWE) control bit to enable 1307 wake-up upon detection of an active low signal on the /GPW (PH7) pin. 1308 On ADSP-BF549 this option enables the same functionality on the 1309 /MRXON pin also PH7. 1310 1311config PM_BFIN_WAKE_PA15 1312 bool "Allow Wake-Up from PA15" 1313 depends on PM && BF60x 1314 default n 1315 help 1316 Enable PA15 Wake-Up 1317 1318config PM_BFIN_WAKE_PA15_POL 1319 int "Wake-up priority" 1320 depends on PM_BFIN_WAKE_PA15 1321 default 0 1322 help 1323 Wake-Up priority 0(low) 1(high) 1324 1325config PM_BFIN_WAKE_PB15 1326 bool "Allow Wake-Up from PB15" 1327 depends on PM && BF60x 1328 default n 1329 help 1330 Enable PB15 Wake-Up 1331 1332config PM_BFIN_WAKE_PB15_POL 1333 int "Wake-up priority" 1334 depends on PM_BFIN_WAKE_PB15 1335 default 0 1336 help 1337 Wake-Up priority 0(low) 1(high) 1338 1339config PM_BFIN_WAKE_PC15 1340 bool "Allow Wake-Up from PC15" 1341 depends on PM && BF60x 1342 default n 1343 help 1344 Enable PC15 Wake-Up 1345 1346config PM_BFIN_WAKE_PC15_POL 1347 int "Wake-up priority" 1348 depends on PM_BFIN_WAKE_PC15 1349 default 0 1350 help 1351 Wake-Up priority 0(low) 1(high) 1352 1353config PM_BFIN_WAKE_PD06 1354 bool "Allow Wake-Up from PD06(ETH0_PHYINT)" 1355 depends on PM && BF60x 1356 default n 1357 help 1358 Enable PD06(ETH0_PHYINT) Wake-up 1359 1360config PM_BFIN_WAKE_PD06_POL 1361 int "Wake-up priority" 1362 depends on PM_BFIN_WAKE_PD06 1363 default 0 1364 help 1365 Wake-Up priority 0(low) 1(high) 1366 1367config PM_BFIN_WAKE_PE12 1368 bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)" 1369 depends on PM && BF60x 1370 default n 1371 help 1372 Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up 1373 1374config PM_BFIN_WAKE_PE12_POL 1375 int "Wake-up priority" 1376 depends on PM_BFIN_WAKE_PE12 1377 default 0 1378 help 1379 Wake-Up priority 0(low) 1(high) 1380 1381config PM_BFIN_WAKE_PG04 1382 bool "Allow Wake-Up from PG04(CAN0_RX)" 1383 depends on PM && BF60x 1384 default n 1385 help 1386 Enable PG04(CAN0_RX) Wake-up 1387 1388config PM_BFIN_WAKE_PG04_POL 1389 int "Wake-up priority" 1390 depends on PM_BFIN_WAKE_PG04 1391 default 0 1392 help 1393 Wake-Up priority 0(low) 1(high) 1394 1395config PM_BFIN_WAKE_PG13 1396 bool "Allow Wake-Up from PG13" 1397 depends on PM && BF60x 1398 default n 1399 help 1400 Enable PG13 Wake-Up 1401 1402config PM_BFIN_WAKE_PG13_POL 1403 int "Wake-up priority" 1404 depends on PM_BFIN_WAKE_PG13 1405 default 0 1406 help 1407 Wake-Up priority 0(low) 1(high) 1408 1409config PM_BFIN_WAKE_USB 1410 bool "Allow Wake-Up from (USB)" 1411 depends on PM && BF60x 1412 default n 1413 help 1414 Enable (USB) Wake-up 1415 1416config PM_BFIN_WAKE_USB_POL 1417 int "Wake-up priority" 1418 depends on PM_BFIN_WAKE_USB 1419 default 0 1420 help 1421 Wake-Up priority 0(low) 1(high) 1422 1423endmenu 1424 1425menu "CPU Frequency scaling" 1426 1427source "drivers/cpufreq/Kconfig" 1428 1429config BFIN_CPU_FREQ 1430 bool 1431 depends on CPU_FREQ 1432 select CPU_FREQ_TABLE 1433 default y 1434 1435config CPU_VOLTAGE 1436 bool "CPU Voltage scaling" 1437 depends on CPU_FREQ 1438 default n 1439 help 1440 Say Y here if you want CPU voltage scaling according to the CPU frequency. 1441 This option violates the PLL BYPASS recommendation in the Blackfin Processor 1442 manuals. There is a theoretical risk that during VDDINT transitions 1443 the PLL may unlock. 1444 1445endmenu 1446 1447source "net/Kconfig" 1448 1449source "drivers/Kconfig" 1450 1451source "drivers/firmware/Kconfig" 1452 1453source "fs/Kconfig" 1454 1455source "arch/blackfin/Kconfig.debug" 1456 1457source "security/Kconfig" 1458 1459source "crypto/Kconfig" 1460 1461source "lib/Kconfig" 1462