1 /* 2 * cpu.h: Values of the PRId register used to match up 3 * various MIPS cpu types. 4 * 5 * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 6 * Copyright (C) 2004 Maciej W. Rozycki 7 */ 8 #ifndef _ASM_CPU_H 9 #define _ASM_CPU_H 10 11 /* Assigned Company values for bits 23:16 of the PRId Register 12 (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from 13 MTI, the PRId register is defined in this (backwards compatible) 14 way: 15 16 +----------------+----------------+----------------+----------------+ 17 | Company Options| Company ID | Processor ID | Revision | 18 +----------------+----------------+----------------+----------------+ 19 31 24 23 16 15 8 7 20 21 I don't have docs for all the previous processors, but my impression is 22 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64 23 spec. 24 */ 25 26 #define PRID_COMP_LEGACY 0x000000 27 #define PRID_COMP_MIPS 0x010000 28 #define PRID_COMP_BROADCOM 0x020000 29 #define PRID_COMP_ALCHEMY 0x030000 30 #define PRID_COMP_SIBYTE 0x040000 31 #define PRID_COMP_SANDCRAFT 0x050000 32 #define PRID_COMP_NXP 0x060000 33 #define PRID_COMP_TOSHIBA 0x070000 34 #define PRID_COMP_LSI 0x080000 35 #define PRID_COMP_LEXRA 0x0b0000 36 #define PRID_COMP_NETLOGIC 0x0c0000 37 #define PRID_COMP_CAVIUM 0x0d0000 38 #define PRID_COMP_INGENIC 0xd00000 39 40 /* 41 * Assigned values for the product ID register. In order to detect a 42 * certain CPU type exactly eventually additional registers may need to 43 * be examined. These are valid when 23:16 == PRID_COMP_LEGACY 44 */ 45 #define PRID_IMP_R2000 0x0100 46 #define PRID_IMP_AU1_REV1 0x0100 47 #define PRID_IMP_AU1_REV2 0x0200 48 #define PRID_IMP_R3000 0x0200 /* Same as R2000A */ 49 #define PRID_IMP_R6000 0x0300 /* Same as R3000A */ 50 #define PRID_IMP_R4000 0x0400 51 #define PRID_IMP_R6000A 0x0600 52 #define PRID_IMP_R10000 0x0900 53 #define PRID_IMP_R4300 0x0b00 54 #define PRID_IMP_VR41XX 0x0c00 55 #define PRID_IMP_R12000 0x0e00 56 #define PRID_IMP_R14000 0x0f00 57 #define PRID_IMP_R8000 0x1000 58 #define PRID_IMP_PR4450 0x1200 59 #define PRID_IMP_R4600 0x2000 60 #define PRID_IMP_R4700 0x2100 61 #define PRID_IMP_TX39 0x2200 62 #define PRID_IMP_R4640 0x2200 63 #define PRID_IMP_R4650 0x2200 /* Same as R4640 */ 64 #define PRID_IMP_R5000 0x2300 65 #define PRID_IMP_TX49 0x2d00 66 #define PRID_IMP_SONIC 0x2400 67 #define PRID_IMP_MAGIC 0x2500 68 #define PRID_IMP_RM7000 0x2700 69 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */ 70 #define PRID_IMP_RM9000 0x3400 71 #define PRID_IMP_LOONGSON1 0x4200 72 #define PRID_IMP_R5432 0x5400 73 #define PRID_IMP_R5500 0x5500 74 #define PRID_IMP_LOONGSON2 0x6300 75 76 #define PRID_IMP_UNKNOWN 0xff00 77 78 /* 79 * These are the PRID's for when 23:16 == PRID_COMP_MIPS 80 */ 81 82 #define PRID_IMP_QEMU 0x0000 83 #define PRID_IMP_4KC 0x8000 84 #define PRID_IMP_5KC 0x8100 85 #define PRID_IMP_20KC 0x8200 86 #define PRID_IMP_4KEC 0x8400 87 #define PRID_IMP_4KSC 0x8600 88 #define PRID_IMP_25KF 0x8800 89 #define PRID_IMP_5KE 0x8900 90 #define PRID_IMP_4KECR2 0x9000 91 #define PRID_IMP_4KEMPR2 0x9100 92 #define PRID_IMP_4KSD 0x9200 93 #define PRID_IMP_24K 0x9300 94 #define PRID_IMP_34K 0x9500 95 #define PRID_IMP_24KE 0x9600 96 #define PRID_IMP_74K 0x9700 97 #define PRID_IMP_1004K 0x9900 98 #define PRID_IMP_1074K 0x9a00 99 #define PRID_IMP_M14KC 0x9c00 100 #define PRID_IMP_M14KEC 0x9e00 101 #define PRID_IMP_INTERAPTIV_UP 0xa000 102 #define PRID_IMP_INTERAPTIV_MP 0xa100 103 #define PRID_IMP_PROAPTIV_UP 0xa200 104 #define PRID_IMP_PROAPTIV_MP 0xa300 105 #define PRID_IMP_VIRTUOSO 0xa700 106 #define PRID_IMP_P5600 0xa800 107 #define PRID_IMP_SAMURAI_UP 0xa900 108 109 /* 110 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE 111 */ 112 113 #define PRID_IMP_SB1 0x0100 114 #define PRID_IMP_SB1A 0x1100 115 116 /* 117 * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT 118 */ 119 120 #define PRID_IMP_SR71000 0x0400 121 122 /* 123 * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM 124 */ 125 126 #define PRID_IMP_BMIPS32_REV4 0x4000 127 #define PRID_IMP_BMIPS32_REV8 0x8000 128 #define PRID_IMP_BMIPS3300 0x9000 129 #define PRID_IMP_BMIPS3300_ALT 0x9100 130 #define PRID_IMP_BMIPS3300_BUG 0x0000 131 #define PRID_IMP_BMIPS43XX 0xa000 132 #define PRID_IMP_BMIPS5000 0x5a00 133 134 #define PRID_REV_BMIPS4380_LO 0x0040 135 #define PRID_REV_BMIPS4380_HI 0x006f 136 137 /* 138 * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM 139 */ 140 141 #define PRID_IMP_CAVIUM_CN38XX 0x0000 142 #define PRID_IMP_CAVIUM_CN31XX 0x0100 143 #define PRID_IMP_CAVIUM_CN30XX 0x0200 144 #define PRID_IMP_CAVIUM_CN58XX 0x0300 145 #define PRID_IMP_CAVIUM_CN56XX 0x0400 146 #define PRID_IMP_CAVIUM_CN50XX 0x0600 147 #define PRID_IMP_CAVIUM_CN52XX 0x0700 148 #define PRID_IMP_CAVIUM_CN63XX 0x9000 149 #define PRID_IMP_CAVIUM_CN68XX 0x9100 150 #define PRID_IMP_CAVIUM_CN66XX 0x9200 151 #define PRID_IMP_CAVIUM_CN61XX 0x9300 152 153 /* 154 * These are the PRID's for when 23:16 == PRID_COMP_INGENIC 155 */ 156 157 #define PRID_IMP_JZRISC 0x0200 158 159 /* 160 * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC 161 */ 162 #define PRID_IMP_NETLOGIC_XLR732 0x0000 163 #define PRID_IMP_NETLOGIC_XLR716 0x0200 164 #define PRID_IMP_NETLOGIC_XLR532 0x0900 165 #define PRID_IMP_NETLOGIC_XLR308 0x0600 166 #define PRID_IMP_NETLOGIC_XLR532C 0x0800 167 #define PRID_IMP_NETLOGIC_XLR516C 0x0a00 168 #define PRID_IMP_NETLOGIC_XLR508C 0x0b00 169 #define PRID_IMP_NETLOGIC_XLR308C 0x0f00 170 #define PRID_IMP_NETLOGIC_XLS608 0x8000 171 #define PRID_IMP_NETLOGIC_XLS408 0x8800 172 #define PRID_IMP_NETLOGIC_XLS404 0x8c00 173 #define PRID_IMP_NETLOGIC_XLS208 0x8e00 174 #define PRID_IMP_NETLOGIC_XLS204 0x8f00 175 #define PRID_IMP_NETLOGIC_XLS108 0xce00 176 #define PRID_IMP_NETLOGIC_XLS104 0xcf00 177 #define PRID_IMP_NETLOGIC_XLS616B 0x4000 178 #define PRID_IMP_NETLOGIC_XLS608B 0x4a00 179 #define PRID_IMP_NETLOGIC_XLS416B 0x4400 180 #define PRID_IMP_NETLOGIC_XLS412B 0x4c00 181 #define PRID_IMP_NETLOGIC_XLS408B 0x4e00 182 #define PRID_IMP_NETLOGIC_XLS404B 0x4f00 183 #define PRID_IMP_NETLOGIC_AU13XX 0x8000 184 185 #define PRID_IMP_NETLOGIC_XLP8XX 0x1000 186 #define PRID_IMP_NETLOGIC_XLP3XX 0x1100 187 188 /* 189 * Definitions for 7:0 on legacy processors 190 */ 191 192 #define PRID_REV_MASK 0x00ff 193 194 #define PRID_REV_TX4927 0x0022 195 #define PRID_REV_TX4937 0x0030 196 #define PRID_REV_R4400 0x0040 197 #define PRID_REV_R3000A 0x0030 198 #define PRID_REV_R3000 0x0020 199 #define PRID_REV_R2000A 0x0010 200 #define PRID_REV_TX3912 0x0010 201 #define PRID_REV_TX3922 0x0030 202 #define PRID_REV_TX3927 0x0040 203 #define PRID_REV_VR4111 0x0050 204 #define PRID_REV_VR4181 0x0050 /* Same as VR4111 */ 205 #define PRID_REV_VR4121 0x0060 206 #define PRID_REV_VR4122 0x0070 207 #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ 208 #define PRID_REV_VR4130 0x0080 209 #define PRID_REV_34K_V1_0_2 0x0022 210 #define PRID_REV_LOONGSON1B 0x0020 211 #define PRID_REV_LOONGSON2E 0x0002 212 #define PRID_REV_LOONGSON2F 0x0003 213 214 /* 215 * Older processors used to encode processor version and revision in two 216 * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores 217 * have switched to use the 8-bits as 3:3:2 bitfield with the last field as 218 * the patch number. *ARGH* 219 */ 220 #define PRID_REV_ENCODE_44(ver, rev) \ 221 ((ver) << 4 | (rev)) 222 #define PRID_REV_ENCODE_332(ver, rev, patch) \ 223 ((ver) << 5 | (rev) << 2 | (patch)) 224 225 /* 226 * FPU implementation/revision register (CP1 control register 0). 227 * 228 * +---------------------------------+----------------+----------------+ 229 * | 0 | Implementation | Revision | 230 * +---------------------------------+----------------+----------------+ 231 * 31 16 15 8 7 0 232 */ 233 234 #define FPIR_IMP_NONE 0x0000 235 236 enum cpu_type_enum { 237 CPU_UNKNOWN, 238 239 /* 240 * R2000 class processors 241 */ 242 CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052, 243 CPU_R3081, CPU_R3081E, 244 245 /* 246 * R6000 class processors 247 */ 248 CPU_R6000, CPU_R6000A, 249 250 /* 251 * R4000 class processors 252 */ 253 CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310, 254 CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650, 255 CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000, 256 CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, CPU_VR4122, 257 CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000, 258 CPU_SR71000, CPU_RM9000, CPU_TX49XX, 259 260 /* 261 * R8000 class processors 262 */ 263 CPU_R8000, 264 265 /* 266 * TX3900 class processors 267 */ 268 CPU_TX3912, CPU_TX3922, CPU_TX3927, 269 270 /* 271 * MIPS32 class processors 272 */ 273 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, 274 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, 275 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC, 276 CPU_M14KEC, CPU_PROAPTIV, CPU_INTERAPTIV, CPU_VIRTUOSO, 277 CPU_P5600, 278 279 /* 280 * MIPS64 class processors 281 */ 282 CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, 283 CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, 284 CPU_XLR, CPU_XLP, CPU_SAMURAI, 285 286 CPU_QEMU, 287 CPU_LAST 288 }; 289 290 #define MIPS_FTLB_CAPABLE 0x1 291 292 /* 293 * ISA Level encodings 294 * 295 */ 296 #define MIPS_CPU_ISA_I 0x00000001 297 #define MIPS_CPU_ISA_II 0x00000002 298 #define MIPS_CPU_ISA_III 0x00000004 299 #define MIPS_CPU_ISA_IV 0x00000008 300 #define MIPS_CPU_ISA_V 0x00000010 301 #define MIPS_CPU_ISA_M32R1 0x00000020 302 #define MIPS_CPU_ISA_M32R2 0x00000040 303 #define MIPS_CPU_ISA_M64R1 0x00000080 304 #define MIPS_CPU_ISA_M64R2 0x00000100 305 #define MIPS_CPU_ISA_M32R6 0x00000200 306 #define MIPS_CPU_ISA_M64R6 0x00000400 307 308 #define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \ 309 MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |MIPS_CPU_ISA_M32R6) 310 #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ 311 MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2 | \ 312 MIPS_CPU_ISA_M64R6) 313 314 /* 315 * CPU Option encodings 316 */ 317 #define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */ 318 #define MIPS_CPU_4KEX 0x00000002 /* "R4K" exception model */ 319 #define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */ 320 #define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */ 321 #define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */ 322 #define MIPS_CPU_FPU 0x00000020 /* CPU has FPU */ 323 #define MIPS_CPU_32FPR 0x00000040 /* 32 dbl. prec. FP registers */ 324 #define MIPS_CPU_COUNTER 0x00000080 /* Cycle count/compare */ 325 #define MIPS_CPU_WATCH 0x00000100 /* watchpoint registers */ 326 #define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */ 327 #define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */ 328 #define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */ 329 #define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */ 330 #define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */ 331 #define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */ 332 #define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */ 333 #define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */ 334 #define MIPS_CPU_INCLUSIVE_CACHES 0x00020000 /* P-cache subset enforced */ 335 #define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */ 336 #define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */ 337 #define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */ 338 #define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ 339 #define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */ 340 #define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */ 341 #define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */ 342 #define MIPS_CPU_SEGMENTS 0x02000000 /* CPU supports memory segmentation */ 343 #define MIPS_CPU_EVA 0x04000000 /* CPU supports EVA functionality */ 344 #define MIPS_CPU_TLBINV 0x08000000 /* CPU supports TLBINV/F */ 345 #define MIPS_CPU_CM2 0x10000000 /* CPU has CM2 */ 346 #define MIPS_CPU_CM2_L2SYNC 0x20000000 /* CPU has CM2 L2-only SYNC feature */ 347 #define MIPS_CPU_TLBINV_FULL 0x40000000 /* CPU supports single TLBINV/F for full V/FTLB */ 348 #define MIPS_CPU_RIXI_EXCEPT 0x80000000 /* CPU has TLB Read/eXec Inhibit exceptions */ 349 350 /* 351 * CPU Option2 encodings 352 */ 353 #define MIPS_CPU_MAAR 0x00000001 /* MAAR exists */ 354 #define MIPS_CPU_HIMEM 0x00000002 /* MIPS32: PA bits exceed PTE space */ 355 #define MIPS_CPU_FRE 0x00000004 /* CPU has FRE support */ 356 #define MIPS_CPU_HTW 0x00000008 /* CPU support Hardware Page Table Walker */ 357 #define MIPS_CPU_L2C 0x00000010 /* CPU has _NO_ L2 description in Config2 */ 358 #define MIPS_CPU_VC 0x00000020 /* CPU has VC-MT support: GNR, CM3 virtual GIC etc */ 359 #define MIPS_CPU_CM3_INCLUSIVE_CACHES 0x00000040 /* L1D is included in L2 */ 360 361 /* 362 * CPU ASE encodings 363 */ 364 #define MIPS_ASE_MIPS16 0x00000001 /* code compression */ 365 #define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */ 366 #define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */ 367 #define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */ 368 #define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ 369 #define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */ 370 #define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */ 371 #define MIPS_ASE_VZ 0x00000080 /* Virtualization ASE */ 372 #define MIPS_ASE_MSA 0x00000100 /* MIPS SIMD Architecture */ 373 374 #endif /* _ASM_CPU_H */ 375