1 /*
2 * linux/drivers/video/omap2/dss/dispc.h
3 *
4 * Copyright (C) 2011 Texas Instruments
5 * Author: Archit Taneja <archit@ti.com>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #ifndef __OMAP2_DISPC_REG_H
22 #define __OMAP2_DISPC_REG_H
23
24 /* DISPC common registers */
25 #define DISPC_REVISION 0x0000
26 #define DISPC_SYSCONFIG 0x0010
27 #define DISPC_SYSSTATUS 0x0014
28 #define DISPC_IRQSTATUS 0x0018
29 #define DISPC_IRQENABLE 0x001C
30 #define DISPC_CONTROL 0x0040
31 #define DISPC_CONFIG 0x0044
32 #define DISPC_CAPABLE 0x0048
33 #define DISPC_LINE_STATUS 0x005C
34 #define DISPC_LINE_NUMBER 0x0060
35 #define DISPC_GLOBAL_ALPHA 0x0074
36 #define DISPC_CONTROL2 0x0238
37 #define DISPC_CONFIG2 0x0620
38 #define DISPC_DIVISOR 0x0804
39 #define DISPC_GLOBAL_BUFFER 0x0800
40 #define DISPC_CONTROL3 0x0848
41 #define DISPC_CONFIG3 0x084C
42 #define DISPC_MSTANDBY_CTRL 0x0858
43
44 /* DISPC overlay registers */
45 #define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \
46 DISPC_BA0_OFFSET(n))
47 #define DISPC_OVL_BA1(n) (DISPC_OVL_BASE(n) + \
48 DISPC_BA1_OFFSET(n))
49 #define DISPC_OVL_BA0_UV(n) (DISPC_OVL_BASE(n) + \
50 DISPC_BA0_UV_OFFSET(n))
51 #define DISPC_OVL_BA1_UV(n) (DISPC_OVL_BASE(n) + \
52 DISPC_BA1_UV_OFFSET(n))
53 #define DISPC_OVL_POSITION(n) (DISPC_OVL_BASE(n) + \
54 DISPC_POS_OFFSET(n))
55 #define DISPC_OVL_SIZE(n) (DISPC_OVL_BASE(n) + \
56 DISPC_SIZE_OFFSET(n))
57 #define DISPC_OVL_ATTRIBUTES(n) (DISPC_OVL_BASE(n) + \
58 DISPC_ATTR_OFFSET(n))
59 #define DISPC_OVL_ATTRIBUTES2(n) (DISPC_OVL_BASE(n) + \
60 DISPC_ATTR2_OFFSET(n))
61 #define DISPC_OVL_FIFO_THRESHOLD(n) (DISPC_OVL_BASE(n) + \
62 DISPC_FIFO_THRESH_OFFSET(n))
63 #define DISPC_OVL_FIFO_SIZE_STATUS(n) (DISPC_OVL_BASE(n) + \
64 DISPC_FIFO_SIZE_STATUS_OFFSET(n))
65 #define DISPC_OVL_ROW_INC(n) (DISPC_OVL_BASE(n) + \
66 DISPC_ROW_INC_OFFSET(n))
67 #define DISPC_OVL_PIXEL_INC(n) (DISPC_OVL_BASE(n) + \
68 DISPC_PIX_INC_OFFSET(n))
69 #define DISPC_OVL_WINDOW_SKIP(n) (DISPC_OVL_BASE(n) + \
70 DISPC_WINDOW_SKIP_OFFSET(n))
71 #define DISPC_OVL_TABLE_BA(n) (DISPC_OVL_BASE(n) + \
72 DISPC_TABLE_BA_OFFSET(n))
73 #define DISPC_OVL_FIR(n) (DISPC_OVL_BASE(n) + \
74 DISPC_FIR_OFFSET(n))
75 #define DISPC_OVL_FIR2(n) (DISPC_OVL_BASE(n) + \
76 DISPC_FIR2_OFFSET(n))
77 #define DISPC_OVL_PICTURE_SIZE(n) (DISPC_OVL_BASE(n) + \
78 DISPC_PIC_SIZE_OFFSET(n))
79 #define DISPC_OVL_ACCU0(n) (DISPC_OVL_BASE(n) + \
80 DISPC_ACCU0_OFFSET(n))
81 #define DISPC_OVL_ACCU1(n) (DISPC_OVL_BASE(n) + \
82 DISPC_ACCU1_OFFSET(n))
83 #define DISPC_OVL_ACCU2_0(n) (DISPC_OVL_BASE(n) + \
84 DISPC_ACCU2_0_OFFSET(n))
85 #define DISPC_OVL_ACCU2_1(n) (DISPC_OVL_BASE(n) + \
86 DISPC_ACCU2_1_OFFSET(n))
87 #define DISPC_OVL_FIR_COEF_H(n, i) (DISPC_OVL_BASE(n) + \
88 DISPC_FIR_COEF_H_OFFSET(n, i))
89 #define DISPC_OVL_FIR_COEF_HV(n, i) (DISPC_OVL_BASE(n) + \
90 DISPC_FIR_COEF_HV_OFFSET(n, i))
91 #define DISPC_OVL_FIR_COEF_H2(n, i) (DISPC_OVL_BASE(n) + \
92 DISPC_FIR_COEF_H2_OFFSET(n, i))
93 #define DISPC_OVL_FIR_COEF_HV2(n, i) (DISPC_OVL_BASE(n) + \
94 DISPC_FIR_COEF_HV2_OFFSET(n, i))
95 #define DISPC_OVL_CONV_COEF(n, i) (DISPC_OVL_BASE(n) + \
96 DISPC_CONV_COEF_OFFSET(n, i))
97 #define DISPC_OVL_FIR_COEF_V(n, i) (DISPC_OVL_BASE(n) + \
98 DISPC_FIR_COEF_V_OFFSET(n, i))
99 #define DISPC_OVL_FIR_COEF_V2(n, i) (DISPC_OVL_BASE(n) + \
100 DISPC_FIR_COEF_V2_OFFSET(n, i))
101 #define DISPC_OVL_PRELOAD(n) (DISPC_OVL_BASE(n) + \
102 DISPC_PRELOAD_OFFSET(n))
103
104 /* DISPC up/downsampling FIR filter coefficient structure */
105 struct dispc_coef {
106 s8 hc4_vc22;
107 s8 hc3_vc2;
108 u8 hc2_vc1;
109 s8 hc1_vc0;
110 s8 hc0_vc00;
111 };
112
113 const struct dispc_coef *dispc_ovl_get_scale_coef(int inc, int five_taps);
114
115 /* DISPC manager/channel specific registers */
DISPC_DEFAULT_COLOR(enum omap_channel channel)116 static inline u16 DISPC_DEFAULT_COLOR(enum omap_channel channel)
117 {
118 switch (channel) {
119 case OMAP_DSS_CHANNEL_LCD:
120 return 0x004C;
121 case OMAP_DSS_CHANNEL_DIGIT:
122 return 0x0050;
123 case OMAP_DSS_CHANNEL_LCD2:
124 return 0x03AC;
125 case OMAP_DSS_CHANNEL_LCD3:
126 return 0x0814;
127 default:
128 BUG();
129 return 0;
130 }
131 }
132
DISPC_TRANS_COLOR(enum omap_channel channel)133 static inline u16 DISPC_TRANS_COLOR(enum omap_channel channel)
134 {
135 switch (channel) {
136 case OMAP_DSS_CHANNEL_LCD:
137 return 0x0054;
138 case OMAP_DSS_CHANNEL_DIGIT:
139 return 0x0058;
140 case OMAP_DSS_CHANNEL_LCD2:
141 return 0x03B0;
142 case OMAP_DSS_CHANNEL_LCD3:
143 return 0x0818;
144 default:
145 BUG();
146 return 0;
147 }
148 }
149
DISPC_TIMING_H(enum omap_channel channel)150 static inline u16 DISPC_TIMING_H(enum omap_channel channel)
151 {
152 switch (channel) {
153 case OMAP_DSS_CHANNEL_LCD:
154 return 0x0064;
155 case OMAP_DSS_CHANNEL_DIGIT:
156 BUG();
157 return 0;
158 case OMAP_DSS_CHANNEL_LCD2:
159 return 0x0400;
160 case OMAP_DSS_CHANNEL_LCD3:
161 return 0x0840;
162 default:
163 BUG();
164 return 0;
165 }
166 }
167
DISPC_TIMING_V(enum omap_channel channel)168 static inline u16 DISPC_TIMING_V(enum omap_channel channel)
169 {
170 switch (channel) {
171 case OMAP_DSS_CHANNEL_LCD:
172 return 0x0068;
173 case OMAP_DSS_CHANNEL_DIGIT:
174 BUG();
175 return 0;
176 case OMAP_DSS_CHANNEL_LCD2:
177 return 0x0404;
178 case OMAP_DSS_CHANNEL_LCD3:
179 return 0x0844;
180 default:
181 BUG();
182 return 0;
183 }
184 }
185
DISPC_POL_FREQ(enum omap_channel channel)186 static inline u16 DISPC_POL_FREQ(enum omap_channel channel)
187 {
188 switch (channel) {
189 case OMAP_DSS_CHANNEL_LCD:
190 return 0x006C;
191 case OMAP_DSS_CHANNEL_DIGIT:
192 BUG();
193 return 0;
194 case OMAP_DSS_CHANNEL_LCD2:
195 return 0x0408;
196 case OMAP_DSS_CHANNEL_LCD3:
197 return 0x083C;
198 default:
199 BUG();
200 return 0;
201 }
202 }
203
DISPC_DIVISORo(enum omap_channel channel)204 static inline u16 DISPC_DIVISORo(enum omap_channel channel)
205 {
206 switch (channel) {
207 case OMAP_DSS_CHANNEL_LCD:
208 return 0x0070;
209 case OMAP_DSS_CHANNEL_DIGIT:
210 BUG();
211 return 0;
212 case OMAP_DSS_CHANNEL_LCD2:
213 return 0x040C;
214 case OMAP_DSS_CHANNEL_LCD3:
215 return 0x0838;
216 default:
217 BUG();
218 return 0;
219 }
220 }
221
222 /* Named as DISPC_SIZE_LCD, DISPC_SIZE_DIGIT and DISPC_SIZE_LCD2 in TRM */
DISPC_SIZE_MGR(enum omap_channel channel)223 static inline u16 DISPC_SIZE_MGR(enum omap_channel channel)
224 {
225 switch (channel) {
226 case OMAP_DSS_CHANNEL_LCD:
227 return 0x007C;
228 case OMAP_DSS_CHANNEL_DIGIT:
229 return 0x0078;
230 case OMAP_DSS_CHANNEL_LCD2:
231 return 0x03CC;
232 case OMAP_DSS_CHANNEL_LCD3:
233 return 0x0834;
234 default:
235 BUG();
236 return 0;
237 }
238 }
239
DISPC_DATA_CYCLE1(enum omap_channel channel)240 static inline u16 DISPC_DATA_CYCLE1(enum omap_channel channel)
241 {
242 switch (channel) {
243 case OMAP_DSS_CHANNEL_LCD:
244 return 0x01D4;
245 case OMAP_DSS_CHANNEL_DIGIT:
246 BUG();
247 return 0;
248 case OMAP_DSS_CHANNEL_LCD2:
249 return 0x03C0;
250 case OMAP_DSS_CHANNEL_LCD3:
251 return 0x0828;
252 default:
253 BUG();
254 return 0;
255 }
256 }
257
DISPC_DATA_CYCLE2(enum omap_channel channel)258 static inline u16 DISPC_DATA_CYCLE2(enum omap_channel channel)
259 {
260 switch (channel) {
261 case OMAP_DSS_CHANNEL_LCD:
262 return 0x01D8;
263 case OMAP_DSS_CHANNEL_DIGIT:
264 BUG();
265 return 0;
266 case OMAP_DSS_CHANNEL_LCD2:
267 return 0x03C4;
268 case OMAP_DSS_CHANNEL_LCD3:
269 return 0x082C;
270 default:
271 BUG();
272 return 0;
273 }
274 }
275
DISPC_DATA_CYCLE3(enum omap_channel channel)276 static inline u16 DISPC_DATA_CYCLE3(enum omap_channel channel)
277 {
278 switch (channel) {
279 case OMAP_DSS_CHANNEL_LCD:
280 return 0x01DC;
281 case OMAP_DSS_CHANNEL_DIGIT:
282 BUG();
283 return 0;
284 case OMAP_DSS_CHANNEL_LCD2:
285 return 0x03C8;
286 case OMAP_DSS_CHANNEL_LCD3:
287 return 0x0830;
288 default:
289 BUG();
290 return 0;
291 }
292 }
293
DISPC_CPR_COEF_R(enum omap_channel channel)294 static inline u16 DISPC_CPR_COEF_R(enum omap_channel channel)
295 {
296 switch (channel) {
297 case OMAP_DSS_CHANNEL_LCD:
298 return 0x0220;
299 case OMAP_DSS_CHANNEL_DIGIT:
300 BUG();
301 return 0;
302 case OMAP_DSS_CHANNEL_LCD2:
303 return 0x03BC;
304 case OMAP_DSS_CHANNEL_LCD3:
305 return 0x0824;
306 default:
307 BUG();
308 return 0;
309 }
310 }
311
DISPC_CPR_COEF_G(enum omap_channel channel)312 static inline u16 DISPC_CPR_COEF_G(enum omap_channel channel)
313 {
314 switch (channel) {
315 case OMAP_DSS_CHANNEL_LCD:
316 return 0x0224;
317 case OMAP_DSS_CHANNEL_DIGIT:
318 BUG();
319 return 0;
320 case OMAP_DSS_CHANNEL_LCD2:
321 return 0x03B8;
322 case OMAP_DSS_CHANNEL_LCD3:
323 return 0x0820;
324 default:
325 BUG();
326 return 0;
327 }
328 }
329
DISPC_CPR_COEF_B(enum omap_channel channel)330 static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel)
331 {
332 switch (channel) {
333 case OMAP_DSS_CHANNEL_LCD:
334 return 0x0228;
335 case OMAP_DSS_CHANNEL_DIGIT:
336 BUG();
337 return 0;
338 case OMAP_DSS_CHANNEL_LCD2:
339 return 0x03B4;
340 case OMAP_DSS_CHANNEL_LCD3:
341 return 0x081C;
342 default:
343 BUG();
344 return 0;
345 }
346 }
347
348 /* DISPC overlay register base addresses */
DISPC_OVL_BASE(enum omap_plane plane)349 static inline u16 DISPC_OVL_BASE(enum omap_plane plane)
350 {
351 switch (plane) {
352 case OMAP_DSS_GFX:
353 return 0x0080;
354 case OMAP_DSS_VIDEO1:
355 return 0x00BC;
356 case OMAP_DSS_VIDEO2:
357 return 0x014C;
358 case OMAP_DSS_VIDEO3:
359 return 0x0300;
360 case OMAP_DSS_WB:
361 return 0x0500;
362 default:
363 BUG();
364 return 0;
365 }
366 }
367
368 /* DISPC overlay register offsets */
DISPC_BA0_OFFSET(enum omap_plane plane)369 static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane)
370 {
371 switch (plane) {
372 case OMAP_DSS_GFX:
373 case OMAP_DSS_VIDEO1:
374 case OMAP_DSS_VIDEO2:
375 return 0x0000;
376 case OMAP_DSS_VIDEO3:
377 case OMAP_DSS_WB:
378 return 0x0008;
379 default:
380 BUG();
381 return 0;
382 }
383 }
384
DISPC_BA1_OFFSET(enum omap_plane plane)385 static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane)
386 {
387 switch (plane) {
388 case OMAP_DSS_GFX:
389 case OMAP_DSS_VIDEO1:
390 case OMAP_DSS_VIDEO2:
391 return 0x0004;
392 case OMAP_DSS_VIDEO3:
393 case OMAP_DSS_WB:
394 return 0x000C;
395 default:
396 BUG();
397 return 0;
398 }
399 }
400
DISPC_BA0_UV_OFFSET(enum omap_plane plane)401 static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane)
402 {
403 switch (plane) {
404 case OMAP_DSS_GFX:
405 BUG();
406 return 0;
407 case OMAP_DSS_VIDEO1:
408 return 0x0544;
409 case OMAP_DSS_VIDEO2:
410 return 0x04BC;
411 case OMAP_DSS_VIDEO3:
412 return 0x0310;
413 case OMAP_DSS_WB:
414 return 0x0118;
415 default:
416 BUG();
417 return 0;
418 }
419 }
420
DISPC_BA1_UV_OFFSET(enum omap_plane plane)421 static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane)
422 {
423 switch (plane) {
424 case OMAP_DSS_GFX:
425 BUG();
426 return 0;
427 case OMAP_DSS_VIDEO1:
428 return 0x0548;
429 case OMAP_DSS_VIDEO2:
430 return 0x04C0;
431 case OMAP_DSS_VIDEO3:
432 return 0x0314;
433 case OMAP_DSS_WB:
434 return 0x011C;
435 default:
436 BUG();
437 return 0;
438 }
439 }
440
DISPC_POS_OFFSET(enum omap_plane plane)441 static inline u16 DISPC_POS_OFFSET(enum omap_plane plane)
442 {
443 switch (plane) {
444 case OMAP_DSS_GFX:
445 case OMAP_DSS_VIDEO1:
446 case OMAP_DSS_VIDEO2:
447 return 0x0008;
448 case OMAP_DSS_VIDEO3:
449 return 0x009C;
450 default:
451 BUG();
452 return 0;
453 }
454 }
455
DISPC_SIZE_OFFSET(enum omap_plane plane)456 static inline u16 DISPC_SIZE_OFFSET(enum omap_plane plane)
457 {
458 switch (plane) {
459 case OMAP_DSS_GFX:
460 case OMAP_DSS_VIDEO1:
461 case OMAP_DSS_VIDEO2:
462 return 0x000C;
463 case OMAP_DSS_VIDEO3:
464 case OMAP_DSS_WB:
465 return 0x00A8;
466 default:
467 BUG();
468 return 0;
469 }
470 }
471
DISPC_ATTR_OFFSET(enum omap_plane plane)472 static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane)
473 {
474 switch (plane) {
475 case OMAP_DSS_GFX:
476 return 0x0020;
477 case OMAP_DSS_VIDEO1:
478 case OMAP_DSS_VIDEO2:
479 return 0x0010;
480 case OMAP_DSS_VIDEO3:
481 case OMAP_DSS_WB:
482 return 0x0070;
483 default:
484 BUG();
485 return 0;
486 }
487 }
488
DISPC_ATTR2_OFFSET(enum omap_plane plane)489 static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane plane)
490 {
491 switch (plane) {
492 case OMAP_DSS_GFX:
493 BUG();
494 return 0;
495 case OMAP_DSS_VIDEO1:
496 return 0x0568;
497 case OMAP_DSS_VIDEO2:
498 return 0x04DC;
499 case OMAP_DSS_VIDEO3:
500 return 0x032C;
501 case OMAP_DSS_WB:
502 return 0x0310;
503 default:
504 BUG();
505 return 0;
506 }
507 }
508
DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane)509 static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane)
510 {
511 switch (plane) {
512 case OMAP_DSS_GFX:
513 return 0x0024;
514 case OMAP_DSS_VIDEO1:
515 case OMAP_DSS_VIDEO2:
516 return 0x0014;
517 case OMAP_DSS_VIDEO3:
518 case OMAP_DSS_WB:
519 return 0x008C;
520 default:
521 BUG();
522 return 0;
523 }
524 }
525
DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane)526 static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane)
527 {
528 switch (plane) {
529 case OMAP_DSS_GFX:
530 return 0x0028;
531 case OMAP_DSS_VIDEO1:
532 case OMAP_DSS_VIDEO2:
533 return 0x0018;
534 case OMAP_DSS_VIDEO3:
535 case OMAP_DSS_WB:
536 return 0x0088;
537 default:
538 BUG();
539 return 0;
540 }
541 }
542
DISPC_ROW_INC_OFFSET(enum omap_plane plane)543 static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane plane)
544 {
545 switch (plane) {
546 case OMAP_DSS_GFX:
547 return 0x002C;
548 case OMAP_DSS_VIDEO1:
549 case OMAP_DSS_VIDEO2:
550 return 0x001C;
551 case OMAP_DSS_VIDEO3:
552 case OMAP_DSS_WB:
553 return 0x00A4;
554 default:
555 BUG();
556 return 0;
557 }
558 }
559
DISPC_PIX_INC_OFFSET(enum omap_plane plane)560 static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane plane)
561 {
562 switch (plane) {
563 case OMAP_DSS_GFX:
564 return 0x0030;
565 case OMAP_DSS_VIDEO1:
566 case OMAP_DSS_VIDEO2:
567 return 0x0020;
568 case OMAP_DSS_VIDEO3:
569 case OMAP_DSS_WB:
570 return 0x0098;
571 default:
572 BUG();
573 return 0;
574 }
575 }
576
DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane)577 static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane)
578 {
579 switch (plane) {
580 case OMAP_DSS_GFX:
581 return 0x0034;
582 case OMAP_DSS_VIDEO1:
583 case OMAP_DSS_VIDEO2:
584 case OMAP_DSS_VIDEO3:
585 BUG();
586 return 0;
587 default:
588 BUG();
589 return 0;
590 }
591 }
592
DISPC_TABLE_BA_OFFSET(enum omap_plane plane)593 static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane plane)
594 {
595 switch (plane) {
596 case OMAP_DSS_GFX:
597 return 0x0038;
598 case OMAP_DSS_VIDEO1:
599 case OMAP_DSS_VIDEO2:
600 case OMAP_DSS_VIDEO3:
601 BUG();
602 return 0;
603 default:
604 BUG();
605 return 0;
606 }
607 }
608
DISPC_FIR_OFFSET(enum omap_plane plane)609 static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane)
610 {
611 switch (plane) {
612 case OMAP_DSS_GFX:
613 BUG();
614 return 0;
615 case OMAP_DSS_VIDEO1:
616 case OMAP_DSS_VIDEO2:
617 return 0x0024;
618 case OMAP_DSS_VIDEO3:
619 case OMAP_DSS_WB:
620 return 0x0090;
621 default:
622 BUG();
623 return 0;
624 }
625 }
626
DISPC_FIR2_OFFSET(enum omap_plane plane)627 static inline u16 DISPC_FIR2_OFFSET(enum omap_plane plane)
628 {
629 switch (plane) {
630 case OMAP_DSS_GFX:
631 BUG();
632 return 0;
633 case OMAP_DSS_VIDEO1:
634 return 0x0580;
635 case OMAP_DSS_VIDEO2:
636 return 0x055C;
637 case OMAP_DSS_VIDEO3:
638 return 0x0424;
639 case OMAP_DSS_WB:
640 return 0x290;
641 default:
642 BUG();
643 return 0;
644 }
645 }
646
DISPC_PIC_SIZE_OFFSET(enum omap_plane plane)647 static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane)
648 {
649 switch (plane) {
650 case OMAP_DSS_GFX:
651 BUG();
652 return 0;
653 case OMAP_DSS_VIDEO1:
654 case OMAP_DSS_VIDEO2:
655 return 0x0028;
656 case OMAP_DSS_VIDEO3:
657 case OMAP_DSS_WB:
658 return 0x0094;
659 default:
660 BUG();
661 return 0;
662 }
663 }
664
665
DISPC_ACCU0_OFFSET(enum omap_plane plane)666 static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane)
667 {
668 switch (plane) {
669 case OMAP_DSS_GFX:
670 BUG();
671 return 0;
672 case OMAP_DSS_VIDEO1:
673 case OMAP_DSS_VIDEO2:
674 return 0x002C;
675 case OMAP_DSS_VIDEO3:
676 case OMAP_DSS_WB:
677 return 0x0000;
678 default:
679 BUG();
680 return 0;
681 }
682 }
683
DISPC_ACCU2_0_OFFSET(enum omap_plane plane)684 static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane plane)
685 {
686 switch (plane) {
687 case OMAP_DSS_GFX:
688 BUG();
689 return 0;
690 case OMAP_DSS_VIDEO1:
691 return 0x0584;
692 case OMAP_DSS_VIDEO2:
693 return 0x0560;
694 case OMAP_DSS_VIDEO3:
695 return 0x0428;
696 case OMAP_DSS_WB:
697 return 0x0294;
698 default:
699 BUG();
700 return 0;
701 }
702 }
703
DISPC_ACCU1_OFFSET(enum omap_plane plane)704 static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
705 {
706 switch (plane) {
707 case OMAP_DSS_GFX:
708 BUG();
709 return 0;
710 case OMAP_DSS_VIDEO1:
711 case OMAP_DSS_VIDEO2:
712 return 0x0030;
713 case OMAP_DSS_VIDEO3:
714 case OMAP_DSS_WB:
715 return 0x0004;
716 default:
717 BUG();
718 return 0;
719 }
720 }
721
DISPC_ACCU2_1_OFFSET(enum omap_plane plane)722 static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane plane)
723 {
724 switch (plane) {
725 case OMAP_DSS_GFX:
726 BUG();
727 return 0;
728 case OMAP_DSS_VIDEO1:
729 return 0x0588;
730 case OMAP_DSS_VIDEO2:
731 return 0x0564;
732 case OMAP_DSS_VIDEO3:
733 return 0x042C;
734 case OMAP_DSS_WB:
735 return 0x0298;
736 default:
737 BUG();
738 return 0;
739 }
740 }
741
742 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane,u16 i)743 static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
744 {
745 switch (plane) {
746 case OMAP_DSS_GFX:
747 BUG();
748 return 0;
749 case OMAP_DSS_VIDEO1:
750 case OMAP_DSS_VIDEO2:
751 return 0x0034 + i * 0x8;
752 case OMAP_DSS_VIDEO3:
753 case OMAP_DSS_WB:
754 return 0x0010 + i * 0x8;
755 default:
756 BUG();
757 return 0;
758 }
759 }
760
761 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane,u16 i)762 static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane, u16 i)
763 {
764 switch (plane) {
765 case OMAP_DSS_GFX:
766 BUG();
767 return 0;
768 case OMAP_DSS_VIDEO1:
769 return 0x058C + i * 0x8;
770 case OMAP_DSS_VIDEO2:
771 return 0x0568 + i * 0x8;
772 case OMAP_DSS_VIDEO3:
773 return 0x0430 + i * 0x8;
774 case OMAP_DSS_WB:
775 return 0x02A0 + i * 0x8;
776 default:
777 BUG();
778 return 0;
779 }
780 }
781
782 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane,u16 i)783 static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
784 {
785 switch (plane) {
786 case OMAP_DSS_GFX:
787 BUG();
788 return 0;
789 case OMAP_DSS_VIDEO1:
790 case OMAP_DSS_VIDEO2:
791 return 0x0038 + i * 0x8;
792 case OMAP_DSS_VIDEO3:
793 case OMAP_DSS_WB:
794 return 0x0014 + i * 0x8;
795 default:
796 BUG();
797 return 0;
798 }
799 }
800
801 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane,u16 i)802 static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane, u16 i)
803 {
804 switch (plane) {
805 case OMAP_DSS_GFX:
806 BUG();
807 return 0;
808 case OMAP_DSS_VIDEO1:
809 return 0x0590 + i * 8;
810 case OMAP_DSS_VIDEO2:
811 return 0x056C + i * 0x8;
812 case OMAP_DSS_VIDEO3:
813 return 0x0434 + i * 0x8;
814 case OMAP_DSS_WB:
815 return 0x02A4 + i * 0x8;
816 default:
817 BUG();
818 return 0;
819 }
820 }
821
822 /* coef index i = {0, 1, 2, 3, 4,} */
DISPC_CONV_COEF_OFFSET(enum omap_plane plane,u16 i)823 static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i)
824 {
825 switch (plane) {
826 case OMAP_DSS_GFX:
827 BUG();
828 return 0;
829 case OMAP_DSS_VIDEO1:
830 case OMAP_DSS_VIDEO2:
831 case OMAP_DSS_VIDEO3:
832 case OMAP_DSS_WB:
833 return 0x0074 + i * 0x4;
834 default:
835 BUG();
836 return 0;
837 }
838 }
839
840 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane,u16 i)841 static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i)
842 {
843 switch (plane) {
844 case OMAP_DSS_GFX:
845 BUG();
846 return 0;
847 case OMAP_DSS_VIDEO1:
848 return 0x0124 + i * 0x4;
849 case OMAP_DSS_VIDEO2:
850 return 0x00B4 + i * 0x4;
851 case OMAP_DSS_VIDEO3:
852 case OMAP_DSS_WB:
853 return 0x0050 + i * 0x4;
854 default:
855 BUG();
856 return 0;
857 }
858 }
859
860 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane,u16 i)861 static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane, u16 i)
862 {
863 switch (plane) {
864 case OMAP_DSS_GFX:
865 BUG();
866 return 0;
867 case OMAP_DSS_VIDEO1:
868 return 0x05CC + i * 0x4;
869 case OMAP_DSS_VIDEO2:
870 return 0x05A8 + i * 0x4;
871 case OMAP_DSS_VIDEO3:
872 return 0x0470 + i * 0x4;
873 case OMAP_DSS_WB:
874 return 0x02E0 + i * 0x4;
875 default:
876 BUG();
877 return 0;
878 }
879 }
880
DISPC_PRELOAD_OFFSET(enum omap_plane plane)881 static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane)
882 {
883 switch (plane) {
884 case OMAP_DSS_GFX:
885 return 0x01AC;
886 case OMAP_DSS_VIDEO1:
887 return 0x0174;
888 case OMAP_DSS_VIDEO2:
889 return 0x00E8;
890 case OMAP_DSS_VIDEO3:
891 return 0x00A0;
892 default:
893 BUG();
894 return 0;
895 }
896 }
897 #endif
898