1 /* drivers/video/msm_fb/mdp_hw.h 2 * 3 * Copyright (C) 2007 QUALCOMM Incorporated 4 * Copyright (C) 2007 Google Incorporated 5 * 6 * This software is licensed under the terms of the GNU General Public 7 * License version 2, as published by the Free Software Foundation, and 8 * may be copied, distributed, and modified under those terms. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 #ifndef _MDP_HW_H_ 16 #define _MDP_HW_H_ 17 18 #include <linux/platform_data/video-msm_fb.h> 19 20 struct mdp_info { 21 struct mdp_device mdp_dev; 22 char * __iomem base; 23 int irq; 24 }; 25 struct mdp_blit_req; 26 struct mdp_device; 27 int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req, 28 struct file *src_file, unsigned long src_start, 29 unsigned long src_len, struct file *dst_file, 30 unsigned long dst_start, unsigned long dst_len); 31 #define mdp_writel(mdp, value, offset) writel(value, mdp->base + offset) 32 #define mdp_readl(mdp, offset) readl(mdp->base + offset) 33 34 #define MDP_SYNC_CONFIG_0 (0x00000) 35 #define MDP_SYNC_CONFIG_1 (0x00004) 36 #define MDP_SYNC_CONFIG_2 (0x00008) 37 #define MDP_SYNC_STATUS_0 (0x0000c) 38 #define MDP_SYNC_STATUS_1 (0x00010) 39 #define MDP_SYNC_STATUS_2 (0x00014) 40 #define MDP_SYNC_THRESH_0 (0x00018) 41 #define MDP_SYNC_THRESH_1 (0x0001c) 42 #define MDP_INTR_ENABLE (0x00020) 43 #define MDP_INTR_STATUS (0x00024) 44 #define MDP_INTR_CLEAR (0x00028) 45 #define MDP_DISPLAY0_START (0x00030) 46 #define MDP_DISPLAY1_START (0x00034) 47 #define MDP_DISPLAY_STATUS (0x00038) 48 #define MDP_EBI2_LCD0 (0x0003c) 49 #define MDP_EBI2_LCD1 (0x00040) 50 #define MDP_DISPLAY0_ADDR (0x00054) 51 #define MDP_DISPLAY1_ADDR (0x00058) 52 #define MDP_EBI2_PORTMAP_MODE (0x0005c) 53 #define MDP_MODE (0x00060) 54 #define MDP_TV_OUT_STATUS (0x00064) 55 #define MDP_HW_VERSION (0x00070) 56 #define MDP_SW_RESET (0x00074) 57 #define MDP_AXI_ERROR_MASTER_STOP (0x00078) 58 #define MDP_SEL_CLK_OR_HCLK_TEST_BUS (0x0007c) 59 #define MDP_PRIMARY_VSYNC_OUT_CTRL (0x00080) 60 #define MDP_SECONDARY_VSYNC_OUT_CTRL (0x00084) 61 #define MDP_EXTERNAL_VSYNC_OUT_CTRL (0x00088) 62 #define MDP_VSYNC_CTRL (0x0008c) 63 #define MDP_CGC_EN (0x00100) 64 #define MDP_CMD_STATUS (0x10008) 65 #define MDP_PROFILE_EN (0x10010) 66 #define MDP_PROFILE_COUNT (0x10014) 67 #define MDP_DMA_START (0x10044) 68 #define MDP_FULL_BYPASS_WORD0 (0x10100) 69 #define MDP_FULL_BYPASS_WORD1 (0x10104) 70 #define MDP_COMMAND_CONFIG (0x10104) 71 #define MDP_FULL_BYPASS_WORD2 (0x10108) 72 #define MDP_FULL_BYPASS_WORD3 (0x1010c) 73 #define MDP_FULL_BYPASS_WORD4 (0x10110) 74 #define MDP_FULL_BYPASS_WORD6 (0x10118) 75 #define MDP_FULL_BYPASS_WORD7 (0x1011c) 76 #define MDP_FULL_BYPASS_WORD8 (0x10120) 77 #define MDP_FULL_BYPASS_WORD9 (0x10124) 78 #define MDP_PPP_SOURCE_CONFIG (0x10124) 79 #define MDP_FULL_BYPASS_WORD10 (0x10128) 80 #define MDP_FULL_BYPASS_WORD11 (0x1012c) 81 #define MDP_FULL_BYPASS_WORD12 (0x10130) 82 #define MDP_FULL_BYPASS_WORD13 (0x10134) 83 #define MDP_FULL_BYPASS_WORD14 (0x10138) 84 #define MDP_PPP_OPERATION_CONFIG (0x10138) 85 #define MDP_FULL_BYPASS_WORD15 (0x1013c) 86 #define MDP_FULL_BYPASS_WORD16 (0x10140) 87 #define MDP_FULL_BYPASS_WORD17 (0x10144) 88 #define MDP_FULL_BYPASS_WORD18 (0x10148) 89 #define MDP_FULL_BYPASS_WORD19 (0x1014c) 90 #define MDP_FULL_BYPASS_WORD20 (0x10150) 91 #define MDP_PPP_DESTINATION_CONFIG (0x10150) 92 #define MDP_FULL_BYPASS_WORD21 (0x10154) 93 #define MDP_FULL_BYPASS_WORD22 (0x10158) 94 #define MDP_FULL_BYPASS_WORD23 (0x1015c) 95 #define MDP_FULL_BYPASS_WORD24 (0x10160) 96 #define MDP_FULL_BYPASS_WORD25 (0x10164) 97 #define MDP_FULL_BYPASS_WORD26 (0x10168) 98 #define MDP_FULL_BYPASS_WORD27 (0x1016c) 99 #define MDP_FULL_BYPASS_WORD29 (0x10174) 100 #define MDP_FULL_BYPASS_WORD30 (0x10178) 101 #define MDP_FULL_BYPASS_WORD31 (0x1017c) 102 #define MDP_FULL_BYPASS_WORD32 (0x10180) 103 #define MDP_DMA_CONFIG (0x10180) 104 #define MDP_FULL_BYPASS_WORD33 (0x10184) 105 #define MDP_FULL_BYPASS_WORD34 (0x10188) 106 #define MDP_FULL_BYPASS_WORD35 (0x1018c) 107 #define MDP_FULL_BYPASS_WORD37 (0x10194) 108 #define MDP_FULL_BYPASS_WORD39 (0x1019c) 109 #define MDP_FULL_BYPASS_WORD40 (0x101a0) 110 #define MDP_FULL_BYPASS_WORD41 (0x101a4) 111 #define MDP_FULL_BYPASS_WORD43 (0x101ac) 112 #define MDP_FULL_BYPASS_WORD46 (0x101b8) 113 #define MDP_FULL_BYPASS_WORD47 (0x101bc) 114 #define MDP_FULL_BYPASS_WORD48 (0x101c0) 115 #define MDP_FULL_BYPASS_WORD49 (0x101c4) 116 #define MDP_FULL_BYPASS_WORD50 (0x101c8) 117 #define MDP_FULL_BYPASS_WORD51 (0x101cc) 118 #define MDP_FULL_BYPASS_WORD52 (0x101d0) 119 #define MDP_FULL_BYPASS_WORD53 (0x101d4) 120 #define MDP_FULL_BYPASS_WORD54 (0x101d8) 121 #define MDP_FULL_BYPASS_WORD55 (0x101dc) 122 #define MDP_FULL_BYPASS_WORD56 (0x101e0) 123 #define MDP_FULL_BYPASS_WORD57 (0x101e4) 124 #define MDP_FULL_BYPASS_WORD58 (0x101e8) 125 #define MDP_FULL_BYPASS_WORD59 (0x101ec) 126 #define MDP_FULL_BYPASS_WORD60 (0x101f0) 127 #define MDP_VSYNC_THRESHOLD (0x101f0) 128 #define MDP_FULL_BYPASS_WORD61 (0x101f4) 129 #define MDP_FULL_BYPASS_WORD62 (0x101f8) 130 #define MDP_FULL_BYPASS_WORD63 (0x101fc) 131 #define MDP_TFETCH_TEST_MODE (0x20004) 132 #define MDP_TFETCH_STATUS (0x20008) 133 #define MDP_TFETCH_TILE_COUNT (0x20010) 134 #define MDP_TFETCH_FETCH_COUNT (0x20014) 135 #define MDP_TFETCH_CONSTANT_COLOR (0x20040) 136 #define MDP_CSC_BYPASS (0x40004) 137 #define MDP_SCALE_COEFF_LSB (0x5fffc) 138 #define MDP_TV_OUT_CTL (0xc0000) 139 #define MDP_TV_OUT_FIR_COEFF (0xc0004) 140 #define MDP_TV_OUT_BUF_ADDR (0xc0008) 141 #define MDP_TV_OUT_CC_DATA (0xc000c) 142 #define MDP_TV_OUT_SOBEL (0xc0010) 143 #define MDP_TV_OUT_Y_CLAMP (0xc0018) 144 #define MDP_TV_OUT_CB_CLAMP (0xc001c) 145 #define MDP_TV_OUT_CR_CLAMP (0xc0020) 146 #define MDP_TEST_MODE_CLK (0xd0000) 147 #define MDP_TEST_MISR_RESET_CLK (0xd0004) 148 #define MDP_TEST_EXPORT_MISR_CLK (0xd0008) 149 #define MDP_TEST_MISR_CURR_VAL_CLK (0xd000c) 150 #define MDP_TEST_MODE_HCLK (0xd0100) 151 #define MDP_TEST_MISR_RESET_HCLK (0xd0104) 152 #define MDP_TEST_EXPORT_MISR_HCLK (0xd0108) 153 #define MDP_TEST_MISR_CURR_VAL_HCLK (0xd010c) 154 #define MDP_TEST_MODE_DCLK (0xd0200) 155 #define MDP_TEST_MISR_RESET_DCLK (0xd0204) 156 #define MDP_TEST_EXPORT_MISR_DCLK (0xd0208) 157 #define MDP_TEST_MISR_CURR_VAL_DCLK (0xd020c) 158 #define MDP_TEST_CAPTURED_DCLK (0xd0210) 159 #define MDP_TEST_MISR_CAPT_VAL_DCLK (0xd0214) 160 #define MDP_LCDC_CTL (0xe0000) 161 #define MDP_LCDC_HSYNC_CTL (0xe0004) 162 #define MDP_LCDC_VSYNC_CTL (0xe0008) 163 #define MDP_LCDC_ACTIVE_HCTL (0xe000c) 164 #define MDP_LCDC_ACTIVE_VCTL (0xe0010) 165 #define MDP_LCDC_BORDER_CLR (0xe0014) 166 #define MDP_LCDC_H_BLANK (0xe0018) 167 #define MDP_LCDC_V_BLANK (0xe001c) 168 #define MDP_LCDC_UNDERFLOW_CLR (0xe0020) 169 #define MDP_LCDC_HSYNC_SKEW (0xe0024) 170 #define MDP_LCDC_TEST_CTL (0xe0028) 171 #define MDP_LCDC_LINE_IRQ (0xe002c) 172 #define MDP_LCDC_CTL_POLARITY (0xe0030) 173 #define MDP_LCDC_DMA_CONFIG (0xe1000) 174 #define MDP_LCDC_DMA_SIZE (0xe1004) 175 #define MDP_LCDC_DMA_IBUF_ADDR (0xe1008) 176 #define MDP_LCDC_DMA_IBUF_Y_STRIDE (0xe100c) 177 178 179 #define MDP_DMA2_TERM 0x1 180 #define MDP_DMA3_TERM 0x2 181 #define MDP_PPP_TERM 0x3 182 183 /* MDP_INTR_ENABLE */ 184 #define DL0_ROI_DONE (1<<0) 185 #define DL1_ROI_DONE (1<<1) 186 #define DL0_DMA2_TERM_DONE (1<<2) 187 #define DL1_DMA2_TERM_DONE (1<<3) 188 #define DL0_PPP_TERM_DONE (1<<4) 189 #define DL1_PPP_TERM_DONE (1<<5) 190 #define TV_OUT_DMA3_DONE (1<<6) 191 #define TV_ENC_UNDERRUN (1<<7) 192 #define DL0_FETCH_DONE (1<<11) 193 #define DL1_FETCH_DONE (1<<12) 194 195 #define MDP_PPP_BUSY_STATUS (DL0_ROI_DONE| \ 196 DL1_ROI_DONE| \ 197 DL0_PPP_TERM_DONE| \ 198 DL1_PPP_TERM_DONE) 199 200 #define MDP_ANY_INTR_MASK (DL0_ROI_DONE| \ 201 DL1_ROI_DONE| \ 202 DL0_DMA2_TERM_DONE| \ 203 DL1_DMA2_TERM_DONE| \ 204 DL0_PPP_TERM_DONE| \ 205 DL1_PPP_TERM_DONE| \ 206 DL0_FETCH_DONE| \ 207 DL1_FETCH_DONE| \ 208 TV_ENC_UNDERRUN) 209 210 #define MDP_TOP_LUMA 16 211 #define MDP_TOP_CHROMA 0 212 #define MDP_BOTTOM_LUMA 19 213 #define MDP_BOTTOM_CHROMA 3 214 #define MDP_LEFT_LUMA 22 215 #define MDP_LEFT_CHROMA 6 216 #define MDP_RIGHT_LUMA 25 217 #define MDP_RIGHT_CHROMA 9 218 219 #define CLR_G 0x0 220 #define CLR_B 0x1 221 #define CLR_R 0x2 222 #define CLR_ALPHA 0x3 223 224 #define CLR_Y CLR_G 225 #define CLR_CB CLR_B 226 #define CLR_CR CLR_R 227 228 /* from lsb to msb */ 229 #define MDP_GET_PACK_PATTERN(a, x, y, z, bit) \ 230 (((a)<<(bit*3))|((x)<<(bit*2))|((y)<<bit)|(z)) 231 232 /* MDP_SYNC_CONFIG_0/1/2 */ 233 #define MDP_SYNCFG_HGT_LOC 22 234 #define MDP_SYNCFG_VSYNC_EXT_EN (1<<21) 235 #define MDP_SYNCFG_VSYNC_INT_EN (1<<20) 236 237 /* MDP_SYNC_THRESH_0 */ 238 #define MDP_PRIM_BELOW_LOC 0 239 #define MDP_PRIM_ABOVE_LOC 8 240 241 /* MDP_{PRIMARY,SECONDARY,EXTERNAL}_VSYNC_OUT_CRL */ 242 #define VSYNC_PULSE_EN (1<<31) 243 #define VSYNC_PULSE_INV (1<<30) 244 245 /* MDP_VSYNC_CTRL */ 246 #define DISP0_VSYNC_MAP_VSYNC0 0 247 #define DISP0_VSYNC_MAP_VSYNC1 (1<<0) 248 #define DISP0_VSYNC_MAP_VSYNC2 ((1<<0)|(1<<1)) 249 250 #define DISP1_VSYNC_MAP_VSYNC0 0 251 #define DISP1_VSYNC_MAP_VSYNC1 (1<<2) 252 #define DISP1_VSYNC_MAP_VSYNC2 ((1<<2)|(1<<3)) 253 254 #define PRIMARY_LCD_SYNC_EN (1<<4) 255 #define PRIMARY_LCD_SYNC_DISABLE 0 256 257 #define SECONDARY_LCD_SYNC_EN (1<<5) 258 #define SECONDARY_LCD_SYNC_DISABLE 0 259 260 #define EXTERNAL_LCD_SYNC_EN (1<<6) 261 #define EXTERNAL_LCD_SYNC_DISABLE 0 262 263 /* MDP_VSYNC_THRESHOLD / MDP_FULL_BYPASS_WORD60 */ 264 #define VSYNC_THRESHOLD_ABOVE_LOC 0 265 #define VSYNC_THRESHOLD_BELOW_LOC 16 266 #define VSYNC_ANTI_TEAR_EN (1<<31) 267 268 /* MDP_COMMAND_CONFIG / MDP_FULL_BYPASS_WORD1 */ 269 #define MDP_CMD_DBGBUS_EN (1<<0) 270 271 /* MDP_PPP_SOURCE_CONFIG / MDP_FULL_BYPASS_WORD9&53 */ 272 #define PPP_SRC_C0G_8BIT ((1<<1)|(1<<0)) 273 #define PPP_SRC_C1B_8BIT ((1<<3)|(1<<2)) 274 #define PPP_SRC_C2R_8BIT ((1<<5)|(1<<4)) 275 #define PPP_SRC_C3A_8BIT ((1<<7)|(1<<6)) 276 277 #define PPP_SRC_C0G_6BIT (1<<1) 278 #define PPP_SRC_C1B_6BIT (1<<3) 279 #define PPP_SRC_C2R_6BIT (1<<5) 280 281 #define PPP_SRC_C0G_5BIT (1<<0) 282 #define PPP_SRC_C1B_5BIT (1<<2) 283 #define PPP_SRC_C2R_5BIT (1<<4) 284 285 #define PPP_SRC_C3ALPHA_EN (1<<8) 286 287 #define PPP_SRC_BPP_1BYTES 0 288 #define PPP_SRC_BPP_2BYTES (1<<9) 289 #define PPP_SRC_BPP_3BYTES (1<<10) 290 #define PPP_SRC_BPP_4BYTES ((1<<10)|(1<<9)) 291 292 #define PPP_SRC_BPP_ROI_ODD_X (1<<11) 293 #define PPP_SRC_BPP_ROI_ODD_Y (1<<12) 294 #define PPP_SRC_INTERLVD_2COMPONENTS (1<<13) 295 #define PPP_SRC_INTERLVD_3COMPONENTS (1<<14) 296 #define PPP_SRC_INTERLVD_4COMPONENTS ((1<<14)|(1<<13)) 297 298 299 /* RGB666 unpack format 300 ** TIGHT means R6+G6+B6 together 301 ** LOOSE means R6+2 +G6+2+ B6+2 (with MSB) 302 ** or 2+R6 +2+G6 +2+B6 (with LSB) 303 */ 304 #define PPP_SRC_PACK_TIGHT (1<<17) 305 #define PPP_SRC_PACK_LOOSE 0 306 #define PPP_SRC_PACK_ALIGN_LSB 0 307 #define PPP_SRC_PACK_ALIGN_MSB (1<<18) 308 309 #define PPP_SRC_PLANE_INTERLVD 0 310 #define PPP_SRC_PLANE_PSEUDOPLNR (1<<20) 311 312 #define PPP_SRC_WMV9_MODE (1<<21) 313 314 /* MDP_PPP_OPERATION_CONFIG / MDP_FULL_BYPASS_WORD14 */ 315 #define PPP_OP_SCALE_X_ON (1<<0) 316 #define PPP_OP_SCALE_Y_ON (1<<1) 317 318 #define PPP_OP_CONVERT_RGB2YCBCR 0 319 #define PPP_OP_CONVERT_YCBCR2RGB (1<<2) 320 #define PPP_OP_CONVERT_ON (1<<3) 321 322 #define PPP_OP_CONVERT_MATRIX_PRIMARY 0 323 #define PPP_OP_CONVERT_MATRIX_SECONDARY (1<<4) 324 325 #define PPP_OP_LUT_C0_ON (1<<5) 326 #define PPP_OP_LUT_C1_ON (1<<6) 327 #define PPP_OP_LUT_C2_ON (1<<7) 328 329 /* rotate or blend enable */ 330 #define PPP_OP_ROT_ON (1<<8) 331 332 #define PPP_OP_ROT_90 (1<<9) 333 #define PPP_OP_FLIP_LR (1<<10) 334 #define PPP_OP_FLIP_UD (1<<11) 335 336 #define PPP_OP_BLEND_ON (1<<12) 337 338 #define PPP_OP_BLEND_SRCPIXEL_ALPHA 0 339 #define PPP_OP_BLEND_DSTPIXEL_ALPHA (1<<13) 340 #define PPP_OP_BLEND_CONSTANT_ALPHA (1<<14) 341 #define PPP_OP_BLEND_SRCPIXEL_TRANSP ((1<<13)|(1<<14)) 342 343 #define PPP_OP_BLEND_ALPHA_BLEND_NORMAL 0 344 #define PPP_OP_BLEND_ALPHA_BLEND_REVERSE (1<<15) 345 346 #define PPP_OP_DITHER_EN (1<<16) 347 348 #define PPP_OP_COLOR_SPACE_RGB 0 349 #define PPP_OP_COLOR_SPACE_YCBCR (1<<17) 350 351 #define PPP_OP_SRC_CHROMA_RGB 0 352 #define PPP_OP_SRC_CHROMA_H2V1 (1<<18) 353 #define PPP_OP_SRC_CHROMA_H1V2 (1<<19) 354 #define PPP_OP_SRC_CHROMA_420 ((1<<18)|(1<<19)) 355 #define PPP_OP_SRC_CHROMA_COSITE 0 356 #define PPP_OP_SRC_CHROMA_OFFSITE (1<<20) 357 358 #define PPP_OP_DST_CHROMA_RGB 0 359 #define PPP_OP_DST_CHROMA_H2V1 (1<<21) 360 #define PPP_OP_DST_CHROMA_H1V2 (1<<22) 361 #define PPP_OP_DST_CHROMA_420 ((1<<21)|(1<<22)) 362 #define PPP_OP_DST_CHROMA_COSITE 0 363 #define PPP_OP_DST_CHROMA_OFFSITE (1<<23) 364 365 #define PPP_BLEND_ALPHA_TRANSP (1<<24) 366 367 #define PPP_OP_BG_CHROMA_RGB 0 368 #define PPP_OP_BG_CHROMA_H2V1 (1<<25) 369 #define PPP_OP_BG_CHROMA_H1V2 (1<<26) 370 #define PPP_OP_BG_CHROMA_420 ((1<<25)|(1<<26)) 371 #define PPP_OP_BG_CHROMA_SITE_COSITE 0 372 #define PPP_OP_BG_CHROMA_SITE_OFFSITE (1<<27) 373 374 /* MDP_PPP_DESTINATION_CONFIG / MDP_FULL_BYPASS_WORD20 */ 375 #define PPP_DST_C0G_8BIT ((1<<0)|(1<<1)) 376 #define PPP_DST_C1B_8BIT ((1<<3)|(1<<2)) 377 #define PPP_DST_C2R_8BIT ((1<<5)|(1<<4)) 378 #define PPP_DST_C3A_8BIT ((1<<7)|(1<<6)) 379 380 #define PPP_DST_C0G_6BIT (1<<1) 381 #define PPP_DST_C1B_6BIT (1<<3) 382 #define PPP_DST_C2R_6BIT (1<<5) 383 384 #define PPP_DST_C0G_5BIT (1<<0) 385 #define PPP_DST_C1B_5BIT (1<<2) 386 #define PPP_DST_C2R_5BIT (1<<4) 387 388 #define PPP_DST_C3A_8BIT ((1<<7)|(1<<6)) 389 #define PPP_DST_C3ALPHA_EN (1<<8) 390 391 #define PPP_DST_INTERLVD_2COMPONENTS (1<<9) 392 #define PPP_DST_INTERLVD_3COMPONENTS (1<<10) 393 #define PPP_DST_INTERLVD_4COMPONENTS ((1<<10)|(1<<9)) 394 #define PPP_DST_INTERLVD_6COMPONENTS ((1<<11)|(1<<9)) 395 396 #define PPP_DST_PACK_LOOSE 0 397 #define PPP_DST_PACK_TIGHT (1<<13) 398 #define PPP_DST_PACK_ALIGN_LSB 0 399 #define PPP_DST_PACK_ALIGN_MSB (1<<14) 400 401 #define PPP_DST_OUT_SEL_AXI 0 402 #define PPP_DST_OUT_SEL_MDDI (1<<15) 403 404 #define PPP_DST_BPP_2BYTES (1<<16) 405 #define PPP_DST_BPP_3BYTES (1<<17) 406 #define PPP_DST_BPP_4BYTES ((1<<17)|(1<<16)) 407 408 #define PPP_DST_PLANE_INTERLVD 0 409 #define PPP_DST_PLANE_PLANAR (1<<18) 410 #define PPP_DST_PLANE_PSEUDOPLNR (1<<19) 411 412 #define PPP_DST_TO_TV (1<<20) 413 414 #define PPP_DST_MDDI_PRIMARY 0 415 #define PPP_DST_MDDI_SECONDARY (1<<21) 416 #define PPP_DST_MDDI_EXTERNAL (1<<22) 417 418 /* image configurations by image type */ 419 #define PPP_CFG_MDP_RGB_565(dir) (PPP_##dir##_C2R_5BIT | \ 420 PPP_##dir##_C0G_6BIT | \ 421 PPP_##dir##_C1B_5BIT | \ 422 PPP_##dir##_BPP_2BYTES | \ 423 PPP_##dir##_INTERLVD_3COMPONENTS | \ 424 PPP_##dir##_PACK_TIGHT | \ 425 PPP_##dir##_PACK_ALIGN_LSB | \ 426 PPP_##dir##_PLANE_INTERLVD) 427 428 #define PPP_CFG_MDP_RGB_888(dir) (PPP_##dir##_C2R_8BIT | \ 429 PPP_##dir##_C0G_8BIT | \ 430 PPP_##dir##_C1B_8BIT | \ 431 PPP_##dir##_BPP_3BYTES | \ 432 PPP_##dir##_INTERLVD_3COMPONENTS | \ 433 PPP_##dir##_PACK_TIGHT | \ 434 PPP_##dir##_PACK_ALIGN_LSB | \ 435 PPP_##dir##_PLANE_INTERLVD) 436 437 #define PPP_CFG_MDP_ARGB_8888(dir) (PPP_##dir##_C2R_8BIT | \ 438 PPP_##dir##_C0G_8BIT | \ 439 PPP_##dir##_C1B_8BIT | \ 440 PPP_##dir##_C3A_8BIT | \ 441 PPP_##dir##_C3ALPHA_EN | \ 442 PPP_##dir##_BPP_4BYTES | \ 443 PPP_##dir##_INTERLVD_4COMPONENTS | \ 444 PPP_##dir##_PACK_TIGHT | \ 445 PPP_##dir##_PACK_ALIGN_LSB | \ 446 PPP_##dir##_PLANE_INTERLVD) 447 448 #define PPP_CFG_MDP_XRGB_8888(dir) PPP_CFG_MDP_ARGB_8888(dir) 449 #define PPP_CFG_MDP_RGBA_8888(dir) PPP_CFG_MDP_ARGB_8888(dir) 450 #define PPP_CFG_MDP_BGRA_8888(dir) PPP_CFG_MDP_ARGB_8888(dir) 451 #define PPP_CFG_MDP_RGBX_8888(dir) PPP_CFG_MDP_ARGB_8888(dir) 452 453 #define PPP_CFG_MDP_Y_CBCR_H2V2(dir) (PPP_##dir##_C2R_8BIT | \ 454 PPP_##dir##_C0G_8BIT | \ 455 PPP_##dir##_C1B_8BIT | \ 456 PPP_##dir##_C3A_8BIT | \ 457 PPP_##dir##_BPP_2BYTES | \ 458 PPP_##dir##_INTERLVD_2COMPONENTS | \ 459 PPP_##dir##_PACK_TIGHT | \ 460 PPP_##dir##_PACK_ALIGN_LSB | \ 461 PPP_##dir##_PLANE_PSEUDOPLNR) 462 463 #define PPP_CFG_MDP_Y_CRCB_H2V2(dir) PPP_CFG_MDP_Y_CBCR_H2V2(dir) 464 465 #define PPP_CFG_MDP_YCRYCB_H2V1(dir) (PPP_##dir##_C2R_8BIT | \ 466 PPP_##dir##_C0G_8BIT | \ 467 PPP_##dir##_C1B_8BIT | \ 468 PPP_##dir##_C3A_8BIT | \ 469 PPP_##dir##_BPP_2BYTES | \ 470 PPP_##dir##_INTERLVD_4COMPONENTS | \ 471 PPP_##dir##_PACK_TIGHT | \ 472 PPP_##dir##_PACK_ALIGN_LSB |\ 473 PPP_##dir##_PLANE_INTERLVD) 474 475 #define PPP_CFG_MDP_Y_CBCR_H2V1(dir) (PPP_##dir##_C2R_8BIT | \ 476 PPP_##dir##_C0G_8BIT | \ 477 PPP_##dir##_C1B_8BIT | \ 478 PPP_##dir##_C3A_8BIT | \ 479 PPP_##dir##_BPP_2BYTES | \ 480 PPP_##dir##_INTERLVD_2COMPONENTS | \ 481 PPP_##dir##_PACK_TIGHT | \ 482 PPP_##dir##_PACK_ALIGN_LSB | \ 483 PPP_##dir##_PLANE_PSEUDOPLNR) 484 485 #define PPP_CFG_MDP_Y_CRCB_H2V1(dir) PPP_CFG_MDP_Y_CBCR_H2V1(dir) 486 487 #define PPP_PACK_PATTERN_MDP_RGB_565 \ 488 MDP_GET_PACK_PATTERN(0, CLR_R, CLR_G, CLR_B, 8) 489 #define PPP_PACK_PATTERN_MDP_RGB_888 PPP_PACK_PATTERN_MDP_RGB_565 490 #define PPP_PACK_PATTERN_MDP_XRGB_8888 \ 491 MDP_GET_PACK_PATTERN(CLR_B, CLR_G, CLR_R, CLR_ALPHA, 8) 492 #define PPP_PACK_PATTERN_MDP_ARGB_8888 PPP_PACK_PATTERN_MDP_XRGB_8888 493 #define PPP_PACK_PATTERN_MDP_RGBA_8888 \ 494 MDP_GET_PACK_PATTERN(CLR_ALPHA, CLR_B, CLR_G, CLR_R, 8) 495 #define PPP_PACK_PATTERN_MDP_BGRA_8888 \ 496 MDP_GET_PACK_PATTERN(CLR_ALPHA, CLR_R, CLR_G, CLR_B, 8) 497 #define PPP_PACK_PATTERN_MDP_RGBX_8888 \ 498 MDP_GET_PACK_PATTERN(CLR_ALPHA, CLR_B, CLR_G, CLR_R, 8) 499 #define PPP_PACK_PATTERN_MDP_Y_CBCR_H2V1 \ 500 MDP_GET_PACK_PATTERN(0, 0, CLR_CB, CLR_CR, 8) 501 #define PPP_PACK_PATTERN_MDP_Y_CBCR_H2V2 PPP_PACK_PATTERN_MDP_Y_CBCR_H2V1 502 #define PPP_PACK_PATTERN_MDP_Y_CRCB_H2V1 \ 503 MDP_GET_PACK_PATTERN(0, 0, CLR_CR, CLR_CB, 8) 504 #define PPP_PACK_PATTERN_MDP_Y_CRCB_H2V2 PPP_PACK_PATTERN_MDP_Y_CRCB_H2V1 505 #define PPP_PACK_PATTERN_MDP_YCRYCB_H2V1 \ 506 MDP_GET_PACK_PATTERN(CLR_Y, CLR_R, CLR_Y, CLR_B, 8) 507 508 #define PPP_CHROMA_SAMP_MDP_RGB_565(dir) PPP_OP_##dir##_CHROMA_RGB 509 #define PPP_CHROMA_SAMP_MDP_RGB_888(dir) PPP_OP_##dir##_CHROMA_RGB 510 #define PPP_CHROMA_SAMP_MDP_XRGB_8888(dir) PPP_OP_##dir##_CHROMA_RGB 511 #define PPP_CHROMA_SAMP_MDP_ARGB_8888(dir) PPP_OP_##dir##_CHROMA_RGB 512 #define PPP_CHROMA_SAMP_MDP_RGBA_8888(dir) PPP_OP_##dir##_CHROMA_RGB 513 #define PPP_CHROMA_SAMP_MDP_BGRA_8888(dir) PPP_OP_##dir##_CHROMA_RGB 514 #define PPP_CHROMA_SAMP_MDP_RGBX_8888(dir) PPP_OP_##dir##_CHROMA_RGB 515 #define PPP_CHROMA_SAMP_MDP_Y_CBCR_H2V1(dir) PPP_OP_##dir##_CHROMA_H2V1 516 #define PPP_CHROMA_SAMP_MDP_Y_CBCR_H2V2(dir) PPP_OP_##dir##_CHROMA_420 517 #define PPP_CHROMA_SAMP_MDP_Y_CRCB_H2V1(dir) PPP_OP_##dir##_CHROMA_H2V1 518 #define PPP_CHROMA_SAMP_MDP_Y_CRCB_H2V2(dir) PPP_OP_##dir##_CHROMA_420 519 #define PPP_CHROMA_SAMP_MDP_YCRYCB_H2V1(dir) PPP_OP_##dir##_CHROMA_H2V1 520 521 /* Helpful array generation macros */ 522 #define PPP_ARRAY0(name) \ 523 [MDP_RGB_565] = PPP_##name##_MDP_RGB_565,\ 524 [MDP_RGB_888] = PPP_##name##_MDP_RGB_888,\ 525 [MDP_XRGB_8888] = PPP_##name##_MDP_XRGB_8888,\ 526 [MDP_ARGB_8888] = PPP_##name##_MDP_ARGB_8888,\ 527 [MDP_RGBA_8888] = PPP_##name##_MDP_RGBA_8888,\ 528 [MDP_BGRA_8888] = PPP_##name##_MDP_BGRA_8888,\ 529 [MDP_RGBX_8888] = PPP_##name##_MDP_RGBX_8888,\ 530 [MDP_Y_CBCR_H2V1] = PPP_##name##_MDP_Y_CBCR_H2V1,\ 531 [MDP_Y_CBCR_H2V2] = PPP_##name##_MDP_Y_CBCR_H2V2,\ 532 [MDP_Y_CRCB_H2V1] = PPP_##name##_MDP_Y_CRCB_H2V1,\ 533 [MDP_Y_CRCB_H2V2] = PPP_##name##_MDP_Y_CRCB_H2V2,\ 534 [MDP_YCRYCB_H2V1] = PPP_##name##_MDP_YCRYCB_H2V1 535 536 #define PPP_ARRAY1(name, dir) \ 537 [MDP_RGB_565] = PPP_##name##_MDP_RGB_565(dir),\ 538 [MDP_RGB_888] = PPP_##name##_MDP_RGB_888(dir),\ 539 [MDP_XRGB_8888] = PPP_##name##_MDP_XRGB_8888(dir),\ 540 [MDP_ARGB_8888] = PPP_##name##_MDP_ARGB_8888(dir),\ 541 [MDP_RGBA_8888] = PPP_##name##_MDP_RGBA_8888(dir),\ 542 [MDP_BGRA_8888] = PPP_##name##_MDP_BGRA_8888(dir),\ 543 [MDP_RGBX_8888] = PPP_##name##_MDP_RGBX_8888(dir),\ 544 [MDP_Y_CBCR_H2V1] = PPP_##name##_MDP_Y_CBCR_H2V1(dir),\ 545 [MDP_Y_CBCR_H2V2] = PPP_##name##_MDP_Y_CBCR_H2V2(dir),\ 546 [MDP_Y_CRCB_H2V1] = PPP_##name##_MDP_Y_CRCB_H2V1(dir),\ 547 [MDP_Y_CRCB_H2V2] = PPP_##name##_MDP_Y_CRCB_H2V2(dir),\ 548 [MDP_YCRYCB_H2V1] = PPP_##name##_MDP_YCRYCB_H2V1(dir) 549 550 #define IS_YCRCB(img) ((img == MDP_Y_CRCB_H2V2) | (img == MDP_Y_CBCR_H2V2) | \ 551 (img == MDP_Y_CRCB_H2V1) | (img == MDP_Y_CBCR_H2V1) | \ 552 (img == MDP_YCRYCB_H2V1)) 553 #define IS_RGB(img) ((img == MDP_RGB_565) | (img == MDP_RGB_888) | \ 554 (img == MDP_ARGB_8888) | (img == MDP_RGBA_8888) | \ 555 (img == MDP_XRGB_8888) | (img == MDP_BGRA_8888) | \ 556 (img == MDP_RGBX_8888)) 557 #define HAS_ALPHA(img) ((img == MDP_ARGB_8888) | (img == MDP_RGBA_8888) | \ 558 (img == MDP_BGRA_8888)) 559 560 #define IS_PSEUDOPLNR(img) ((img == MDP_Y_CRCB_H2V2) | \ 561 (img == MDP_Y_CBCR_H2V2) | \ 562 (img == MDP_Y_CRCB_H2V1) | \ 563 (img == MDP_Y_CBCR_H2V1)) 564 565 /* Mappings from addr to purpose */ 566 #define PPP_ADDR_SRC_ROI MDP_FULL_BYPASS_WORD2 567 #define PPP_ADDR_SRC0 MDP_FULL_BYPASS_WORD3 568 #define PPP_ADDR_SRC1 MDP_FULL_BYPASS_WORD4 569 #define PPP_ADDR_SRC_YSTRIDE MDP_FULL_BYPASS_WORD7 570 #define PPP_ADDR_SRC_CFG MDP_FULL_BYPASS_WORD9 571 #define PPP_ADDR_SRC_PACK_PATTERN MDP_FULL_BYPASS_WORD10 572 #define PPP_ADDR_OPERATION MDP_FULL_BYPASS_WORD14 573 #define PPP_ADDR_PHASEX_INIT MDP_FULL_BYPASS_WORD15 574 #define PPP_ADDR_PHASEY_INIT MDP_FULL_BYPASS_WORD16 575 #define PPP_ADDR_PHASEX_STEP MDP_FULL_BYPASS_WORD17 576 #define PPP_ADDR_PHASEY_STEP MDP_FULL_BYPASS_WORD18 577 #define PPP_ADDR_ALPHA_TRANSP MDP_FULL_BYPASS_WORD19 578 #define PPP_ADDR_DST_CFG MDP_FULL_BYPASS_WORD20 579 #define PPP_ADDR_DST_PACK_PATTERN MDP_FULL_BYPASS_WORD21 580 #define PPP_ADDR_DST_ROI MDP_FULL_BYPASS_WORD25 581 #define PPP_ADDR_DST0 MDP_FULL_BYPASS_WORD26 582 #define PPP_ADDR_DST1 MDP_FULL_BYPASS_WORD27 583 #define PPP_ADDR_DST_YSTRIDE MDP_FULL_BYPASS_WORD30 584 #define PPP_ADDR_EDGE MDP_FULL_BYPASS_WORD46 585 #define PPP_ADDR_BG0 MDP_FULL_BYPASS_WORD48 586 #define PPP_ADDR_BG1 MDP_FULL_BYPASS_WORD49 587 #define PPP_ADDR_BG_YSTRIDE MDP_FULL_BYPASS_WORD51 588 #define PPP_ADDR_BG_CFG MDP_FULL_BYPASS_WORD53 589 #define PPP_ADDR_BG_PACK_PATTERN MDP_FULL_BYPASS_WORD54 590 591 /* MDP_DMA_CONFIG / MDP_FULL_BYPASS_WORD32 */ 592 #define DMA_DSTC0G_6BITS (1<<1) 593 #define DMA_DSTC1B_6BITS (1<<3) 594 #define DMA_DSTC2R_6BITS (1<<5) 595 #define DMA_DSTC0G_5BITS (1<<0) 596 #define DMA_DSTC1B_5BITS (1<<2) 597 #define DMA_DSTC2R_5BITS (1<<4) 598 599 #define DMA_PACK_TIGHT (1<<6) 600 #define DMA_PACK_LOOSE 0 601 #define DMA_PACK_ALIGN_LSB 0 602 #define DMA_PACK_ALIGN_MSB (1<<7) 603 #define DMA_PACK_PATTERN_RGB \ 604 (MDP_GET_PACK_PATTERN(0, CLR_R, CLR_G, CLR_B, 2)<<8) 605 606 #define DMA_OUT_SEL_AHB 0 607 #define DMA_OUT_SEL_MDDI (1<<14) 608 #define DMA_AHBM_LCD_SEL_PRIMARY 0 609 #define DMA_AHBM_LCD_SEL_SECONDARY (1<<15) 610 #define DMA_IBUF_C3ALPHA_EN (1<<16) 611 #define DMA_DITHER_EN (1<<17) 612 613 #define DMA_MDDI_DMAOUT_LCD_SEL_PRIMARY 0 614 #define DMA_MDDI_DMAOUT_LCD_SEL_SECONDARY (1<<18) 615 #define DMA_MDDI_DMAOUT_LCD_SEL_EXTERNAL (1<<19) 616 617 #define DMA_IBUF_FORMAT_RGB565 (1<<20) 618 #define DMA_IBUF_FORMAT_RGB888_OR_ARGB8888 0 619 620 #define DMA_IBUF_NONCONTIGUOUS (1<<21) 621 622 /* MDDI REGISTER ? */ 623 #define MDDI_VDO_PACKET_DESC 0x5666 624 #define MDDI_VDO_PACKET_PRIM 0xC3 625 #define MDDI_VDO_PACKET_SECD 0xC0 626 627 #endif 628