1 /**
2 * core.h - DesignWare USB3 DRD Core Header
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 #ifndef __DRIVERS_USB_DWC3_CORE_H
40 #define __DRIVERS_USB_DWC3_CORE_H
41
42 #include <linux/device.h>
43 #include <linux/spinlock.h>
44 #include <linux/ioport.h>
45 #include <linux/list.h>
46 #include <linux/dma-mapping.h>
47 #include <linux/mm.h>
48 #include <linux/debugfs.h>
49
50 #include <linux/usb/ch9.h>
51 #include <linux/usb/gadget.h>
52
53 /* Global constants */
54 #define DWC3_EP0_BOUNCE_SIZE 512
55 #define DWC3_ENDPOINTS_NUM 32
56 #define DWC3_XHCI_RESOURCES_NUM 2
57
58 #define DWC3_EVENT_SIZE 4 /* bytes */
59 #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */
60 #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM)
61 #define DWC3_EVENT_TYPE_MASK 0xfe
62
63 #define DWC3_EVENT_TYPE_DEV 0
64 #define DWC3_EVENT_TYPE_CARKIT 3
65 #define DWC3_EVENT_TYPE_I2C 4
66
67 #define DWC3_DEVICE_EVENT_DISCONNECT 0
68 #define DWC3_DEVICE_EVENT_RESET 1
69 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2
70 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
71 #define DWC3_DEVICE_EVENT_WAKEUP 4
72 #define DWC3_DEVICE_EVENT_HIBER_REQ 5
73 #define DWC3_DEVICE_EVENT_EOPF 6
74 #define DWC3_DEVICE_EVENT_SOF 7
75 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
76 #define DWC3_DEVICE_EVENT_CMD_CMPL 10
77 #define DWC3_DEVICE_EVENT_OVERFLOW 11
78
79 #define DWC3_GEVNTCOUNT_MASK 0xfffc
80 #define DWC3_GSNPSID_MASK 0xffff0000
81 #define DWC3_GSNPSREV_MASK 0xffff
82
83 /* DWC3 registers memory space boundries */
84 #define DWC3_XHCI_REGS_START 0x0
85 #define DWC3_XHCI_REGS_END 0x7fff
86 #define DWC3_GLOBALS_REGS_START 0xc100
87 #define DWC3_GLOBALS_REGS_END 0xc6ff
88 #define DWC3_DEVICE_REGS_START 0xc700
89 #define DWC3_DEVICE_REGS_END 0xcbff
90 #define DWC3_OTG_REGS_START 0xcc00
91 #define DWC3_OTG_REGS_END 0xccff
92
93 /* Global Registers */
94 #define DWC3_GSBUSCFG0 0xc100
95 #define DWC3_GSBUSCFG1 0xc104
96 #define DWC3_GTXTHRCFG 0xc108
97 #define DWC3_GRXTHRCFG 0xc10c
98 #define DWC3_GCTL 0xc110
99 #define DWC3_GEVTEN 0xc114
100 #define DWC3_GSTS 0xc118
101 #define DWC3_GSNPSID 0xc120
102 #define DWC3_GGPIO 0xc124
103 #define DWC3_GUID 0xc128
104 #define DWC3_GUCTL 0xc12c
105 #define DWC3_GBUSERRADDR0 0xc130
106 #define DWC3_GBUSERRADDR1 0xc134
107 #define DWC3_GPRTBIMAP0 0xc138
108 #define DWC3_GPRTBIMAP1 0xc13c
109 #define DWC3_GHWPARAMS0 0xc140
110 #define DWC3_GHWPARAMS1 0xc144
111 #define DWC3_GHWPARAMS2 0xc148
112 #define DWC3_GHWPARAMS3 0xc14c
113 #define DWC3_GHWPARAMS4 0xc150
114 #define DWC3_GHWPARAMS5 0xc154
115 #define DWC3_GHWPARAMS6 0xc158
116 #define DWC3_GHWPARAMS7 0xc15c
117 #define DWC3_GDBGFIFOSPACE 0xc160
118 #define DWC3_GDBGLTSSM 0xc164
119 #define DWC3_GPRTBIMAP_HS0 0xc180
120 #define DWC3_GPRTBIMAP_HS1 0xc184
121 #define DWC3_GPRTBIMAP_FS0 0xc188
122 #define DWC3_GPRTBIMAP_FS1 0xc18c
123
124 #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
125 #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
126
127 #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04))
128
129 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
130
131 #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
132 #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
133
134 #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10))
135 #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10))
136 #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10))
137 #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
138
139 #define DWC3_GHWPARAMS8 0xc600
140
141 /* Device Registers */
142 #define DWC3_DCFG 0xc700
143 #define DWC3_DCTL 0xc704
144 #define DWC3_DEVTEN 0xc708
145 #define DWC3_DSTS 0xc70c
146 #define DWC3_DGCMDPAR 0xc710
147 #define DWC3_DGCMD 0xc714
148 #define DWC3_DALEPENA 0xc720
149 #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10))
150 #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10))
151 #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10))
152 #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10))
153
154 /* OTG Registers */
155 #define DWC3_OCFG 0xcc00
156 #define DWC3_OCTL 0xcc04
157 #define DWC3_OEVT 0xcc08
158 #define DWC3_OEVTEN 0xcc0C
159 #define DWC3_OSTS 0xcc10
160
161 /* Bit fields */
162
163 /* Global Configuration Register */
164 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
165 #define DWC3_GCTL_U2RSTECN (1 << 16)
166 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
167 #define DWC3_GCTL_CLK_BUS (0)
168 #define DWC3_GCTL_CLK_PIPE (1)
169 #define DWC3_GCTL_CLK_PIPEHALF (2)
170 #define DWC3_GCTL_CLK_MASK (3)
171
172 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
173 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
174 #define DWC3_GCTL_PRTCAP_HOST 1
175 #define DWC3_GCTL_PRTCAP_DEVICE 2
176 #define DWC3_GCTL_PRTCAP_OTG 3
177
178 #define DWC3_GCTL_CORESOFTRESET (1 << 11)
179 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
180 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
181 #define DWC3_GCTL_DISSCRAMBLE (1 << 3)
182 #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)
183 #define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
184
185 /* Global USB2 PHY Configuration Register */
186 #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
187 #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
188
189 /* Global USB3 PIPE Control Register */
190 #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
191 #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
192
193 /* Global TX Fifo Size Register */
194 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
195 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
196
197 /* Global HWPARAMS1 Register */
198 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
199 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
200 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
201 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
202 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
203 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
204
205 /* Global HWPARAMS4 Register */
206 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
207 #define DWC3_MAX_HIBER_SCRATCHBUFS 15
208
209 /* Device Configuration Register */
210 #define DWC3_DCFG_LPM_CAP (1 << 22)
211 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
212 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
213
214 #define DWC3_DCFG_SPEED_MASK (7 << 0)
215 #define DWC3_DCFG_SUPERSPEED (4 << 0)
216 #define DWC3_DCFG_HIGHSPEED (0 << 0)
217 #define DWC3_DCFG_FULLSPEED2 (1 << 0)
218 #define DWC3_DCFG_LOWSPEED (2 << 0)
219 #define DWC3_DCFG_FULLSPEED1 (3 << 0)
220
221 #define DWC3_DCFG_LPM_CAP (1 << 22)
222
223 /* Device Control Register */
224 #define DWC3_DCTL_RUN_STOP (1 << 31)
225 #define DWC3_DCTL_CSFTRST (1 << 30)
226 #define DWC3_DCTL_LSFTRST (1 << 29)
227
228 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
229 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
230
231 #define DWC3_DCTL_APPL1RES (1 << 23)
232
233 /* These apply for core versions 1.87a and earlier */
234 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
235 #define DWC3_DCTL_TRGTULST(n) ((n) << 17)
236 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
237 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
238 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
239 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
240 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
241
242 /* These apply for core versions 1.94a and later */
243 #define DWC3_DCTL_KEEP_CONNECT (1 << 19)
244 #define DWC3_DCTL_L1_HIBER_EN (1 << 18)
245 #define DWC3_DCTL_CRS (1 << 17)
246 #define DWC3_DCTL_CSS (1 << 16)
247
248 #define DWC3_DCTL_INITU2ENA (1 << 12)
249 #define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
250 #define DWC3_DCTL_INITU1ENA (1 << 10)
251 #define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
252 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
253
254 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
255 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
256
257 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
258 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
259 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
260 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
261 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
262 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
263 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
264
265 /* Device Event Enable Register */
266 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)
267 #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11)
268 #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10)
269 #define DWC3_DEVTEN_ERRTICERREN (1 << 9)
270 #define DWC3_DEVTEN_SOFEN (1 << 7)
271 #define DWC3_DEVTEN_EOPFEN (1 << 6)
272 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5)
273 #define DWC3_DEVTEN_WKUPEVTEN (1 << 4)
274 #define DWC3_DEVTEN_ULSTCNGEN (1 << 3)
275 #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2)
276 #define DWC3_DEVTEN_USBRSTEN (1 << 1)
277 #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)
278
279 /* Device Status Register */
280 #define DWC3_DSTS_DCNRD (1 << 29)
281
282 /* This applies for core versions 1.87a and earlier */
283 #define DWC3_DSTS_PWRUPREQ (1 << 24)
284
285 /* These apply for core versions 1.94a and later */
286 #define DWC3_DSTS_RSS (1 << 25)
287 #define DWC3_DSTS_SSS (1 << 24)
288
289 #define DWC3_DSTS_COREIDLE (1 << 23)
290 #define DWC3_DSTS_DEVCTRLHLT (1 << 22)
291
292 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
293 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
294
295 #define DWC3_DSTS_RXFIFOEMPTY (1 << 17)
296
297 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
298 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
299
300 #define DWC3_DSTS_CONNECTSPD (7 << 0)
301
302 #define DWC3_DSTS_SUPERSPEED (4 << 0)
303 #define DWC3_DSTS_HIGHSPEED (0 << 0)
304 #define DWC3_DSTS_FULLSPEED2 (1 << 0)
305 #define DWC3_DSTS_LOWSPEED (2 << 0)
306 #define DWC3_DSTS_FULLSPEED1 (3 << 0)
307
308 /* Device Generic Command Register */
309 #define DWC3_DGCMD_SET_LMP 0x01
310 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
311 #define DWC3_DGCMD_XMIT_FUNCTION 0x03
312
313 /* These apply for core versions 1.94a and later */
314 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
315 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
316
317 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
318 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
319 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
320 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
321
322 #define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1)
323 #define DWC3_DGCMD_CMDACT (1 << 10)
324 #define DWC3_DGCMD_CMDIOC (1 << 8)
325
326 /* Device Generic Command Parameter Register */
327 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0)
328 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
329 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
330 #define DWC3_DGCMDPAR_TX_FIFO (1 << 5)
331 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
332 #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0)
333
334 /* Device Endpoint Command Register */
335 #define DWC3_DEPCMD_PARAM_SHIFT 16
336 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
337 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
338 #define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1)
339 #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11)
340 #define DWC3_DEPCMD_CMDACT (1 << 10)
341 #define DWC3_DEPCMD_CMDIOC (1 << 8)
342
343 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
344 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
345 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
346 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
347 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
348 #define DWC3_DEPCMD_SETSTALL (0x04 << 0)
349 /* This applies for core versions 1.90a and earlier */
350 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
351 /* This applies for core versions 1.94a and later */
352 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
353 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
354 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
355
356 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
357 #define DWC3_DALEPENA_EP(n) (1 << n)
358
359 #define DWC3_DEPCMD_TYPE_CONTROL 0
360 #define DWC3_DEPCMD_TYPE_ISOC 1
361 #define DWC3_DEPCMD_TYPE_BULK 2
362 #define DWC3_DEPCMD_TYPE_INTR 3
363
364 /* Structures */
365
366 struct dwc3_trb;
367
368 /**
369 * struct dwc3_event_buffer - Software event buffer representation
370 * @list: a list of event buffers
371 * @buf: _THE_ buffer
372 * @length: size of this buffer
373 * @lpos: event offset
374 * @count: cache of last read event count register
375 * @flags: flags related to this event buffer
376 * @dma: dma_addr_t
377 * @dwc: pointer to DWC controller
378 */
379 struct dwc3_event_buffer {
380 void *buf;
381 unsigned length;
382 unsigned int lpos;
383 unsigned int count;
384 unsigned int flags;
385
386 #define DWC3_EVENT_PENDING BIT(0)
387
388 dma_addr_t dma;
389
390 struct dwc3 *dwc;
391 };
392
393 #define DWC3_EP_FLAG_STALLED (1 << 0)
394 #define DWC3_EP_FLAG_WEDGED (1 << 1)
395
396 #define DWC3_EP_DIRECTION_TX true
397 #define DWC3_EP_DIRECTION_RX false
398
399 #define DWC3_TRB_NUM 32
400 #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1)
401
402 /**
403 * struct dwc3_ep - device side endpoint representation
404 * @endpoint: usb endpoint
405 * @request_list: list of requests for this endpoint
406 * @req_queued: list of requests on this ep which have TRBs setup
407 * @trb_pool: array of transaction buffers
408 * @trb_pool_dma: dma address of @trb_pool
409 * @free_slot: next slot which is going to be used
410 * @busy_slot: first slot which is owned by HW
411 * @desc: usb_endpoint_descriptor pointer
412 * @dwc: pointer to DWC controller
413 * @flags: endpoint flags (wedged, stalled, ...)
414 * @current_trb: index of current used trb
415 * @number: endpoint number (1 - 15)
416 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
417 * @resource_index: Resource transfer index
418 * @interval: the intervall on which the ISOC transfer is started
419 * @name: a human readable name e.g. ep1out-bulk
420 * @direction: true for TX, false for RX
421 * @stream_capable: true when streams are enabled
422 */
423 struct dwc3_ep {
424 struct usb_ep endpoint;
425 struct list_head request_list;
426 struct list_head req_queued;
427
428 struct dwc3_trb *trb_pool;
429 dma_addr_t trb_pool_dma;
430 u32 free_slot;
431 u32 busy_slot;
432 const struct usb_ss_ep_comp_descriptor *comp_desc;
433 struct dwc3 *dwc;
434
435 unsigned flags;
436 #define DWC3_EP_ENABLED (1 << 0)
437 #define DWC3_EP_STALL (1 << 1)
438 #define DWC3_EP_WEDGE (1 << 2)
439 #define DWC3_EP_BUSY (1 << 4)
440 #define DWC3_EP_PENDING_REQUEST (1 << 5)
441 #define DWC3_EP_MISSED_ISOC (1 << 6)
442
443 /* This last one is specific to EP0 */
444 #define DWC3_EP0_DIR_IN (1 << 31)
445
446 unsigned current_trb;
447
448 u8 number;
449 u8 type;
450 u8 resource_index;
451 u32 interval;
452
453 char name[20];
454
455 unsigned direction:1;
456 unsigned stream_capable:1;
457 };
458
459 enum dwc3_phy {
460 DWC3_PHY_UNKNOWN = 0,
461 DWC3_PHY_USB3,
462 DWC3_PHY_USB2,
463 };
464
465 enum dwc3_ep0_next {
466 DWC3_EP0_UNKNOWN = 0,
467 DWC3_EP0_COMPLETE,
468 DWC3_EP0_NRDY_DATA,
469 DWC3_EP0_NRDY_STATUS,
470 };
471
472 enum dwc3_ep0_state {
473 EP0_UNCONNECTED = 0,
474 EP0_SETUP_PHASE,
475 EP0_DATA_PHASE,
476 EP0_STATUS_PHASE,
477 };
478
479 enum dwc3_link_state {
480 /* In SuperSpeed */
481 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
482 DWC3_LINK_STATE_U1 = 0x01,
483 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
484 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
485 DWC3_LINK_STATE_SS_DIS = 0x04,
486 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
487 DWC3_LINK_STATE_SS_INACT = 0x06,
488 DWC3_LINK_STATE_POLL = 0x07,
489 DWC3_LINK_STATE_RECOV = 0x08,
490 DWC3_LINK_STATE_HRESET = 0x09,
491 DWC3_LINK_STATE_CMPLY = 0x0a,
492 DWC3_LINK_STATE_LPBK = 0x0b,
493 DWC3_LINK_STATE_RESET = 0x0e,
494 DWC3_LINK_STATE_RESUME = 0x0f,
495 DWC3_LINK_STATE_MASK = 0x0f,
496 };
497
498 /* TRB Length, PCM and Status */
499 #define DWC3_TRB_SIZE_MASK (0x00ffffff)
500 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
501 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
502 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
503
504 #define DWC3_TRBSTS_OK 0
505 #define DWC3_TRBSTS_MISSED_ISOC 1
506 #define DWC3_TRBSTS_SETUP_PENDING 2
507 #define DWC3_TRB_STS_XFER_IN_PROG 4
508
509 /* TRB Control */
510 #define DWC3_TRB_CTRL_HWO (1 << 0)
511 #define DWC3_TRB_CTRL_LST (1 << 1)
512 #define DWC3_TRB_CTRL_CHN (1 << 2)
513 #define DWC3_TRB_CTRL_CSP (1 << 3)
514 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
515 #define DWC3_TRB_CTRL_ISP_IMI (1 << 10)
516 #define DWC3_TRB_CTRL_IOC (1 << 11)
517 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
518
519 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
520 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
521 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
522 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
523 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
524 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
525 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
526 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
527
528 /**
529 * struct dwc3_trb - transfer request block (hw format)
530 * @bpl: DW0-3
531 * @bph: DW4-7
532 * @size: DW8-B
533 * @trl: DWC-F
534 */
535 struct dwc3_trb {
536 u32 bpl;
537 u32 bph;
538 u32 size;
539 u32 ctrl;
540 } __packed;
541
542 /**
543 * dwc3_hwparams - copy of HWPARAMS registers
544 * @hwparams0 - GHWPARAMS0
545 * @hwparams1 - GHWPARAMS1
546 * @hwparams2 - GHWPARAMS2
547 * @hwparams3 - GHWPARAMS3
548 * @hwparams4 - GHWPARAMS4
549 * @hwparams5 - GHWPARAMS5
550 * @hwparams6 - GHWPARAMS6
551 * @hwparams7 - GHWPARAMS7
552 * @hwparams8 - GHWPARAMS8
553 */
554 struct dwc3_hwparams {
555 u32 hwparams0;
556 u32 hwparams1;
557 u32 hwparams2;
558 u32 hwparams3;
559 u32 hwparams4;
560 u32 hwparams5;
561 u32 hwparams6;
562 u32 hwparams7;
563 u32 hwparams8;
564 };
565
566 /* HWPARAMS0 */
567 #define DWC3_MODE(n) ((n) & 0x7)
568
569 #define DWC3_MODE_DEVICE 0
570 #define DWC3_MODE_HOST 1
571 #define DWC3_MODE_DRD 2
572 #define DWC3_MODE_HUB 3
573
574 #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
575
576 /* HWPARAMS1 */
577 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
578
579 /* HWPARAMS3 */
580 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
581 #define DWC3_NUM_EPS_MASK (0x3f << 12)
582 #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
583 (DWC3_NUM_EPS_MASK)) >> 12)
584 #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
585 (DWC3_NUM_IN_EPS_MASK)) >> 18)
586
587 /* HWPARAMS7 */
588 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
589
590 struct dwc3_request {
591 struct usb_request request;
592 struct list_head list;
593 struct dwc3_ep *dep;
594 u32 start_slot;
595
596 u8 epnum;
597 struct dwc3_trb *trb;
598 dma_addr_t trb_dma;
599
600 unsigned direction:1;
601 unsigned mapped:1;
602 unsigned queued:1;
603 };
604
605 /*
606 * struct dwc3_scratchpad_array - hibernation scratchpad array
607 * (format defined by hw)
608 */
609 struct dwc3_scratchpad_array {
610 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
611 };
612
613 /**
614 * struct dwc3 - representation of our controller
615 * @ctrl_req: usb control request which is used for ep0
616 * @ep0_trb: trb which is used for the ctrl_req
617 * @ep0_bounce: bounce buffer for ep0
618 * @setup_buf: used while precessing STD USB requests
619 * @ctrl_req_addr: dma address of ctrl_req
620 * @ep0_trb: dma address of ep0_trb
621 * @ep0_usb_req: dummy req used while handling STD USB requests
622 * @ep0_bounce_addr: dma address of ep0_bounce
623 * @lock: for synchronizing
624 * @dev: pointer to our struct device
625 * @xhci: pointer to our xHCI child
626 * @event_buffer_list: a list of event buffers
627 * @gadget: device side representation of the peripheral controller
628 * @gadget_driver: pointer to the gadget driver
629 * @regs: base address for our registers
630 * @regs_size: address space size
631 * @num_event_buffers: calculated number of event buffers
632 * @u1u2: only used on revisions <1.83a for workaround
633 * @maximum_speed: maximum speed requested (mainly for testing purposes)
634 * @revision: revision register contents
635 * @mode: mode of operation
636 * @usb2_phy: pointer to USB2 PHY
637 * @usb3_phy: pointer to USB3 PHY
638 * @dcfg: saved contents of DCFG register
639 * @gctl: saved contents of GCTL register
640 * @is_selfpowered: true when we are selfpowered
641 * @three_stage_setup: set if we perform a three phase setup
642 * @ep0_bounced: true when we used bounce buffer
643 * @ep0_expect_in: true when we expect a DATA IN transfer
644 * @start_config_issued: true when StartConfig command has been issued
645 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
646 * @needs_fifo_resize: not all users might want fifo resizing, flag it
647 * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes.
648 * @isoch_delay: wValue from Set Isochronous Delay request;
649 * @u2sel: parameter from Set SEL request.
650 * @u2pel: parameter from Set SEL request.
651 * @u1sel: parameter from Set SEL request.
652 * @u1pel: parameter from Set SEL request.
653 * @num_out_eps: number of out endpoints
654 * @num_in_eps: number of in endpoints
655 * @ep0_next_event: hold the next expected event
656 * @ep0state: state of endpoint zero
657 * @link_state: link state
658 * @speed: device speed (super, high, full, low)
659 * @mem: points to start of memory which is used for this struct.
660 * @hwparams: copy of hwparams registers
661 * @root: debugfs root folder pointer
662 */
663 struct dwc3 {
664 struct usb_ctrlrequest *ctrl_req;
665 struct dwc3_trb *ep0_trb;
666 void *ep0_bounce;
667 u8 *setup_buf;
668 dma_addr_t ctrl_req_addr;
669 dma_addr_t ep0_trb_addr;
670 dma_addr_t ep0_bounce_addr;
671 struct dwc3_request ep0_usb_req;
672
673 /* device lock */
674 spinlock_t lock;
675
676 struct device *dev;
677
678 struct platform_device *xhci;
679 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
680
681 struct dwc3_event_buffer **ev_buffs;
682 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
683
684 struct usb_gadget gadget;
685 struct usb_gadget_driver *gadget_driver;
686
687 struct usb_phy *usb2_phy;
688 struct usb_phy *usb3_phy;
689
690 void __iomem *regs;
691 size_t regs_size;
692
693 /* used for suspend/resume */
694 u32 dcfg;
695 u32 gctl;
696
697 u32 num_event_buffers;
698 u32 u1u2;
699 u32 maximum_speed;
700 u32 revision;
701 u32 mode;
702
703 #define DWC3_REVISION_173A 0x5533173a
704 #define DWC3_REVISION_175A 0x5533175a
705 #define DWC3_REVISION_180A 0x5533180a
706 #define DWC3_REVISION_183A 0x5533183a
707 #define DWC3_REVISION_185A 0x5533185a
708 #define DWC3_REVISION_187A 0x5533187a
709 #define DWC3_REVISION_188A 0x5533188a
710 #define DWC3_REVISION_190A 0x5533190a
711 #define DWC3_REVISION_194A 0x5533194a
712 #define DWC3_REVISION_200A 0x5533200a
713 #define DWC3_REVISION_202A 0x5533202a
714 #define DWC3_REVISION_210A 0x5533210a
715 #define DWC3_REVISION_220A 0x5533220a
716 #define DWC3_REVISION_230A 0x5533230a
717 #define DWC3_REVISION_240A 0x5533240a
718 #define DWC3_REVISION_250A 0x5533250a
719
720 unsigned is_selfpowered:1;
721 unsigned three_stage_setup:1;
722 unsigned ep0_bounced:1;
723 unsigned ep0_expect_in:1;
724 unsigned start_config_issued:1;
725 unsigned setup_packet_pending:1;
726 unsigned delayed_status:1;
727 unsigned needs_fifo_resize:1;
728 unsigned resize_fifos:1;
729 unsigned pullups_connected:1;
730
731 enum dwc3_ep0_next ep0_next_event;
732 enum dwc3_ep0_state ep0state;
733 enum dwc3_link_state link_state;
734
735 u16 isoch_delay;
736 u16 u2sel;
737 u16 u2pel;
738 u8 u1sel;
739 u8 u1pel;
740
741 u8 speed;
742
743 u8 num_out_eps;
744 u8 num_in_eps;
745
746 void *mem;
747
748 struct dwc3_hwparams hwparams;
749 struct dentry *root;
750 struct debugfs_regset32 *regset;
751
752 u8 test_mode;
753 u8 test_mode_nr;
754 };
755
756 /* -------------------------------------------------------------------------- */
757
758 /* -------------------------------------------------------------------------- */
759
760 struct dwc3_event_type {
761 u32 is_devspec:1;
762 u32 type:6;
763 u32 reserved8_31:25;
764 } __packed;
765
766 #define DWC3_DEPEVT_XFERCOMPLETE 0x01
767 #define DWC3_DEPEVT_XFERINPROGRESS 0x02
768 #define DWC3_DEPEVT_XFERNOTREADY 0x03
769 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04
770 #define DWC3_DEPEVT_STREAMEVT 0x06
771 #define DWC3_DEPEVT_EPCMDCMPLT 0x07
772
773 /**
774 * struct dwc3_event_depvt - Device Endpoint Events
775 * @one_bit: indicates this is an endpoint event (not used)
776 * @endpoint_number: number of the endpoint
777 * @endpoint_event: The event we have:
778 * 0x00 - Reserved
779 * 0x01 - XferComplete
780 * 0x02 - XferInProgress
781 * 0x03 - XferNotReady
782 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
783 * 0x05 - Reserved
784 * 0x06 - StreamEvt
785 * 0x07 - EPCmdCmplt
786 * @reserved11_10: Reserved, don't use.
787 * @status: Indicates the status of the event. Refer to databook for
788 * more information.
789 * @parameters: Parameters of the current event. Refer to databook for
790 * more information.
791 */
792 struct dwc3_event_depevt {
793 u32 one_bit:1;
794 u32 endpoint_number:5;
795 u32 endpoint_event:4;
796 u32 reserved11_10:2;
797 u32 status:4;
798
799 /* Within XferNotReady */
800 #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3)
801
802 /* Within XferComplete */
803 #define DEPEVT_STATUS_BUSERR (1 << 0)
804 #define DEPEVT_STATUS_SHORT (1 << 1)
805 #define DEPEVT_STATUS_IOC (1 << 2)
806 #define DEPEVT_STATUS_LST (1 << 3)
807
808 /* Stream event only */
809 #define DEPEVT_STREAMEVT_FOUND 1
810 #define DEPEVT_STREAMEVT_NOTFOUND 2
811
812 /* Control-only Status */
813 #define DEPEVT_STATUS_CONTROL_DATA 1
814 #define DEPEVT_STATUS_CONTROL_STATUS 2
815
816 u32 parameters:16;
817 } __packed;
818
819 /**
820 * struct dwc3_event_devt - Device Events
821 * @one_bit: indicates this is a non-endpoint event (not used)
822 * @device_event: indicates it's a device event. Should read as 0x00
823 * @type: indicates the type of device event.
824 * 0 - DisconnEvt
825 * 1 - USBRst
826 * 2 - ConnectDone
827 * 3 - ULStChng
828 * 4 - WkUpEvt
829 * 5 - Reserved
830 * 6 - EOPF
831 * 7 - SOF
832 * 8 - Reserved
833 * 9 - ErrticErr
834 * 10 - CmdCmplt
835 * 11 - EvntOverflow
836 * 12 - VndrDevTstRcved
837 * @reserved15_12: Reserved, not used
838 * @event_info: Information about this event
839 * @reserved31_24: Reserved, not used
840 */
841 struct dwc3_event_devt {
842 u32 one_bit:1;
843 u32 device_event:7;
844 u32 type:4;
845 u32 reserved15_12:4;
846 u32 event_info:8;
847 u32 reserved31_24:8;
848 } __packed;
849
850 /**
851 * struct dwc3_event_gevt - Other Core Events
852 * @one_bit: indicates this is a non-endpoint event (not used)
853 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
854 * @phy_port_number: self-explanatory
855 * @reserved31_12: Reserved, not used.
856 */
857 struct dwc3_event_gevt {
858 u32 one_bit:1;
859 u32 device_event:7;
860 u32 phy_port_number:4;
861 u32 reserved31_12:20;
862 } __packed;
863
864 /**
865 * union dwc3_event - representation of Event Buffer contents
866 * @raw: raw 32-bit event
867 * @type: the type of the event
868 * @depevt: Device Endpoint Event
869 * @devt: Device Event
870 * @gevt: Global Event
871 */
872 union dwc3_event {
873 u32 raw;
874 struct dwc3_event_type type;
875 struct dwc3_event_depevt depevt;
876 struct dwc3_event_devt devt;
877 struct dwc3_event_gevt gevt;
878 };
879
880 /*
881 * DWC3 Features to be used as Driver Data
882 */
883
884 #define DWC3_HAS_PERIPHERAL BIT(0)
885 #define DWC3_HAS_XHCI BIT(1)
886 #define DWC3_HAS_OTG BIT(3)
887
888 /* prototypes */
889 void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
890 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc);
891
892 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
893 int dwc3_host_init(struct dwc3 *dwc);
894 void dwc3_host_exit(struct dwc3 *dwc);
895 #else
dwc3_host_init(struct dwc3 * dwc)896 static inline int dwc3_host_init(struct dwc3 *dwc)
897 { return 0; }
dwc3_host_exit(struct dwc3 * dwc)898 static inline void dwc3_host_exit(struct dwc3 *dwc)
899 { }
900 #endif
901
902 #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
903 int dwc3_gadget_init(struct dwc3 *dwc);
904 void dwc3_gadget_exit(struct dwc3 *dwc);
905 #else
dwc3_gadget_init(struct dwc3 * dwc)906 static inline int dwc3_gadget_init(struct dwc3 *dwc)
907 { return 0; }
dwc3_gadget_exit(struct dwc3 * dwc)908 static inline void dwc3_gadget_exit(struct dwc3 *dwc)
909 { }
910 #endif
911
912 /* power management interface */
913 #if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
914 int dwc3_gadget_prepare(struct dwc3 *dwc);
915 void dwc3_gadget_complete(struct dwc3 *dwc);
916 int dwc3_gadget_suspend(struct dwc3 *dwc);
917 int dwc3_gadget_resume(struct dwc3 *dwc);
918 #else
dwc3_gadget_prepare(struct dwc3 * dwc)919 static inline int dwc3_gadget_prepare(struct dwc3 *dwc)
920 {
921 return 0;
922 }
923
dwc3_gadget_complete(struct dwc3 * dwc)924 static inline void dwc3_gadget_complete(struct dwc3 *dwc)
925 {
926 }
927
dwc3_gadget_suspend(struct dwc3 * dwc)928 static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
929 {
930 return 0;
931 }
932
dwc3_gadget_resume(struct dwc3 * dwc)933 static inline int dwc3_gadget_resume(struct dwc3 *dwc)
934 {
935 return 0;
936 }
937 #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */
938
939 #endif /* __DRIVERS_USB_DWC3_CORE_H */
940