1 /**************************************************************************** 2 * Driver for Solarflare Solarstorm network controllers and boards 3 * Copyright 2009-2011 Solarflare Communications Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published 7 * by the Free Software Foundation, incorporated herein by reference. 8 */ 9 10 11 #ifndef MCDI_PCOL_H 12 #define MCDI_PCOL_H 13 14 /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */ 15 /* Power-on reset state */ 16 #define MC_FW_STATE_POR (1) 17 /* If this is set in MC_RESET_STATE_REG then it should be 18 * possible to jump into IMEM without loading code from flash. */ 19 #define MC_FW_WARM_BOOT_OK (2) 20 /* The MC main image has started to boot. */ 21 #define MC_FW_STATE_BOOTING (4) 22 /* The Scheduler has started. */ 23 #define MC_FW_STATE_SCHED (8) 24 25 /* Siena MC shared memmory offsets */ 26 /* The 'doorbell' addresses are hard-wired to alert the MC when written */ 27 #define MC_SMEM_P0_DOORBELL_OFST 0x000 28 #define MC_SMEM_P1_DOORBELL_OFST 0x004 29 /* The rest of these are firmware-defined */ 30 #define MC_SMEM_P0_PDU_OFST 0x008 31 #define MC_SMEM_P1_PDU_OFST 0x108 32 #define MC_SMEM_PDU_LEN 0x100 33 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0 34 #define MC_SMEM_P0_STATUS_OFST 0x7f8 35 #define MC_SMEM_P1_STATUS_OFST 0x7fc 36 37 /* Values to be written to the per-port status dword in shared 38 * memory on reboot and assert */ 39 #define MC_STATUS_DWORD_REBOOT (0xb007b007) 40 #define MC_STATUS_DWORD_ASSERT (0xdeaddead) 41 42 /* The current version of the MCDI protocol. 43 * 44 * Note that the ROM burnt into the card only talks V0, so at the very 45 * least every driver must support version 0 and MCDI_PCOL_VERSION 46 */ 47 #define MCDI_PCOL_VERSION 1 48 49 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */ 50 51 /* MCDI version 1 52 * 53 * Each MCDI request starts with an MCDI_HEADER, which is a 32byte 54 * structure, filled in by the client. 55 * 56 * 0 7 8 16 20 22 23 24 31 57 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS | 58 * | | | 59 * | | \--- Response 60 * | \------- Error 61 * \------------------------------ Resync (always set) 62 * 63 * The client writes it's request into MC shared memory, and rings the 64 * doorbell. Each request is completed by either by the MC writting 65 * back into shared memory, or by writting out an event. 66 * 67 * All MCDI commands support completion by shared memory response. Each 68 * request may also contain additional data (accounted for by HEADER.LEN), 69 * and some response's may also contain additional data (again, accounted 70 * for by HEADER.LEN). 71 * 72 * Some MCDI commands support completion by event, in which any associated 73 * response data is included in the event. 74 * 75 * The protocol requires one response to be delivered for every request, a 76 * request should not be sent unless the response for the previous request 77 * has been received (either by polling shared memory, or by receiving 78 * an event). 79 */ 80 81 /** Request/Response structure */ 82 #define MCDI_HEADER_OFST 0 83 #define MCDI_HEADER_CODE_LBN 0 84 #define MCDI_HEADER_CODE_WIDTH 7 85 #define MCDI_HEADER_RESYNC_LBN 7 86 #define MCDI_HEADER_RESYNC_WIDTH 1 87 #define MCDI_HEADER_DATALEN_LBN 8 88 #define MCDI_HEADER_DATALEN_WIDTH 8 89 #define MCDI_HEADER_SEQ_LBN 16 90 #define MCDI_HEADER_RSVD_LBN 20 91 #define MCDI_HEADER_RSVD_WIDTH 2 92 #define MCDI_HEADER_SEQ_WIDTH 4 93 #define MCDI_HEADER_ERROR_LBN 22 94 #define MCDI_HEADER_ERROR_WIDTH 1 95 #define MCDI_HEADER_RESPONSE_LBN 23 96 #define MCDI_HEADER_RESPONSE_WIDTH 1 97 #define MCDI_HEADER_XFLAGS_LBN 24 98 #define MCDI_HEADER_XFLAGS_WIDTH 8 99 /* Request response using event */ 100 #define MCDI_HEADER_XFLAGS_EVREQ 0x01 101 102 /* Maximum number of payload bytes */ 103 #define MCDI_CTL_SDU_LEN_MAX 0xfc 104 105 /* The MC can generate events for two reasons: 106 * - To complete a shared memory request if XFLAGS_EVREQ was set 107 * - As a notification (link state, i2c event), controlled 108 * via MC_CMD_LOG_CTRL 109 * 110 * Both events share a common structure: 111 * 112 * 0 32 33 36 44 52 60 113 * | Data | Cont | Level | Src | Code | Rsvd | 114 * | 115 * \ There is another event pending in this notification 116 * 117 * If Code==CMDDONE, then the fields are further interpreted as: 118 * 119 * - LEVEL==INFO Command succeeded 120 * - LEVEL==ERR Command failed 121 * 122 * 0 8 16 24 32 123 * | Seq | Datalen | Errno | Rsvd | 124 * 125 * These fields are taken directly out of the standard MCDI header, i.e., 126 * LEVEL==ERR, Datalen == 0 => Reboot 127 * 128 * Events can be squirted out of the UART (using LOG_CTRL) without a 129 * MCDI header. An event can be distinguished from a MCDI response by 130 * examining the first byte which is 0xc0. This corresponds to the 131 * non-existent MCDI command MC_CMD_DEBUG_LOG. 132 * 133 * 0 7 8 134 * | command | Resync | = 0xc0 135 * 136 * Since the event is written in big-endian byte order, this works 137 * providing bits 56-63 of the event are 0xc0. 138 * 139 * 56 60 63 140 * | Rsvd | Code | = 0xc0 141 * 142 * Which means for convenience the event code is 0xc for all MC 143 * generated events. 144 */ 145 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc 146 147 148 /* Non-existent command target */ 149 #define MC_CMD_ERR_ENOENT 2 150 /* assert() has killed the MC */ 151 #define MC_CMD_ERR_EINTR 4 152 /* Caller does not hold required locks */ 153 #define MC_CMD_ERR_EACCES 13 154 /* Resource is currently unavailable (e.g. lock contention) */ 155 #define MC_CMD_ERR_EBUSY 16 156 /* Invalid argument to target */ 157 #define MC_CMD_ERR_EINVAL 22 158 /* Non-recursive resource is already acquired */ 159 #define MC_CMD_ERR_EDEADLK 35 160 /* Operation not implemented */ 161 #define MC_CMD_ERR_ENOSYS 38 162 /* Operation timed out */ 163 #define MC_CMD_ERR_ETIME 62 164 165 #define MC_CMD_ERR_CODE_OFST 0 166 167 /* We define 8 "escape" commands to allow 168 for command number space extension */ 169 170 #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78 171 #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79 172 #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A 173 #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B 174 #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C 175 #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D 176 #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E 177 #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F 178 179 /* Vectors in the boot ROM */ 180 /* Point to the copycode entry point. */ 181 #define MC_BOOTROM_COPYCODE_VEC (0x7f4) 182 /* Points to the recovery mode entry point. */ 183 #define MC_BOOTROM_NOFLASH_VEC (0x7f8) 184 185 /* The command set exported by the boot ROM (MCDI v0) */ 186 #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \ 187 (1 << MC_CMD_READ32) | \ 188 (1 << MC_CMD_WRITE32) | \ 189 (1 << MC_CMD_COPYCODE) | \ 190 (1 << MC_CMD_GET_VERSION), \ 191 0, 0, 0 } 192 193 #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \ 194 (MC_CMD_SENSOR_ENTRY_OFST + (_x)) 195 196 #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \ 197 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 198 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \ 199 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 200 201 #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \ 202 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 203 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \ 204 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 205 206 #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \ 207 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 208 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \ 209 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 210 211 212 /* MCDI_EVENT structuredef */ 213 #define MCDI_EVENT_LEN 8 214 #define MCDI_EVENT_CONT_LBN 32 215 #define MCDI_EVENT_CONT_WIDTH 1 216 #define MCDI_EVENT_LEVEL_LBN 33 217 #define MCDI_EVENT_LEVEL_WIDTH 3 218 #define MCDI_EVENT_LEVEL_INFO 0x0 /* enum */ 219 #define MCDI_EVENT_LEVEL_WARN 0x1 /* enum */ 220 #define MCDI_EVENT_LEVEL_ERR 0x2 /* enum */ 221 #define MCDI_EVENT_LEVEL_FATAL 0x3 /* enum */ 222 #define MCDI_EVENT_DATA_OFST 0 223 #define MCDI_EVENT_CMDDONE_SEQ_LBN 0 224 #define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8 225 #define MCDI_EVENT_CMDDONE_DATALEN_LBN 8 226 #define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8 227 #define MCDI_EVENT_CMDDONE_ERRNO_LBN 16 228 #define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8 229 #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0 230 #define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16 231 #define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16 232 #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4 233 #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1 /* enum */ 234 #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2 /* enum */ 235 #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3 /* enum */ 236 #define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20 237 #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4 238 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24 239 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8 240 #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0 241 #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8 242 #define MCDI_EVENT_SENSOREVT_STATE_LBN 8 243 #define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8 244 #define MCDI_EVENT_SENSOREVT_VALUE_LBN 16 245 #define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16 246 #define MCDI_EVENT_FWALERT_DATA_LBN 8 247 #define MCDI_EVENT_FWALERT_DATA_WIDTH 24 248 #define MCDI_EVENT_FWALERT_REASON_LBN 0 249 #define MCDI_EVENT_FWALERT_REASON_WIDTH 8 250 #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 /* enum */ 251 #define MCDI_EVENT_FLR_VF_LBN 0 252 #define MCDI_EVENT_FLR_VF_WIDTH 8 253 #define MCDI_EVENT_TX_ERR_TXQ_LBN 0 254 #define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12 255 #define MCDI_EVENT_TX_ERR_TYPE_LBN 12 256 #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4 257 #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1 /* enum */ 258 #define MCDI_EVENT_TX_ERR_NO_EOP 0x2 /* enum */ 259 #define MCDI_EVENT_TX_ERR_2BIG 0x3 /* enum */ 260 #define MCDI_EVENT_TX_ERR_INFO_LBN 16 261 #define MCDI_EVENT_TX_ERR_INFO_WIDTH 16 262 #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0 263 #define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12 264 #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0 265 #define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8 266 #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 /* enum */ 267 #define MCDI_EVENT_PTP_ERR_FILTER 0x2 /* enum */ 268 #define MCDI_EVENT_PTP_ERR_FIFO 0x3 /* enum */ 269 #define MCDI_EVENT_PTP_ERR_QUEUE 0x4 /* enum */ 270 #define MCDI_EVENT_DATA_LBN 0 271 #define MCDI_EVENT_DATA_WIDTH 32 272 #define MCDI_EVENT_SRC_LBN 36 273 #define MCDI_EVENT_SRC_WIDTH 8 274 #define MCDI_EVENT_EV_CODE_LBN 60 275 #define MCDI_EVENT_EV_CODE_WIDTH 4 276 #define MCDI_EVENT_CODE_LBN 44 277 #define MCDI_EVENT_CODE_WIDTH 8 278 #define MCDI_EVENT_CODE_BADSSERT 0x1 /* enum */ 279 #define MCDI_EVENT_CODE_PMNOTICE 0x2 /* enum */ 280 #define MCDI_EVENT_CODE_CMDDONE 0x3 /* enum */ 281 #define MCDI_EVENT_CODE_LINKCHANGE 0x4 /* enum */ 282 #define MCDI_EVENT_CODE_SENSOREVT 0x5 /* enum */ 283 #define MCDI_EVENT_CODE_SCHEDERR 0x6 /* enum */ 284 #define MCDI_EVENT_CODE_REBOOT 0x7 /* enum */ 285 #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8 /* enum */ 286 #define MCDI_EVENT_CODE_FWALERT 0x9 /* enum */ 287 #define MCDI_EVENT_CODE_FLR 0xa /* enum */ 288 #define MCDI_EVENT_CODE_TX_ERR 0xb /* enum */ 289 #define MCDI_EVENT_CODE_TX_FLUSH 0xc /* enum */ 290 #define MCDI_EVENT_CODE_PTP_RX 0xd /* enum */ 291 #define MCDI_EVENT_CODE_PTP_FAULT 0xe /* enum */ 292 #define MCDI_EVENT_CODE_PTP_PPS 0xf /* enum */ 293 #define MCDI_EVENT_CMDDONE_DATA_OFST 0 294 #define MCDI_EVENT_CMDDONE_DATA_LBN 0 295 #define MCDI_EVENT_CMDDONE_DATA_WIDTH 32 296 #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0 297 #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0 298 #define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32 299 #define MCDI_EVENT_SENSOREVT_DATA_OFST 0 300 #define MCDI_EVENT_SENSOREVT_DATA_LBN 0 301 #define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32 302 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0 303 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0 304 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32 305 #define MCDI_EVENT_TX_ERR_DATA_OFST 0 306 #define MCDI_EVENT_TX_ERR_DATA_LBN 0 307 #define MCDI_EVENT_TX_ERR_DATA_WIDTH 32 308 #define MCDI_EVENT_PTP_SECONDS_OFST 0 309 #define MCDI_EVENT_PTP_SECONDS_LBN 0 310 #define MCDI_EVENT_PTP_SECONDS_WIDTH 32 311 #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0 312 #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0 313 #define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32 314 #define MCDI_EVENT_PTP_UUID_OFST 0 315 #define MCDI_EVENT_PTP_UUID_LBN 0 316 #define MCDI_EVENT_PTP_UUID_WIDTH 32 317 318 319 /***********************************/ 320 /* MC_CMD_READ32 321 * Read multiple 32byte words from MC memory. 322 */ 323 #define MC_CMD_READ32 0x1 324 325 /* MC_CMD_READ32_IN msgrequest */ 326 #define MC_CMD_READ32_IN_LEN 8 327 #define MC_CMD_READ32_IN_ADDR_OFST 0 328 #define MC_CMD_READ32_IN_NUMWORDS_OFST 4 329 330 /* MC_CMD_READ32_OUT msgresponse */ 331 #define MC_CMD_READ32_OUT_LENMIN 4 332 #define MC_CMD_READ32_OUT_LENMAX 252 333 #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num)) 334 #define MC_CMD_READ32_OUT_BUFFER_OFST 0 335 #define MC_CMD_READ32_OUT_BUFFER_LEN 4 336 #define MC_CMD_READ32_OUT_BUFFER_MINNUM 1 337 #define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63 338 339 340 /***********************************/ 341 /* MC_CMD_WRITE32 342 * Write multiple 32byte words to MC memory. 343 */ 344 #define MC_CMD_WRITE32 0x2 345 346 /* MC_CMD_WRITE32_IN msgrequest */ 347 #define MC_CMD_WRITE32_IN_LENMIN 8 348 #define MC_CMD_WRITE32_IN_LENMAX 252 349 #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num)) 350 #define MC_CMD_WRITE32_IN_ADDR_OFST 0 351 #define MC_CMD_WRITE32_IN_BUFFER_OFST 4 352 #define MC_CMD_WRITE32_IN_BUFFER_LEN 4 353 #define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1 354 #define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62 355 356 /* MC_CMD_WRITE32_OUT msgresponse */ 357 #define MC_CMD_WRITE32_OUT_LEN 0 358 359 360 /***********************************/ 361 /* MC_CMD_COPYCODE 362 * Copy MC code between two locations and jump. 363 */ 364 #define MC_CMD_COPYCODE 0x3 365 366 /* MC_CMD_COPYCODE_IN msgrequest */ 367 #define MC_CMD_COPYCODE_IN_LEN 16 368 #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0 369 #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4 370 #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8 371 #define MC_CMD_COPYCODE_IN_JUMP_OFST 12 372 #define MC_CMD_COPYCODE_JUMP_NONE 0x1 /* enum */ 373 374 /* MC_CMD_COPYCODE_OUT msgresponse */ 375 #define MC_CMD_COPYCODE_OUT_LEN 0 376 377 378 /***********************************/ 379 /* MC_CMD_SET_FUNC 380 */ 381 #define MC_CMD_SET_FUNC 0x4 382 383 /* MC_CMD_SET_FUNC_IN msgrequest */ 384 #define MC_CMD_SET_FUNC_IN_LEN 4 385 #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0 386 387 /* MC_CMD_SET_FUNC_OUT msgresponse */ 388 #define MC_CMD_SET_FUNC_OUT_LEN 0 389 390 391 /***********************************/ 392 /* MC_CMD_GET_BOOT_STATUS 393 */ 394 #define MC_CMD_GET_BOOT_STATUS 0x5 395 396 /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */ 397 #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0 398 399 /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */ 400 #define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8 401 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0 402 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4 403 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0 404 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1 405 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1 406 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1 407 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2 408 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1 409 410 411 /***********************************/ 412 /* MC_CMD_GET_ASSERTS 413 * Get and clear any assertion status. 414 */ 415 #define MC_CMD_GET_ASSERTS 0x6 416 417 /* MC_CMD_GET_ASSERTS_IN msgrequest */ 418 #define MC_CMD_GET_ASSERTS_IN_LEN 4 419 #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0 420 421 /* MC_CMD_GET_ASSERTS_OUT msgresponse */ 422 #define MC_CMD_GET_ASSERTS_OUT_LEN 140 423 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0 424 #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 /* enum */ 425 #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 /* enum */ 426 #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 /* enum */ 427 #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 /* enum */ 428 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4 429 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8 430 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4 431 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31 432 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132 433 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136 434 435 436 /***********************************/ 437 /* MC_CMD_LOG_CTRL 438 * Configure the output stream for various events and messages. 439 */ 440 #define MC_CMD_LOG_CTRL 0x7 441 442 /* MC_CMD_LOG_CTRL_IN msgrequest */ 443 #define MC_CMD_LOG_CTRL_IN_LEN 8 444 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0 445 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1 /* enum */ 446 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2 /* enum */ 447 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4 448 449 /* MC_CMD_LOG_CTRL_OUT msgresponse */ 450 #define MC_CMD_LOG_CTRL_OUT_LEN 0 451 452 453 /***********************************/ 454 /* MC_CMD_GET_VERSION 455 * Get version information about the MC firmware. 456 */ 457 #define MC_CMD_GET_VERSION 0x8 458 459 /* MC_CMD_GET_VERSION_IN msgrequest */ 460 #define MC_CMD_GET_VERSION_IN_LEN 0 461 462 /* MC_CMD_GET_VERSION_V0_OUT msgresponse */ 463 #define MC_CMD_GET_VERSION_V0_OUT_LEN 4 464 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 465 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff /* enum */ 466 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_BOOTROM 0xb0070000 /* enum */ 467 468 /* MC_CMD_GET_VERSION_OUT msgresponse */ 469 #define MC_CMD_GET_VERSION_OUT_LEN 32 470 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 471 /* Enum values, see field(s): */ 472 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 473 #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4 474 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8 475 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16 476 #define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24 477 #define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8 478 #define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24 479 #define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28 480 481 482 /***********************************/ 483 /* MC_CMD_GET_FPGAREG 484 * Read multiple bytes from PTP FPGA. 485 */ 486 #define MC_CMD_GET_FPGAREG 0x9 487 488 /* MC_CMD_GET_FPGAREG_IN msgrequest */ 489 #define MC_CMD_GET_FPGAREG_IN_LEN 8 490 #define MC_CMD_GET_FPGAREG_IN_ADDR_OFST 0 491 #define MC_CMD_GET_FPGAREG_IN_NUMBYTES_OFST 4 492 493 /* MC_CMD_GET_FPGAREG_OUT msgresponse */ 494 #define MC_CMD_GET_FPGAREG_OUT_LENMIN 1 495 #define MC_CMD_GET_FPGAREG_OUT_LENMAX 252 496 #define MC_CMD_GET_FPGAREG_OUT_LEN(num) (0+1*(num)) 497 #define MC_CMD_GET_FPGAREG_OUT_BUFFER_OFST 0 498 #define MC_CMD_GET_FPGAREG_OUT_BUFFER_LEN 1 499 #define MC_CMD_GET_FPGAREG_OUT_BUFFER_MINNUM 1 500 #define MC_CMD_GET_FPGAREG_OUT_BUFFER_MAXNUM 252 501 502 503 /***********************************/ 504 /* MC_CMD_PUT_FPGAREG 505 * Write multiple bytes to PTP FPGA. 506 */ 507 #define MC_CMD_PUT_FPGAREG 0xa 508 509 /* MC_CMD_PUT_FPGAREG_IN msgrequest */ 510 #define MC_CMD_PUT_FPGAREG_IN_LENMIN 5 511 #define MC_CMD_PUT_FPGAREG_IN_LENMAX 252 512 #define MC_CMD_PUT_FPGAREG_IN_LEN(num) (4+1*(num)) 513 #define MC_CMD_PUT_FPGAREG_IN_ADDR_OFST 0 514 #define MC_CMD_PUT_FPGAREG_IN_BUFFER_OFST 4 515 #define MC_CMD_PUT_FPGAREG_IN_BUFFER_LEN 1 516 #define MC_CMD_PUT_FPGAREG_IN_BUFFER_MINNUM 1 517 #define MC_CMD_PUT_FPGAREG_IN_BUFFER_MAXNUM 248 518 519 /* MC_CMD_PUT_FPGAREG_OUT msgresponse */ 520 #define MC_CMD_PUT_FPGAREG_OUT_LEN 0 521 522 523 /***********************************/ 524 /* MC_CMD_PTP 525 * Perform PTP operation 526 */ 527 #define MC_CMD_PTP 0xb 528 529 /* MC_CMD_PTP_IN msgrequest */ 530 #define MC_CMD_PTP_IN_LEN 1 531 #define MC_CMD_PTP_IN_OP_OFST 0 532 #define MC_CMD_PTP_IN_OP_LEN 1 533 #define MC_CMD_PTP_OP_ENABLE 0x1 /* enum */ 534 #define MC_CMD_PTP_OP_DISABLE 0x2 /* enum */ 535 #define MC_CMD_PTP_OP_TRANSMIT 0x3 /* enum */ 536 #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4 /* enum */ 537 #define MC_CMD_PTP_OP_STATUS 0x5 /* enum */ 538 #define MC_CMD_PTP_OP_ADJUST 0x6 /* enum */ 539 #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7 /* enum */ 540 #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8 /* enum */ 541 #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9 /* enum */ 542 #define MC_CMD_PTP_OP_RESET_STATS 0xa /* enum */ 543 #define MC_CMD_PTP_OP_DEBUG 0xb /* enum */ 544 #define MC_CMD_PTP_OP_MAX 0xc /* enum */ 545 546 /* MC_CMD_PTP_IN_ENABLE msgrequest */ 547 #define MC_CMD_PTP_IN_ENABLE_LEN 16 548 #define MC_CMD_PTP_IN_CMD_OFST 0 549 #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4 550 #define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8 551 #define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12 552 #define MC_CMD_PTP_MODE_V1 0x0 /* enum */ 553 #define MC_CMD_PTP_MODE_V1_VLAN 0x1 /* enum */ 554 #define MC_CMD_PTP_MODE_V2 0x2 /* enum */ 555 #define MC_CMD_PTP_MODE_V2_VLAN 0x3 /* enum */ 556 #define MC_CMD_PTP_MODE_V2_ENHANCED 0x4 /* enum */ 557 558 /* MC_CMD_PTP_IN_DISABLE msgrequest */ 559 #define MC_CMD_PTP_IN_DISABLE_LEN 8 560 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 561 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 562 563 /* MC_CMD_PTP_IN_TRANSMIT msgrequest */ 564 #define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13 565 #define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252 566 #define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num)) 567 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 568 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 569 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8 570 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12 571 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1 572 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1 573 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240 574 575 /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */ 576 #define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8 577 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 578 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 579 580 /* MC_CMD_PTP_IN_STATUS msgrequest */ 581 #define MC_CMD_PTP_IN_STATUS_LEN 8 582 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 583 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 584 585 /* MC_CMD_PTP_IN_ADJUST msgrequest */ 586 #define MC_CMD_PTP_IN_ADJUST_LEN 24 587 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 588 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 589 #define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8 590 #define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8 591 #define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8 592 #define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12 593 #define MC_CMD_PTP_IN_ADJUST_BITS 0x28 /* enum */ 594 #define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16 595 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20 596 597 /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */ 598 #define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20 599 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 600 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 601 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8 602 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12 603 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8 604 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12 605 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16 606 607 /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */ 608 #define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8 609 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 610 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 611 612 /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */ 613 #define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12 614 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 615 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 616 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8 617 618 /* MC_CMD_PTP_IN_RESET_STATS msgrequest */ 619 #define MC_CMD_PTP_IN_RESET_STATS_LEN 8 620 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 621 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 622 623 /* MC_CMD_PTP_IN_DEBUG msgrequest */ 624 #define MC_CMD_PTP_IN_DEBUG_LEN 12 625 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 626 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 627 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8 628 629 /* MC_CMD_PTP_OUT msgresponse */ 630 #define MC_CMD_PTP_OUT_LEN 0 631 632 /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */ 633 #define MC_CMD_PTP_OUT_TRANSMIT_LEN 8 634 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0 635 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4 636 637 /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */ 638 #define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8 639 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0 640 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4 641 642 /* MC_CMD_PTP_OUT_STATUS msgresponse */ 643 #define MC_CMD_PTP_OUT_STATUS_LEN 64 644 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0 645 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4 646 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8 647 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12 648 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16 649 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20 650 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24 651 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28 652 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32 653 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36 654 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40 655 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44 656 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48 657 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52 658 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56 659 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60 660 661 /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */ 662 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20 663 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240 664 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num)) 665 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0 666 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20 667 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1 668 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12 669 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0 670 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4 671 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8 672 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12 673 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16 674 675 /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */ 676 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8 677 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0 678 #define MC_CMD_PTP_MANF_SUCCESS 0x0 /* enum */ 679 #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1 /* enum */ 680 #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2 /* enum */ 681 #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3 /* enum */ 682 #define MC_CMD_PTP_MANF_OSCILLATOR 0x4 /* enum */ 683 #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5 /* enum */ 684 #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6 /* enum */ 685 #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7 /* enum */ 686 #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8 /* enum */ 687 #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9 /* enum */ 688 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4 689 690 /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */ 691 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12 692 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0 693 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4 694 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8 695 696 697 /***********************************/ 698 /* MC_CMD_CSR_READ32 699 * Read 32bit words from the indirect memory map. 700 */ 701 #define MC_CMD_CSR_READ32 0xc 702 703 /* MC_CMD_CSR_READ32_IN msgrequest */ 704 #define MC_CMD_CSR_READ32_IN_LEN 12 705 #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0 706 #define MC_CMD_CSR_READ32_IN_STEP_OFST 4 707 #define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8 708 709 /* MC_CMD_CSR_READ32_OUT msgresponse */ 710 #define MC_CMD_CSR_READ32_OUT_LENMIN 4 711 #define MC_CMD_CSR_READ32_OUT_LENMAX 252 712 #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num)) 713 #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0 714 #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4 715 #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1 716 #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63 717 718 719 /***********************************/ 720 /* MC_CMD_CSR_WRITE32 721 * Write 32bit dwords to the indirect memory map. 722 */ 723 #define MC_CMD_CSR_WRITE32 0xd 724 725 /* MC_CMD_CSR_WRITE32_IN msgrequest */ 726 #define MC_CMD_CSR_WRITE32_IN_LENMIN 12 727 #define MC_CMD_CSR_WRITE32_IN_LENMAX 252 728 #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num)) 729 #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0 730 #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4 731 #define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8 732 #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4 733 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1 734 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61 735 736 /* MC_CMD_CSR_WRITE32_OUT msgresponse */ 737 #define MC_CMD_CSR_WRITE32_OUT_LEN 4 738 #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0 739 740 741 /***********************************/ 742 /* MC_CMD_STACKINFO 743 * Get stack information. 744 */ 745 #define MC_CMD_STACKINFO 0xf 746 747 /* MC_CMD_STACKINFO_IN msgrequest */ 748 #define MC_CMD_STACKINFO_IN_LEN 0 749 750 /* MC_CMD_STACKINFO_OUT msgresponse */ 751 #define MC_CMD_STACKINFO_OUT_LENMIN 12 752 #define MC_CMD_STACKINFO_OUT_LENMAX 252 753 #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num)) 754 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0 755 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12 756 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1 757 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21 758 759 760 /***********************************/ 761 /* MC_CMD_MDIO_READ 762 * MDIO register read. 763 */ 764 #define MC_CMD_MDIO_READ 0x10 765 766 /* MC_CMD_MDIO_READ_IN msgrequest */ 767 #define MC_CMD_MDIO_READ_IN_LEN 16 768 #define MC_CMD_MDIO_READ_IN_BUS_OFST 0 769 #define MC_CMD_MDIO_BUS_INTERNAL 0x0 /* enum */ 770 #define MC_CMD_MDIO_BUS_EXTERNAL 0x1 /* enum */ 771 #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4 772 #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8 773 #define MC_CMD_MDIO_CLAUSE22 0x20 /* enum */ 774 #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12 775 776 /* MC_CMD_MDIO_READ_OUT msgresponse */ 777 #define MC_CMD_MDIO_READ_OUT_LEN 8 778 #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0 779 #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4 780 #define MC_CMD_MDIO_STATUS_GOOD 0x8 /* enum */ 781 782 783 /***********************************/ 784 /* MC_CMD_MDIO_WRITE 785 * MDIO register write. 786 */ 787 #define MC_CMD_MDIO_WRITE 0x11 788 789 /* MC_CMD_MDIO_WRITE_IN msgrequest */ 790 #define MC_CMD_MDIO_WRITE_IN_LEN 20 791 #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0 792 /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */ 793 /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */ 794 #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4 795 #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8 796 /* MC_CMD_MDIO_CLAUSE22 0x20 */ 797 #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12 798 #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16 799 800 /* MC_CMD_MDIO_WRITE_OUT msgresponse */ 801 #define MC_CMD_MDIO_WRITE_OUT_LEN 4 802 #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0 803 /* MC_CMD_MDIO_STATUS_GOOD 0x8 */ 804 805 806 /***********************************/ 807 /* MC_CMD_DBI_WRITE 808 * Write DBI register(s). 809 */ 810 #define MC_CMD_DBI_WRITE 0x12 811 812 /* MC_CMD_DBI_WRITE_IN msgrequest */ 813 #define MC_CMD_DBI_WRITE_IN_LENMIN 12 814 #define MC_CMD_DBI_WRITE_IN_LENMAX 252 815 #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num)) 816 #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0 817 #define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12 818 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1 819 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21 820 821 /* MC_CMD_DBI_WRITE_OUT msgresponse */ 822 #define MC_CMD_DBI_WRITE_OUT_LEN 0 823 824 /* MC_CMD_DBIWROP_TYPEDEF structuredef */ 825 #define MC_CMD_DBIWROP_TYPEDEF_LEN 12 826 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0 827 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0 828 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32 829 #define MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST 4 830 #define MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_LBN 32 831 #define MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_WIDTH 32 832 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8 833 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64 834 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32 835 836 837 /***********************************/ 838 /* MC_CMD_PORT_READ32 839 * Read a 32-bit register from the indirect port register map. 840 */ 841 #define MC_CMD_PORT_READ32 0x14 842 843 /* MC_CMD_PORT_READ32_IN msgrequest */ 844 #define MC_CMD_PORT_READ32_IN_LEN 4 845 #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0 846 847 /* MC_CMD_PORT_READ32_OUT msgresponse */ 848 #define MC_CMD_PORT_READ32_OUT_LEN 8 849 #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0 850 #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4 851 852 853 /***********************************/ 854 /* MC_CMD_PORT_WRITE32 855 * Write a 32-bit register to the indirect port register map. 856 */ 857 #define MC_CMD_PORT_WRITE32 0x15 858 859 /* MC_CMD_PORT_WRITE32_IN msgrequest */ 860 #define MC_CMD_PORT_WRITE32_IN_LEN 8 861 #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0 862 #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4 863 864 /* MC_CMD_PORT_WRITE32_OUT msgresponse */ 865 #define MC_CMD_PORT_WRITE32_OUT_LEN 4 866 #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0 867 868 869 /***********************************/ 870 /* MC_CMD_PORT_READ128 871 * Read a 128-bit register from the indirect port register map. 872 */ 873 #define MC_CMD_PORT_READ128 0x16 874 875 /* MC_CMD_PORT_READ128_IN msgrequest */ 876 #define MC_CMD_PORT_READ128_IN_LEN 4 877 #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0 878 879 /* MC_CMD_PORT_READ128_OUT msgresponse */ 880 #define MC_CMD_PORT_READ128_OUT_LEN 20 881 #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0 882 #define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16 883 #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16 884 885 886 /***********************************/ 887 /* MC_CMD_PORT_WRITE128 888 * Write a 128-bit register to the indirect port register map. 889 */ 890 #define MC_CMD_PORT_WRITE128 0x17 891 892 /* MC_CMD_PORT_WRITE128_IN msgrequest */ 893 #define MC_CMD_PORT_WRITE128_IN_LEN 20 894 #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0 895 #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4 896 #define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16 897 898 /* MC_CMD_PORT_WRITE128_OUT msgresponse */ 899 #define MC_CMD_PORT_WRITE128_OUT_LEN 4 900 #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0 901 902 903 /***********************************/ 904 /* MC_CMD_GET_BOARD_CFG 905 * Returns the MC firmware configuration structure. 906 */ 907 #define MC_CMD_GET_BOARD_CFG 0x18 908 909 /* MC_CMD_GET_BOARD_CFG_IN msgrequest */ 910 #define MC_CMD_GET_BOARD_CFG_IN_LEN 0 911 912 /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */ 913 #define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96 914 #define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136 915 #define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num)) 916 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0 917 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4 918 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32 919 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36 920 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0x0 /* enum */ 921 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 0x1 /* enum */ 922 #define MC_CMD_CAPABILITIES_TURBO_LBN 0x1 /* enum */ 923 #define MC_CMD_CAPABILITIES_TURBO_WIDTH 0x1 /* enum */ 924 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 0x2 /* enum */ 925 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 0x1 /* enum */ 926 #define MC_CMD_CAPABILITIES_PTP_LBN 0x3 /* enum */ 927 #define MC_CMD_CAPABILITIES_PTP_WIDTH 0x1 /* enum */ 928 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40 929 /* Enum values, see field(s): */ 930 /* CAPABILITIES_PORT0 */ 931 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44 932 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6 933 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50 934 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6 935 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56 936 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60 937 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64 938 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68 939 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72 940 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2 941 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12 942 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32 943 944 945 /***********************************/ 946 /* MC_CMD_DBI_READX 947 * Read DBI register(s). 948 */ 949 #define MC_CMD_DBI_READX 0x19 950 951 /* MC_CMD_DBI_READX_IN msgrequest */ 952 #define MC_CMD_DBI_READX_IN_LENMIN 8 953 #define MC_CMD_DBI_READX_IN_LENMAX 248 954 #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num)) 955 #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0 956 #define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8 957 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0 958 #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4 959 #define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1 960 #define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31 961 962 /* MC_CMD_DBI_READX_OUT msgresponse */ 963 #define MC_CMD_DBI_READX_OUT_LENMIN 4 964 #define MC_CMD_DBI_READX_OUT_LENMAX 252 965 #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num)) 966 #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0 967 #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4 968 #define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1 969 #define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63 970 971 972 /***********************************/ 973 /* MC_CMD_SET_RAND_SEED 974 * Set the 16byte seed for the MC pseudo-random generator. 975 */ 976 #define MC_CMD_SET_RAND_SEED 0x1a 977 978 /* MC_CMD_SET_RAND_SEED_IN msgrequest */ 979 #define MC_CMD_SET_RAND_SEED_IN_LEN 16 980 #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0 981 #define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16 982 983 /* MC_CMD_SET_RAND_SEED_OUT msgresponse */ 984 #define MC_CMD_SET_RAND_SEED_OUT_LEN 0 985 986 987 /***********************************/ 988 /* MC_CMD_LTSSM_HIST 989 * Retrieve the history of the PCIE LTSSM. 990 */ 991 #define MC_CMD_LTSSM_HIST 0x1b 992 993 /* MC_CMD_LTSSM_HIST_IN msgrequest */ 994 #define MC_CMD_LTSSM_HIST_IN_LEN 0 995 996 /* MC_CMD_LTSSM_HIST_OUT msgresponse */ 997 #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0 998 #define MC_CMD_LTSSM_HIST_OUT_LENMAX 252 999 #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num)) 1000 #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0 1001 #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4 1002 #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0 1003 #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63 1004 1005 1006 /***********************************/ 1007 /* MC_CMD_DRV_ATTACH 1008 * Inform MCPU that this port is managed on the host. 1009 */ 1010 #define MC_CMD_DRV_ATTACH 0x1c 1011 1012 /* MC_CMD_DRV_ATTACH_IN msgrequest */ 1013 #define MC_CMD_DRV_ATTACH_IN_LEN 8 1014 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0 1015 #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4 1016 1017 /* MC_CMD_DRV_ATTACH_OUT msgresponse */ 1018 #define MC_CMD_DRV_ATTACH_OUT_LEN 4 1019 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0 1020 1021 1022 /***********************************/ 1023 /* MC_CMD_NCSI_PROD 1024 * Trigger an NC-SI event. 1025 */ 1026 #define MC_CMD_NCSI_PROD 0x1d 1027 1028 /* MC_CMD_NCSI_PROD_IN msgrequest */ 1029 #define MC_CMD_NCSI_PROD_IN_LEN 4 1030 #define MC_CMD_NCSI_PROD_IN_EVENTS_OFST 0 1031 #define MC_CMD_NCSI_PROD_LINKCHANGE 0x0 /* enum */ 1032 #define MC_CMD_NCSI_PROD_RESET 0x1 /* enum */ 1033 #define MC_CMD_NCSI_PROD_DRVATTACH 0x2 /* enum */ 1034 #define MC_CMD_NCSI_PROD_IN_LINKCHANGE_LBN 0 1035 #define MC_CMD_NCSI_PROD_IN_LINKCHANGE_WIDTH 1 1036 #define MC_CMD_NCSI_PROD_IN_RESET_LBN 1 1037 #define MC_CMD_NCSI_PROD_IN_RESET_WIDTH 1 1038 #define MC_CMD_NCSI_PROD_IN_DRVATTACH_LBN 2 1039 #define MC_CMD_NCSI_PROD_IN_DRVATTACH_WIDTH 1 1040 1041 /* MC_CMD_NCSI_PROD_OUT msgresponse */ 1042 #define MC_CMD_NCSI_PROD_OUT_LEN 0 1043 1044 1045 /***********************************/ 1046 /* MC_CMD_SHMUART 1047 * Route UART output to circular buffer in shared memory instead. 1048 */ 1049 #define MC_CMD_SHMUART 0x1f 1050 1051 /* MC_CMD_SHMUART_IN msgrequest */ 1052 #define MC_CMD_SHMUART_IN_LEN 4 1053 #define MC_CMD_SHMUART_IN_FLAG_OFST 0 1054 1055 /* MC_CMD_SHMUART_OUT msgresponse */ 1056 #define MC_CMD_SHMUART_OUT_LEN 0 1057 1058 1059 /***********************************/ 1060 /* MC_CMD_ENTITY_RESET 1061 * Generic per-port reset. 1062 */ 1063 #define MC_CMD_ENTITY_RESET 0x20 1064 1065 /* MC_CMD_ENTITY_RESET_IN msgrequest */ 1066 #define MC_CMD_ENTITY_RESET_IN_LEN 4 1067 #define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0 1068 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0 1069 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1 1070 1071 /* MC_CMD_ENTITY_RESET_OUT msgresponse */ 1072 #define MC_CMD_ENTITY_RESET_OUT_LEN 0 1073 1074 1075 /***********************************/ 1076 /* MC_CMD_PCIE_CREDITS 1077 * Read instantaneous and minimum flow control thresholds. 1078 */ 1079 #define MC_CMD_PCIE_CREDITS 0x21 1080 1081 /* MC_CMD_PCIE_CREDITS_IN msgrequest */ 1082 #define MC_CMD_PCIE_CREDITS_IN_LEN 8 1083 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0 1084 #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4 1085 1086 /* MC_CMD_PCIE_CREDITS_OUT msgresponse */ 1087 #define MC_CMD_PCIE_CREDITS_OUT_LEN 16 1088 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0 1089 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2 1090 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2 1091 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2 1092 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4 1093 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2 1094 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6 1095 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2 1096 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8 1097 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2 1098 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10 1099 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2 1100 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12 1101 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2 1102 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14 1103 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2 1104 1105 1106 /***********************************/ 1107 /* MC_CMD_RXD_MONITOR 1108 * Get histogram of RX queue fill level. 1109 */ 1110 #define MC_CMD_RXD_MONITOR 0x22 1111 1112 /* MC_CMD_RXD_MONITOR_IN msgrequest */ 1113 #define MC_CMD_RXD_MONITOR_IN_LEN 12 1114 #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0 1115 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4 1116 #define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8 1117 1118 /* MC_CMD_RXD_MONITOR_OUT msgresponse */ 1119 #define MC_CMD_RXD_MONITOR_OUT_LEN 80 1120 #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0 1121 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4 1122 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8 1123 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12 1124 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16 1125 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20 1126 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24 1127 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28 1128 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32 1129 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36 1130 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40 1131 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44 1132 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48 1133 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52 1134 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56 1135 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60 1136 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64 1137 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68 1138 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72 1139 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76 1140 1141 1142 /***********************************/ 1143 /* MC_CMD_PUTS 1144 * puts(3) implementation over MCDI 1145 */ 1146 #define MC_CMD_PUTS 0x23 1147 1148 /* MC_CMD_PUTS_IN msgrequest */ 1149 #define MC_CMD_PUTS_IN_LENMIN 13 1150 #define MC_CMD_PUTS_IN_LENMAX 252 1151 #define MC_CMD_PUTS_IN_LEN(num) (12+1*(num)) 1152 #define MC_CMD_PUTS_IN_DEST_OFST 0 1153 #define MC_CMD_PUTS_IN_UART_LBN 0 1154 #define MC_CMD_PUTS_IN_UART_WIDTH 1 1155 #define MC_CMD_PUTS_IN_PORT_LBN 1 1156 #define MC_CMD_PUTS_IN_PORT_WIDTH 1 1157 #define MC_CMD_PUTS_IN_DHOST_OFST 4 1158 #define MC_CMD_PUTS_IN_DHOST_LEN 6 1159 #define MC_CMD_PUTS_IN_STRING_OFST 12 1160 #define MC_CMD_PUTS_IN_STRING_LEN 1 1161 #define MC_CMD_PUTS_IN_STRING_MINNUM 1 1162 #define MC_CMD_PUTS_IN_STRING_MAXNUM 240 1163 1164 /* MC_CMD_PUTS_OUT msgresponse */ 1165 #define MC_CMD_PUTS_OUT_LEN 0 1166 1167 1168 /***********************************/ 1169 /* MC_CMD_GET_PHY_CFG 1170 * Report PHY configuration. 1171 */ 1172 #define MC_CMD_GET_PHY_CFG 0x24 1173 1174 /* MC_CMD_GET_PHY_CFG_IN msgrequest */ 1175 #define MC_CMD_GET_PHY_CFG_IN_LEN 0 1176 1177 /* MC_CMD_GET_PHY_CFG_OUT msgresponse */ 1178 #define MC_CMD_GET_PHY_CFG_OUT_LEN 72 1179 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0 1180 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0 1181 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1 1182 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1 1183 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1 1184 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2 1185 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1 1186 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3 1187 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1 1188 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4 1189 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1 1190 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5 1191 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1 1192 #define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6 1193 #define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1 1194 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4 1195 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8 1196 #define MC_CMD_PHY_CAP_10HDX_LBN 1 1197 #define MC_CMD_PHY_CAP_10HDX_WIDTH 1 1198 #define MC_CMD_PHY_CAP_10FDX_LBN 2 1199 #define MC_CMD_PHY_CAP_10FDX_WIDTH 1 1200 #define MC_CMD_PHY_CAP_100HDX_LBN 3 1201 #define MC_CMD_PHY_CAP_100HDX_WIDTH 1 1202 #define MC_CMD_PHY_CAP_100FDX_LBN 4 1203 #define MC_CMD_PHY_CAP_100FDX_WIDTH 1 1204 #define MC_CMD_PHY_CAP_1000HDX_LBN 5 1205 #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1 1206 #define MC_CMD_PHY_CAP_1000FDX_LBN 6 1207 #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1 1208 #define MC_CMD_PHY_CAP_10000FDX_LBN 7 1209 #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1 1210 #define MC_CMD_PHY_CAP_PAUSE_LBN 8 1211 #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1 1212 #define MC_CMD_PHY_CAP_ASYM_LBN 9 1213 #define MC_CMD_PHY_CAP_ASYM_WIDTH 1 1214 #define MC_CMD_PHY_CAP_AN_LBN 10 1215 #define MC_CMD_PHY_CAP_AN_WIDTH 1 1216 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12 1217 #define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16 1218 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20 1219 #define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24 1220 #define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20 1221 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44 1222 #define MC_CMD_MEDIA_XAUI 0x1 /* enum */ 1223 #define MC_CMD_MEDIA_CX4 0x2 /* enum */ 1224 #define MC_CMD_MEDIA_KX4 0x3 /* enum */ 1225 #define MC_CMD_MEDIA_XFP 0x4 /* enum */ 1226 #define MC_CMD_MEDIA_SFP_PLUS 0x5 /* enum */ 1227 #define MC_CMD_MEDIA_BASE_T 0x6 /* enum */ 1228 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48 1229 #define MC_CMD_MMD_CLAUSE22 0x0 /* enum */ 1230 #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */ 1231 #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */ 1232 #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */ 1233 #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */ 1234 #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */ 1235 #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */ 1236 #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */ 1237 #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d /* enum */ 1238 #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */ 1239 #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */ 1240 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52 1241 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20 1242 1243 1244 /***********************************/ 1245 /* MC_CMD_START_BIST 1246 * Start a BIST test on the PHY. 1247 */ 1248 #define MC_CMD_START_BIST 0x25 1249 1250 /* MC_CMD_START_BIST_IN msgrequest */ 1251 #define MC_CMD_START_BIST_IN_LEN 4 1252 #define MC_CMD_START_BIST_IN_TYPE_OFST 0 1253 #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1 /* enum */ 1254 #define MC_CMD_PHY_BIST_CABLE_LONG 0x2 /* enum */ 1255 #define MC_CMD_BPX_SERDES_BIST 0x3 /* enum */ 1256 #define MC_CMD_MC_LOOPBACK_BIST 0x4 /* enum */ 1257 #define MC_CMD_PHY_BIST 0x5 /* enum */ 1258 1259 /* MC_CMD_START_BIST_OUT msgresponse */ 1260 #define MC_CMD_START_BIST_OUT_LEN 0 1261 1262 1263 /***********************************/ 1264 /* MC_CMD_POLL_BIST 1265 * Poll for BIST completion. 1266 */ 1267 #define MC_CMD_POLL_BIST 0x26 1268 1269 /* MC_CMD_POLL_BIST_IN msgrequest */ 1270 #define MC_CMD_POLL_BIST_IN_LEN 0 1271 1272 /* MC_CMD_POLL_BIST_OUT msgresponse */ 1273 #define MC_CMD_POLL_BIST_OUT_LEN 8 1274 #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 1275 #define MC_CMD_POLL_BIST_RUNNING 0x1 /* enum */ 1276 #define MC_CMD_POLL_BIST_PASSED 0x2 /* enum */ 1277 #define MC_CMD_POLL_BIST_FAILED 0x3 /* enum */ 1278 #define MC_CMD_POLL_BIST_TIMEOUT 0x4 /* enum */ 1279 #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4 1280 1281 /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */ 1282 #define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36 1283 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 1284 /* Enum values, see field(s): */ 1285 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 1286 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4 1287 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8 1288 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12 1289 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16 1290 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20 1291 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1 /* enum */ 1292 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2 /* enum */ 1293 #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3 /* enum */ 1294 #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4 /* enum */ 1295 #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9 /* enum */ 1296 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24 1297 /* Enum values, see field(s): */ 1298 /* CABLE_STATUS_A */ 1299 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28 1300 /* Enum values, see field(s): */ 1301 /* CABLE_STATUS_A */ 1302 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32 1303 /* Enum values, see field(s): */ 1304 /* CABLE_STATUS_A */ 1305 1306 /* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */ 1307 #define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8 1308 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 1309 /* Enum values, see field(s): */ 1310 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 1311 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4 1312 #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0 /* enum */ 1313 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1 /* enum */ 1314 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2 /* enum */ 1315 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3 /* enum */ 1316 #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4 /* enum */ 1317 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5 /* enum */ 1318 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6 /* enum */ 1319 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7 /* enum */ 1320 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8 /* enum */ 1321 1322 1323 /***********************************/ 1324 /* MC_CMD_FLUSH_RX_QUEUES 1325 * Flush receive queue(s). 1326 */ 1327 #define MC_CMD_FLUSH_RX_QUEUES 0x27 1328 1329 /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */ 1330 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4 1331 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252 1332 #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num)) 1333 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0 1334 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4 1335 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1 1336 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63 1337 1338 /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */ 1339 #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0 1340 1341 1342 /***********************************/ 1343 /* MC_CMD_GET_LOOPBACK_MODES 1344 * Get port's loopback modes. 1345 */ 1346 #define MC_CMD_GET_LOOPBACK_MODES 0x28 1347 1348 /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */ 1349 #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0 1350 1351 /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */ 1352 #define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 32 1353 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0 1354 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8 1355 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0 1356 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4 1357 #define MC_CMD_LOOPBACK_NONE 0x0 /* enum */ 1358 #define MC_CMD_LOOPBACK_DATA 0x1 /* enum */ 1359 #define MC_CMD_LOOPBACK_GMAC 0x2 /* enum */ 1360 #define MC_CMD_LOOPBACK_XGMII 0x3 /* enum */ 1361 #define MC_CMD_LOOPBACK_XGXS 0x4 /* enum */ 1362 #define MC_CMD_LOOPBACK_XAUI 0x5 /* enum */ 1363 #define MC_CMD_LOOPBACK_GMII 0x6 /* enum */ 1364 #define MC_CMD_LOOPBACK_SGMII 0x7 /* enum */ 1365 #define MC_CMD_LOOPBACK_XGBR 0x8 /* enum */ 1366 #define MC_CMD_LOOPBACK_XFI 0x9 /* enum */ 1367 #define MC_CMD_LOOPBACK_XAUI_FAR 0xa /* enum */ 1368 #define MC_CMD_LOOPBACK_GMII_FAR 0xb /* enum */ 1369 #define MC_CMD_LOOPBACK_SGMII_FAR 0xc /* enum */ 1370 #define MC_CMD_LOOPBACK_XFI_FAR 0xd /* enum */ 1371 #define MC_CMD_LOOPBACK_GPHY 0xe /* enum */ 1372 #define MC_CMD_LOOPBACK_PHYXS 0xf /* enum */ 1373 #define MC_CMD_LOOPBACK_PCS 0x10 /* enum */ 1374 #define MC_CMD_LOOPBACK_PMAPMD 0x11 /* enum */ 1375 #define MC_CMD_LOOPBACK_XPORT 0x12 /* enum */ 1376 #define MC_CMD_LOOPBACK_XGMII_WS 0x13 /* enum */ 1377 #define MC_CMD_LOOPBACK_XAUI_WS 0x14 /* enum */ 1378 #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 /* enum */ 1379 #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 /* enum */ 1380 #define MC_CMD_LOOPBACK_GMII_WS 0x17 /* enum */ 1381 #define MC_CMD_LOOPBACK_XFI_WS 0x18 /* enum */ 1382 #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 /* enum */ 1383 #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a /* enum */ 1384 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8 1385 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8 1386 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8 1387 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12 1388 /* Enum values, see field(s): */ 1389 /* 100M */ 1390 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16 1391 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8 1392 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16 1393 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20 1394 /* Enum values, see field(s): */ 1395 /* 100M */ 1396 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24 1397 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8 1398 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24 1399 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28 1400 /* Enum values, see field(s): */ 1401 /* 100M */ 1402 1403 1404 /***********************************/ 1405 /* MC_CMD_GET_LINK 1406 * Read the unified MAC/PHY link state. 1407 */ 1408 #define MC_CMD_GET_LINK 0x29 1409 1410 /* MC_CMD_GET_LINK_IN msgrequest */ 1411 #define MC_CMD_GET_LINK_IN_LEN 0 1412 1413 /* MC_CMD_GET_LINK_OUT msgresponse */ 1414 #define MC_CMD_GET_LINK_OUT_LEN 28 1415 #define MC_CMD_GET_LINK_OUT_CAP_OFST 0 1416 #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4 1417 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8 1418 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12 1419 /* Enum values, see field(s): */ 1420 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 1421 #define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16 1422 #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0 1423 #define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1 1424 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1 1425 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1 1426 #define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2 1427 #define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1 1428 #define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3 1429 #define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1 1430 #define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20 1431 #define MC_CMD_FCNTL_OFF 0x0 /* enum */ 1432 #define MC_CMD_FCNTL_RESPOND 0x1 /* enum */ 1433 #define MC_CMD_FCNTL_BIDIR 0x2 /* enum */ 1434 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24 1435 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 1436 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 1437 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 1438 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 1439 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 1440 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 1441 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 1442 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 1443 1444 1445 /***********************************/ 1446 /* MC_CMD_SET_LINK 1447 * Write the unified MAC/PHY link configuration. 1448 */ 1449 #define MC_CMD_SET_LINK 0x2a 1450 1451 /* MC_CMD_SET_LINK_IN msgrequest */ 1452 #define MC_CMD_SET_LINK_IN_LEN 16 1453 #define MC_CMD_SET_LINK_IN_CAP_OFST 0 1454 #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4 1455 #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0 1456 #define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1 1457 #define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1 1458 #define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1 1459 #define MC_CMD_SET_LINK_IN_TXDIS_LBN 2 1460 #define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1 1461 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8 1462 /* Enum values, see field(s): */ 1463 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 1464 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12 1465 1466 /* MC_CMD_SET_LINK_OUT msgresponse */ 1467 #define MC_CMD_SET_LINK_OUT_LEN 0 1468 1469 1470 /***********************************/ 1471 /* MC_CMD_SET_ID_LED 1472 * Set indentification LED state. 1473 */ 1474 #define MC_CMD_SET_ID_LED 0x2b 1475 1476 /* MC_CMD_SET_ID_LED_IN msgrequest */ 1477 #define MC_CMD_SET_ID_LED_IN_LEN 4 1478 #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0 1479 #define MC_CMD_LED_OFF 0x0 /* enum */ 1480 #define MC_CMD_LED_ON 0x1 /* enum */ 1481 #define MC_CMD_LED_DEFAULT 0x2 /* enum */ 1482 1483 /* MC_CMD_SET_ID_LED_OUT msgresponse */ 1484 #define MC_CMD_SET_ID_LED_OUT_LEN 0 1485 1486 1487 /***********************************/ 1488 /* MC_CMD_SET_MAC 1489 * Set MAC configuration. 1490 */ 1491 #define MC_CMD_SET_MAC 0x2c 1492 1493 /* MC_CMD_SET_MAC_IN msgrequest */ 1494 #define MC_CMD_SET_MAC_IN_LEN 24 1495 #define MC_CMD_SET_MAC_IN_MTU_OFST 0 1496 #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4 1497 #define MC_CMD_SET_MAC_IN_ADDR_OFST 8 1498 #define MC_CMD_SET_MAC_IN_ADDR_LEN 8 1499 #define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8 1500 #define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12 1501 #define MC_CMD_SET_MAC_IN_REJECT_OFST 16 1502 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0 1503 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1 1504 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1 1505 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1 1506 #define MC_CMD_SET_MAC_IN_FCNTL_OFST 20 1507 /* MC_CMD_FCNTL_OFF 0x0 */ 1508 /* MC_CMD_FCNTL_RESPOND 0x1 */ 1509 /* MC_CMD_FCNTL_BIDIR 0x2 */ 1510 #define MC_CMD_FCNTL_AUTO 0x3 /* enum */ 1511 1512 /* MC_CMD_SET_MAC_OUT msgresponse */ 1513 #define MC_CMD_SET_MAC_OUT_LEN 0 1514 1515 1516 /***********************************/ 1517 /* MC_CMD_PHY_STATS 1518 * Get generic PHY statistics. 1519 */ 1520 #define MC_CMD_PHY_STATS 0x2d 1521 1522 /* MC_CMD_PHY_STATS_IN msgrequest */ 1523 #define MC_CMD_PHY_STATS_IN_LEN 8 1524 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0 1525 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8 1526 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0 1527 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4 1528 1529 /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */ 1530 #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0 1531 1532 /* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */ 1533 #define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3) 1534 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0 1535 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4 1536 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS 1537 #define MC_CMD_OUI 0x0 /* enum */ 1538 #define MC_CMD_PMA_PMD_LINK_UP 0x1 /* enum */ 1539 #define MC_CMD_PMA_PMD_RX_FAULT 0x2 /* enum */ 1540 #define MC_CMD_PMA_PMD_TX_FAULT 0x3 /* enum */ 1541 #define MC_CMD_PMA_PMD_SIGNAL 0x4 /* enum */ 1542 #define MC_CMD_PMA_PMD_SNR_A 0x5 /* enum */ 1543 #define MC_CMD_PMA_PMD_SNR_B 0x6 /* enum */ 1544 #define MC_CMD_PMA_PMD_SNR_C 0x7 /* enum */ 1545 #define MC_CMD_PMA_PMD_SNR_D 0x8 /* enum */ 1546 #define MC_CMD_PCS_LINK_UP 0x9 /* enum */ 1547 #define MC_CMD_PCS_RX_FAULT 0xa /* enum */ 1548 #define MC_CMD_PCS_TX_FAULT 0xb /* enum */ 1549 #define MC_CMD_PCS_BER 0xc /* enum */ 1550 #define MC_CMD_PCS_BLOCK_ERRORS 0xd /* enum */ 1551 #define MC_CMD_PHYXS_LINK_UP 0xe /* enum */ 1552 #define MC_CMD_PHYXS_RX_FAULT 0xf /* enum */ 1553 #define MC_CMD_PHYXS_TX_FAULT 0x10 /* enum */ 1554 #define MC_CMD_PHYXS_ALIGN 0x11 /* enum */ 1555 #define MC_CMD_PHYXS_SYNC 0x12 /* enum */ 1556 #define MC_CMD_AN_LINK_UP 0x13 /* enum */ 1557 #define MC_CMD_AN_COMPLETE 0x14 /* enum */ 1558 #define MC_CMD_AN_10GBT_STATUS 0x15 /* enum */ 1559 #define MC_CMD_CL22_LINK_UP 0x16 /* enum */ 1560 #define MC_CMD_PHY_NSTATS 0x17 /* enum */ 1561 1562 1563 /***********************************/ 1564 /* MC_CMD_MAC_STATS 1565 * Get generic MAC statistics. 1566 */ 1567 #define MC_CMD_MAC_STATS 0x2e 1568 1569 /* MC_CMD_MAC_STATS_IN msgrequest */ 1570 #define MC_CMD_MAC_STATS_IN_LEN 16 1571 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0 1572 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8 1573 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0 1574 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4 1575 #define MC_CMD_MAC_STATS_IN_CMD_OFST 8 1576 #define MC_CMD_MAC_STATS_IN_DMA_LBN 0 1577 #define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1 1578 #define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1 1579 #define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1 1580 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2 1581 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1 1582 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3 1583 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1 1584 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4 1585 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1 1586 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5 1587 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1 1588 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16 1589 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16 1590 #define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12 1591 1592 /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */ 1593 #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0 1594 1595 /* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */ 1596 #define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) 1597 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0 1598 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8 1599 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0 1600 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4 1601 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS 1602 #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */ 1603 #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */ 1604 #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */ 1605 #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */ 1606 #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */ 1607 #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */ 1608 #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */ 1609 #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */ 1610 #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */ 1611 #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */ 1612 #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */ 1613 #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */ 1614 #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */ 1615 #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */ 1616 #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */ 1617 #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */ 1618 #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */ 1619 #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */ 1620 #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */ 1621 #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */ 1622 #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */ 1623 #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */ 1624 #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */ 1625 #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */ 1626 #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */ 1627 #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */ 1628 #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */ 1629 #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */ 1630 #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */ 1631 #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */ 1632 #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */ 1633 #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */ 1634 #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */ 1635 #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */ 1636 #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */ 1637 #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */ 1638 #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */ 1639 #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */ 1640 #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */ 1641 #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */ 1642 #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */ 1643 #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */ 1644 #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */ 1645 #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */ 1646 #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */ 1647 #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */ 1648 #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */ 1649 #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */ 1650 #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */ 1651 #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */ 1652 #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */ 1653 #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */ 1654 #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */ 1655 #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */ 1656 #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */ 1657 #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */ 1658 #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */ 1659 #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */ 1660 #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */ 1661 #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */ 1662 #define MC_CMD_GMAC_DMABUF_START 0x40 /* enum */ 1663 #define MC_CMD_GMAC_DMABUF_END 0x5f /* enum */ 1664 #define MC_CMD_MAC_GENERATION_END 0x60 /* enum */ 1665 #define MC_CMD_MAC_NSTATS 0x61 /* enum */ 1666 1667 1668 /***********************************/ 1669 /* MC_CMD_SRIOV 1670 * to be documented 1671 */ 1672 #define MC_CMD_SRIOV 0x30 1673 1674 /* MC_CMD_SRIOV_IN msgrequest */ 1675 #define MC_CMD_SRIOV_IN_LEN 12 1676 #define MC_CMD_SRIOV_IN_ENABLE_OFST 0 1677 #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4 1678 #define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8 1679 1680 /* MC_CMD_SRIOV_OUT msgresponse */ 1681 #define MC_CMD_SRIOV_OUT_LEN 8 1682 #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0 1683 #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4 1684 1685 /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */ 1686 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32 1687 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0 1688 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0 1689 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32 1690 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4 1691 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32 1692 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32 1693 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8 1694 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8 1695 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8 1696 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12 1697 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64 1698 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64 1699 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16 1700 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */ 1701 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128 1702 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32 1703 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20 1704 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8 1705 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20 1706 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24 1707 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160 1708 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64 1709 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28 1710 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224 1711 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32 1712 1713 1714 /***********************************/ 1715 /* MC_CMD_MEMCPY 1716 * Perform memory copy operation. 1717 */ 1718 #define MC_CMD_MEMCPY 0x31 1719 1720 /* MC_CMD_MEMCPY_IN msgrequest */ 1721 #define MC_CMD_MEMCPY_IN_LENMIN 32 1722 #define MC_CMD_MEMCPY_IN_LENMAX 224 1723 #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num)) 1724 #define MC_CMD_MEMCPY_IN_RECORD_OFST 0 1725 #define MC_CMD_MEMCPY_IN_RECORD_LEN 32 1726 #define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1 1727 #define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7 1728 1729 /* MC_CMD_MEMCPY_OUT msgresponse */ 1730 #define MC_CMD_MEMCPY_OUT_LEN 0 1731 1732 1733 /***********************************/ 1734 /* MC_CMD_WOL_FILTER_SET 1735 * Set a WoL filter. 1736 */ 1737 #define MC_CMD_WOL_FILTER_SET 0x32 1738 1739 /* MC_CMD_WOL_FILTER_SET_IN msgrequest */ 1740 #define MC_CMD_WOL_FILTER_SET_IN_LEN 192 1741 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 1742 #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */ 1743 #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */ 1744 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 1745 #define MC_CMD_WOL_TYPE_MAGIC 0x0 /* enum */ 1746 #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 /* enum */ 1747 #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3 /* enum */ 1748 #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4 /* enum */ 1749 #define MC_CMD_WOL_TYPE_BITMAP 0x5 /* enum */ 1750 #define MC_CMD_WOL_TYPE_LINK 0x6 /* enum */ 1751 #define MC_CMD_WOL_TYPE_MAX 0x7 /* enum */ 1752 #define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8 1753 #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4 1754 #define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46 1755 1756 /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */ 1757 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16 1758 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 1759 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 1760 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8 1761 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8 1762 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8 1763 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12 1764 1765 /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */ 1766 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20 1767 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 1768 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 1769 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8 1770 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12 1771 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16 1772 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2 1773 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18 1774 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2 1775 1776 /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */ 1777 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44 1778 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 1779 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 1780 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8 1781 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16 1782 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24 1783 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16 1784 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40 1785 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2 1786 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42 1787 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2 1788 1789 /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */ 1790 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187 1791 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 1792 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 1793 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8 1794 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48 1795 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56 1796 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128 1797 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184 1798 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1 1799 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185 1800 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1 1801 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186 1802 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1 1803 1804 /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */ 1805 #define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12 1806 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 1807 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 1808 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8 1809 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0 1810 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1 1811 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1 1812 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1 1813 1814 /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */ 1815 #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4 1816 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0 1817 1818 1819 /***********************************/ 1820 /* MC_CMD_WOL_FILTER_REMOVE 1821 * Remove a WoL filter. 1822 */ 1823 #define MC_CMD_WOL_FILTER_REMOVE 0x33 1824 1825 /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */ 1826 #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4 1827 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0 1828 1829 /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */ 1830 #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0 1831 1832 1833 /***********************************/ 1834 /* MC_CMD_WOL_FILTER_RESET 1835 * Reset (i.e. remove all) WoL filters. 1836 */ 1837 #define MC_CMD_WOL_FILTER_RESET 0x34 1838 1839 /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */ 1840 #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4 1841 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0 1842 #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */ 1843 #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */ 1844 1845 /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */ 1846 #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0 1847 1848 1849 /***********************************/ 1850 /* MC_CMD_SET_MCAST_HASH 1851 * Set the MCASH hash value. 1852 */ 1853 #define MC_CMD_SET_MCAST_HASH 0x35 1854 1855 /* MC_CMD_SET_MCAST_HASH_IN msgrequest */ 1856 #define MC_CMD_SET_MCAST_HASH_IN_LEN 32 1857 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0 1858 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16 1859 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16 1860 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16 1861 1862 /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */ 1863 #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0 1864 1865 1866 /***********************************/ 1867 /* MC_CMD_NVRAM_TYPES 1868 * Get virtual NVRAM partitions information. 1869 */ 1870 #define MC_CMD_NVRAM_TYPES 0x36 1871 1872 /* MC_CMD_NVRAM_TYPES_IN msgrequest */ 1873 #define MC_CMD_NVRAM_TYPES_IN_LEN 0 1874 1875 /* MC_CMD_NVRAM_TYPES_OUT msgresponse */ 1876 #define MC_CMD_NVRAM_TYPES_OUT_LEN 4 1877 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0 1878 #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0 /* enum */ 1879 #define MC_CMD_NVRAM_TYPE_MC_FW 0x1 /* enum */ 1880 #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2 /* enum */ 1881 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3 /* enum */ 1882 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4 /* enum */ 1883 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5 /* enum */ 1884 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6 /* enum */ 1885 #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7 /* enum */ 1886 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8 /* enum */ 1887 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9 /* enum */ 1888 #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa /* enum */ 1889 #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb /* enum */ 1890 #define MC_CMD_NVRAM_TYPE_LOG 0xc /* enum */ 1891 #define MC_CMD_NVRAM_TYPE_FPGA 0xd /* enum */ 1892 1893 1894 /***********************************/ 1895 /* MC_CMD_NVRAM_INFO 1896 * Read info about a virtual NVRAM partition. 1897 */ 1898 #define MC_CMD_NVRAM_INFO 0x37 1899 1900 /* MC_CMD_NVRAM_INFO_IN msgrequest */ 1901 #define MC_CMD_NVRAM_INFO_IN_LEN 4 1902 #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0 1903 /* Enum values, see field(s): */ 1904 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 1905 1906 /* MC_CMD_NVRAM_INFO_OUT msgresponse */ 1907 #define MC_CMD_NVRAM_INFO_OUT_LEN 24 1908 #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0 1909 /* Enum values, see field(s): */ 1910 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 1911 #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4 1912 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8 1913 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12 1914 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0 1915 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1 1916 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16 1917 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20 1918 1919 1920 /***********************************/ 1921 /* MC_CMD_NVRAM_UPDATE_START 1922 * Start a group of update operations on a virtual NVRAM partition. 1923 */ 1924 #define MC_CMD_NVRAM_UPDATE_START 0x38 1925 1926 /* MC_CMD_NVRAM_UPDATE_START_IN msgrequest */ 1927 #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4 1928 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0 1929 /* Enum values, see field(s): */ 1930 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 1931 1932 /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */ 1933 #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0 1934 1935 1936 /***********************************/ 1937 /* MC_CMD_NVRAM_READ 1938 * Read data from a virtual NVRAM partition. 1939 */ 1940 #define MC_CMD_NVRAM_READ 0x39 1941 1942 /* MC_CMD_NVRAM_READ_IN msgrequest */ 1943 #define MC_CMD_NVRAM_READ_IN_LEN 12 1944 #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0 1945 /* Enum values, see field(s): */ 1946 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 1947 #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4 1948 #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8 1949 1950 /* MC_CMD_NVRAM_READ_OUT msgresponse */ 1951 #define MC_CMD_NVRAM_READ_OUT_LENMIN 1 1952 #define MC_CMD_NVRAM_READ_OUT_LENMAX 252 1953 #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num)) 1954 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0 1955 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1 1956 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1 1957 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252 1958 1959 1960 /***********************************/ 1961 /* MC_CMD_NVRAM_WRITE 1962 * Write data to a virtual NVRAM partition. 1963 */ 1964 #define MC_CMD_NVRAM_WRITE 0x3a 1965 1966 /* MC_CMD_NVRAM_WRITE_IN msgrequest */ 1967 #define MC_CMD_NVRAM_WRITE_IN_LENMIN 13 1968 #define MC_CMD_NVRAM_WRITE_IN_LENMAX 252 1969 #define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num)) 1970 #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0 1971 /* Enum values, see field(s): */ 1972 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 1973 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4 1974 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8 1975 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12 1976 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1 1977 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1 1978 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240 1979 1980 /* MC_CMD_NVRAM_WRITE_OUT msgresponse */ 1981 #define MC_CMD_NVRAM_WRITE_OUT_LEN 0 1982 1983 1984 /***********************************/ 1985 /* MC_CMD_NVRAM_ERASE 1986 * Erase sector(s) from a virtual NVRAM partition. 1987 */ 1988 #define MC_CMD_NVRAM_ERASE 0x3b 1989 1990 /* MC_CMD_NVRAM_ERASE_IN msgrequest */ 1991 #define MC_CMD_NVRAM_ERASE_IN_LEN 12 1992 #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0 1993 /* Enum values, see field(s): */ 1994 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 1995 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4 1996 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8 1997 1998 /* MC_CMD_NVRAM_ERASE_OUT msgresponse */ 1999 #define MC_CMD_NVRAM_ERASE_OUT_LEN 0 2000 2001 2002 /***********************************/ 2003 /* MC_CMD_NVRAM_UPDATE_FINISH 2004 * Finish a group of update operations on a virtual NVRAM partition. 2005 */ 2006 #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c 2007 2008 /* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest */ 2009 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8 2010 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0 2011 /* Enum values, see field(s): */ 2012 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 2013 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4 2014 2015 /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse */ 2016 #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0 2017 2018 2019 /***********************************/ 2020 /* MC_CMD_REBOOT 2021 * Reboot the MC. 2022 */ 2023 #define MC_CMD_REBOOT 0x3d 2024 2025 /* MC_CMD_REBOOT_IN msgrequest */ 2026 #define MC_CMD_REBOOT_IN_LEN 4 2027 #define MC_CMD_REBOOT_IN_FLAGS_OFST 0 2028 #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */ 2029 2030 /* MC_CMD_REBOOT_OUT msgresponse */ 2031 #define MC_CMD_REBOOT_OUT_LEN 0 2032 2033 2034 /***********************************/ 2035 /* MC_CMD_SCHEDINFO 2036 * Request scheduler info. 2037 */ 2038 #define MC_CMD_SCHEDINFO 0x3e 2039 2040 /* MC_CMD_SCHEDINFO_IN msgrequest */ 2041 #define MC_CMD_SCHEDINFO_IN_LEN 0 2042 2043 /* MC_CMD_SCHEDINFO_OUT msgresponse */ 2044 #define MC_CMD_SCHEDINFO_OUT_LENMIN 4 2045 #define MC_CMD_SCHEDINFO_OUT_LENMAX 252 2046 #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num)) 2047 #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0 2048 #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4 2049 #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1 2050 #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63 2051 2052 2053 /***********************************/ 2054 /* MC_CMD_REBOOT_MODE 2055 */ 2056 #define MC_CMD_REBOOT_MODE 0x3f 2057 2058 /* MC_CMD_REBOOT_MODE_IN msgrequest */ 2059 #define MC_CMD_REBOOT_MODE_IN_LEN 4 2060 #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0 2061 #define MC_CMD_REBOOT_MODE_NORMAL 0x0 /* enum */ 2062 #define MC_CMD_REBOOT_MODE_SNAPPER 0x3 /* enum */ 2063 2064 /* MC_CMD_REBOOT_MODE_OUT msgresponse */ 2065 #define MC_CMD_REBOOT_MODE_OUT_LEN 4 2066 #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0 2067 2068 2069 /***********************************/ 2070 /* MC_CMD_SENSOR_INFO 2071 * Returns information about every available sensor. 2072 */ 2073 #define MC_CMD_SENSOR_INFO 0x41 2074 2075 /* MC_CMD_SENSOR_INFO_IN msgrequest */ 2076 #define MC_CMD_SENSOR_INFO_IN_LEN 0 2077 2078 /* MC_CMD_SENSOR_INFO_OUT msgresponse */ 2079 #define MC_CMD_SENSOR_INFO_OUT_LENMIN 12 2080 #define MC_CMD_SENSOR_INFO_OUT_LENMAX 252 2081 #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num)) 2082 #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0 2083 #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0 /* enum */ 2084 #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1 /* enum */ 2085 #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2 /* enum */ 2086 #define MC_CMD_SENSOR_PHY0_TEMP 0x3 /* enum */ 2087 #define MC_CMD_SENSOR_PHY0_COOLING 0x4 /* enum */ 2088 #define MC_CMD_SENSOR_PHY1_TEMP 0x5 /* enum */ 2089 #define MC_CMD_SENSOR_PHY1_COOLING 0x6 /* enum */ 2090 #define MC_CMD_SENSOR_IN_1V0 0x7 /* enum */ 2091 #define MC_CMD_SENSOR_IN_1V2 0x8 /* enum */ 2092 #define MC_CMD_SENSOR_IN_1V8 0x9 /* enum */ 2093 #define MC_CMD_SENSOR_IN_2V5 0xa /* enum */ 2094 #define MC_CMD_SENSOR_IN_3V3 0xb /* enum */ 2095 #define MC_CMD_SENSOR_IN_12V0 0xc /* enum */ 2096 #define MC_CMD_SENSOR_IN_1V2A 0xd /* enum */ 2097 #define MC_CMD_SENSOR_IN_VREF 0xe /* enum */ 2098 #define MC_CMD_SENSOR_ENTRY_OFST 4 2099 #define MC_CMD_SENSOR_ENTRY_LEN 8 2100 #define MC_CMD_SENSOR_ENTRY_LO_OFST 4 2101 #define MC_CMD_SENSOR_ENTRY_HI_OFST 8 2102 #define MC_CMD_SENSOR_ENTRY_MINNUM 1 2103 #define MC_CMD_SENSOR_ENTRY_MAXNUM 31 2104 2105 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */ 2106 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8 2107 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0 2108 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2 2109 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0 2110 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16 2111 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2 2112 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2 2113 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16 2114 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16 2115 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4 2116 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2 2117 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32 2118 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16 2119 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6 2120 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2 2121 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48 2122 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16 2123 2124 2125 /***********************************/ 2126 /* MC_CMD_READ_SENSORS 2127 * Returns the current reading from each sensor. 2128 */ 2129 #define MC_CMD_READ_SENSORS 0x42 2130 2131 /* MC_CMD_READ_SENSORS_IN msgrequest */ 2132 #define MC_CMD_READ_SENSORS_IN_LEN 8 2133 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0 2134 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8 2135 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0 2136 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4 2137 2138 /* MC_CMD_READ_SENSORS_OUT msgresponse */ 2139 #define MC_CMD_READ_SENSORS_OUT_LEN 0 2140 2141 /* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */ 2142 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 3 2143 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0 2144 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2 2145 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0 2146 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16 2147 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2 2148 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1 2149 #define MC_CMD_SENSOR_STATE_OK 0x0 /* enum */ 2150 #define MC_CMD_SENSOR_STATE_WARNING 0x1 /* enum */ 2151 #define MC_CMD_SENSOR_STATE_FATAL 0x2 /* enum */ 2152 #define MC_CMD_SENSOR_STATE_BROKEN 0x3 /* enum */ 2153 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16 2154 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8 2155 2156 2157 /***********************************/ 2158 /* MC_CMD_GET_PHY_STATE 2159 * Report current state of PHY. 2160 */ 2161 #define MC_CMD_GET_PHY_STATE 0x43 2162 2163 /* MC_CMD_GET_PHY_STATE_IN msgrequest */ 2164 #define MC_CMD_GET_PHY_STATE_IN_LEN 0 2165 2166 /* MC_CMD_GET_PHY_STATE_OUT msgresponse */ 2167 #define MC_CMD_GET_PHY_STATE_OUT_LEN 4 2168 #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0 2169 #define MC_CMD_PHY_STATE_OK 0x1 /* enum */ 2170 #define MC_CMD_PHY_STATE_ZOMBIE 0x2 /* enum */ 2171 2172 2173 /***********************************/ 2174 /* MC_CMD_SETUP_8021QBB 2175 * 802.1Qbb control. 2176 */ 2177 #define MC_CMD_SETUP_8021QBB 0x44 2178 2179 /* MC_CMD_SETUP_8021QBB_IN msgrequest */ 2180 #define MC_CMD_SETUP_8021QBB_IN_LEN 32 2181 #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0 2182 #define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32 2183 2184 /* MC_CMD_SETUP_8021QBB_OUT msgresponse */ 2185 #define MC_CMD_SETUP_8021QBB_OUT_LEN 0 2186 2187 2188 /***********************************/ 2189 /* MC_CMD_WOL_FILTER_GET 2190 * Retrieve ID of any WoL filters. 2191 */ 2192 #define MC_CMD_WOL_FILTER_GET 0x45 2193 2194 /* MC_CMD_WOL_FILTER_GET_IN msgrequest */ 2195 #define MC_CMD_WOL_FILTER_GET_IN_LEN 0 2196 2197 /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */ 2198 #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4 2199 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0 2200 2201 2202 /***********************************/ 2203 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD 2204 * Add a protocol offload to NIC for lights-out state. 2205 */ 2206 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46 2207 2208 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */ 2209 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8 2210 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252 2211 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num)) 2212 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 2213 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */ 2214 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */ 2215 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4 2216 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4 2217 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1 2218 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62 2219 2220 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */ 2221 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14 2222 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 2223 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4 2224 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6 2225 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10 2226 2227 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */ 2228 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42 2229 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 2230 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4 2231 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6 2232 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10 2233 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16 2234 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26 2235 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16 2236 2237 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 2238 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4 2239 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0 2240 2241 2242 /***********************************/ 2243 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 2244 * Remove a protocol offload from NIC for lights-out state. 2245 */ 2246 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47 2247 2248 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */ 2249 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8 2250 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 2251 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4 2252 2253 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 2254 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0 2255 2256 2257 /***********************************/ 2258 /* MC_CMD_MAC_RESET_RESTORE 2259 * Restore MAC after block reset. 2260 */ 2261 #define MC_CMD_MAC_RESET_RESTORE 0x48 2262 2263 /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */ 2264 #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0 2265 2266 /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */ 2267 #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0 2268 2269 2270 /***********************************/ 2271 /* MC_CMD_TESTASSERT 2272 */ 2273 #define MC_CMD_TESTASSERT 0x49 2274 2275 /* MC_CMD_TESTASSERT_IN msgrequest */ 2276 #define MC_CMD_TESTASSERT_IN_LEN 0 2277 2278 /* MC_CMD_TESTASSERT_OUT msgresponse */ 2279 #define MC_CMD_TESTASSERT_OUT_LEN 0 2280 2281 2282 /***********************************/ 2283 /* MC_CMD_WORKAROUND 2284 * Enable/Disable a given workaround. 2285 */ 2286 #define MC_CMD_WORKAROUND 0x4a 2287 2288 /* MC_CMD_WORKAROUND_IN msgrequest */ 2289 #define MC_CMD_WORKAROUND_IN_LEN 8 2290 #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0 2291 #define MC_CMD_WORKAROUND_BUG17230 0x1 /* enum */ 2292 #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4 2293 2294 /* MC_CMD_WORKAROUND_OUT msgresponse */ 2295 #define MC_CMD_WORKAROUND_OUT_LEN 0 2296 2297 2298 /***********************************/ 2299 /* MC_CMD_GET_PHY_MEDIA_INFO 2300 * Read media-specific data from PHY. 2301 */ 2302 #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b 2303 2304 /* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */ 2305 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4 2306 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0 2307 2308 /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */ 2309 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5 2310 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252 2311 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num)) 2312 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0 2313 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4 2314 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1 2315 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1 2316 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248 2317 2318 2319 /***********************************/ 2320 /* MC_CMD_NVRAM_TEST 2321 * Test a particular NVRAM partition. 2322 */ 2323 #define MC_CMD_NVRAM_TEST 0x4c 2324 2325 /* MC_CMD_NVRAM_TEST_IN msgrequest */ 2326 #define MC_CMD_NVRAM_TEST_IN_LEN 4 2327 #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0 2328 /* Enum values, see field(s): */ 2329 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 2330 2331 /* MC_CMD_NVRAM_TEST_OUT msgresponse */ 2332 #define MC_CMD_NVRAM_TEST_OUT_LEN 4 2333 #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0 2334 #define MC_CMD_NVRAM_TEST_PASS 0x0 /* enum */ 2335 #define MC_CMD_NVRAM_TEST_FAIL 0x1 /* enum */ 2336 #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2 /* enum */ 2337 2338 2339 /***********************************/ 2340 /* MC_CMD_MRSFP_TWEAK 2341 * Read status and/or set parameters for the 'mrsfp' driver. 2342 */ 2343 #define MC_CMD_MRSFP_TWEAK 0x4d 2344 2345 /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */ 2346 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16 2347 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0 2348 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4 2349 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8 2350 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12 2351 2352 /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */ 2353 #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0 2354 2355 /* MC_CMD_MRSFP_TWEAK_OUT msgresponse */ 2356 #define MC_CMD_MRSFP_TWEAK_OUT_LEN 12 2357 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0 2358 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4 2359 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8 2360 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0 /* enum */ 2361 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1 /* enum */ 2362 2363 2364 /***********************************/ 2365 /* MC_CMD_SENSOR_SET_LIMS 2366 * Adjusts the sensor limits. 2367 */ 2368 #define MC_CMD_SENSOR_SET_LIMS 0x4e 2369 2370 /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */ 2371 #define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20 2372 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0 2373 /* Enum values, see field(s): */ 2374 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 2375 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4 2376 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8 2377 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12 2378 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16 2379 2380 /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */ 2381 #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0 2382 2383 2384 /***********************************/ 2385 /* MC_CMD_GET_RESOURCE_LIMITS 2386 */ 2387 #define MC_CMD_GET_RESOURCE_LIMITS 0x4f 2388 2389 /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */ 2390 #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0 2391 2392 /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */ 2393 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16 2394 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0 2395 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4 2396 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8 2397 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12 2398 2399 /* MC_CMD_RESOURCE_SPECIFIER enum */ 2400 #define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff /* enum */ 2401 #define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe /* enum */ 2402 2403 2404 #endif /* MCDI_PCOL_H */ 2405