1 /* 2 * Copyright (c) 2000-2012 LSI Corporation. 3 * 4 * 5 * Name: mpi2.h 6 * Title: MPI Message independent structures and definitions 7 * including System Interface Register Set and 8 * scatter/gather formats. 9 * Creation Date: June 21, 2006 10 * 11 * mpi2.h Version: 02.00.26 12 * 13 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 14 * prefix are for use only on MPI v2.5 products, and must not be used 15 * with MPI v2.0 products. Unless otherwise noted, names beginning with 16 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 17 * 18 * Version History 19 * --------------- 20 * 21 * Date Version Description 22 * -------- -------- ------------------------------------------------------ 23 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 24 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT. 25 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT. 26 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT. 27 * Moved ReplyPostHostIndex register to offset 0x6C of the 28 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for 29 * MPI2_REPLY_POST_HOST_INDEX_OFFSET. 30 * Added union of request descriptors. 31 * Added union of reply descriptors. 32 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT. 33 * Added define for MPI2_VERSION_02_00. 34 * Fixed the size of the FunctionDependent5 field in the 35 * MPI2_DEFAULT_REPLY structure. 36 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT. 37 * Removed the MPI-defined Fault Codes and extended the 38 * product specific codes up to 0xEFFF. 39 * Added a sixth key value for the WriteSequence register 40 * and changed the flush value to 0x0. 41 * Added message function codes for Diagnostic Buffer Post 42 * and Diagnsotic Release. 43 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED 44 * Moved MPI2_VERSION_UNION from mpi2_ioc.h. 45 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT. 46 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT. 47 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT. 48 * Added #defines for marking a reply descriptor as unused. 49 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT. 50 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT. 51 * Moved LUN field defines from mpi2_init.h. 52 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT. 53 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT. 54 * In all request and reply descriptors, replaced VF_ID 55 * field with MSIxIndex field. 56 * Removed DevHandle field from 57 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those 58 * bytes reserved. 59 * Added RAID Accelerator functionality. 60 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT. 61 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT. 62 * Added MSI-x index mask and shift for Reply Post Host 63 * Index register. 64 * Added function code for Host Based Discovery Action. 65 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT. 66 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL. 67 * Added defines for product-specific range of message 68 * function codes, 0xF0 to 0xFF. 69 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT. 70 * Added alternative defines for the SGE Direction bit. 71 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT. 72 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT. 73 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define. 74 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT. 75 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE. 76 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT. 77 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT. 78 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT. 79 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT. 80 * Incorporating additions for MPI v2.5. 81 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT. 82 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT. 83 * Added Hard Reset delay timings. 84 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT. 85 * -------------------------------------------------------------------------- 86 */ 87 88 #ifndef MPI2_H 89 #define MPI2_H 90 91 /***************************************************************************** 92 * 93 * MPI Version Definitions 94 * 95 *****************************************************************************/ 96 97 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 98 #define MPI2_VERSION_MAJOR_SHIFT (8) 99 #define MPI2_VERSION_MINOR_MASK (0x00FF) 100 #define MPI2_VERSION_MINOR_SHIFT (0) 101 102 /*major version for all MPI v2.x */ 103 #define MPI2_VERSION_MAJOR (0x02) 104 105 /*minor version for MPI v2.0 compatible products */ 106 #define MPI2_VERSION_MINOR (0x00) 107 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 108 MPI2_VERSION_MINOR) 109 #define MPI2_VERSION_02_00 (0x0200) 110 111 /*minor version for MPI v2.5 compatible products */ 112 #define MPI25_VERSION_MINOR (0x05) 113 #define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 114 MPI25_VERSION_MINOR) 115 #define MPI2_VERSION_02_05 (0x0205) 116 117 /*Unit and Dev versioning for this MPI header set */ 118 #define MPI2_HEADER_VERSION_UNIT (0x1A) 119 #define MPI2_HEADER_VERSION_DEV (0x00) 120 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 121 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 122 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 123 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 124 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 125 MPI2_HEADER_VERSION_DEV) 126 127 /***************************************************************************** 128 * 129 * IOC State Definitions 130 * 131 *****************************************************************************/ 132 133 #define MPI2_IOC_STATE_RESET (0x00000000) 134 #define MPI2_IOC_STATE_READY (0x10000000) 135 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000) 136 #define MPI2_IOC_STATE_FAULT (0x40000000) 137 138 #define MPI2_IOC_STATE_MASK (0xF0000000) 139 #define MPI2_IOC_STATE_SHIFT (28) 140 141 /*Fault state range for prodcut specific codes */ 142 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000) 143 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF) 144 145 /***************************************************************************** 146 * 147 * System Interface Register Definitions 148 * 149 *****************************************************************************/ 150 151 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS { 152 U32 Doorbell; /*0x00 */ 153 U32 WriteSequence; /*0x04 */ 154 U32 HostDiagnostic; /*0x08 */ 155 U32 Reserved1; /*0x0C */ 156 U32 DiagRWData; /*0x10 */ 157 U32 DiagRWAddressLow; /*0x14 */ 158 U32 DiagRWAddressHigh; /*0x18 */ 159 U32 Reserved2[5]; /*0x1C */ 160 U32 HostInterruptStatus; /*0x30 */ 161 U32 HostInterruptMask; /*0x34 */ 162 U32 DCRData; /*0x38 */ 163 U32 DCRAddress; /*0x3C */ 164 U32 Reserved3[2]; /*0x40 */ 165 U32 ReplyFreeHostIndex; /*0x48 */ 166 U32 Reserved4[8]; /*0x4C */ 167 U32 ReplyPostHostIndex; /*0x6C */ 168 U32 Reserved5; /*0x70 */ 169 U32 HCBSize; /*0x74 */ 170 U32 HCBAddressLow; /*0x78 */ 171 U32 HCBAddressHigh; /*0x7C */ 172 U32 Reserved6[16]; /*0x80 */ 173 U32 RequestDescriptorPostLow; /*0xC0 */ 174 U32 RequestDescriptorPostHigh; /*0xC4 */ 175 U32 Reserved7[14]; /*0xC8 */ 176 } MPI2_SYSTEM_INTERFACE_REGS, 177 *PTR_MPI2_SYSTEM_INTERFACE_REGS, 178 Mpi2SystemInterfaceRegs_t, 179 *pMpi2SystemInterfaceRegs_t; 180 181 /* 182 *Defines for working with the Doorbell register. 183 */ 184 #define MPI2_DOORBELL_OFFSET (0x00000000) 185 186 /*IOC --> System values */ 187 #define MPI2_DOORBELL_USED (0x08000000) 188 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000) 189 #define MPI2_DOORBELL_WHO_INIT_SHIFT (24) 190 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF) 191 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF) 192 193 /*System --> IOC values */ 194 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000) 195 #define MPI2_DOORBELL_FUNCTION_SHIFT (24) 196 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000) 197 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16) 198 199 /* 200 *Defines for the WriteSequence register 201 */ 202 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 203 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F) 204 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 205 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 206 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 207 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 208 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 209 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 210 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 211 212 /* 213 *Defines for the HostDiagnostic register 214 */ 215 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008) 216 217 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800) 218 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000) 219 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800) 220 221 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) 222 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200) 223 #define MPI2_DIAG_HCB_MODE (0x00000100) 224 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080) 225 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040) 226 #define MPI2_DIAG_RESET_HISTORY (0x00000020) 227 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010) 228 #define MPI2_DIAG_RESET_ADAPTER (0x00000004) 229 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002) 230 231 /* 232 *Offsets for DiagRWData and address 233 */ 234 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010) 235 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014) 236 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018) 237 238 /* 239 *Defines for the HostInterruptStatus register 240 */ 241 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030) 242 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000) 243 #define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS 244 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000) 245 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008) 246 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001) 247 #define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS 248 249 /* 250 *Defines for the HostInterruptMask register 251 */ 252 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034) 253 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000) 254 #define MPI2_HIM_REPLY_INT_MASK (0x00000008) 255 #define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK 256 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001) 257 #define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK 258 259 /* 260 *Offsets for DCRData and address 261 */ 262 #define MPI2_DCR_DATA_OFFSET (0x00000038) 263 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C) 264 265 /* 266 *Offset for the Reply Free Queue 267 */ 268 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048) 269 270 /* 271 *Defines for the Reply Descriptor Post Queue 272 */ 273 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 274 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF) 275 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000) 276 #define MPI2_RPHI_MSIX_INDEX_SHIFT (24) 277 278 /* 279 *Defines for the HCBSize and address 280 */ 281 #define MPI2_HCB_SIZE_OFFSET (0x00000074) 282 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000) 283 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001) 284 285 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078) 286 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C) 287 288 /* 289 *Offsets for the Request Queue 290 */ 291 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0) 292 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4) 293 294 /*Hard Reset delay timings */ 295 #define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000) 296 #define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000) 297 #define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000) 298 299 /***************************************************************************** 300 * 301 * Message Descriptors 302 * 303 *****************************************************************************/ 304 305 /*Request Descriptors */ 306 307 /*Default Request Descriptor */ 308 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR { 309 U8 RequestFlags; /*0x00 */ 310 U8 MSIxIndex; /*0x01 */ 311 U16 SMID; /*0x02 */ 312 U16 LMID; /*0x04 */ 313 U16 DescriptorTypeDependent; /*0x06 */ 314 } MPI2_DEFAULT_REQUEST_DESCRIPTOR, 315 *PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 316 Mpi2DefaultRequestDescriptor_t, 317 *pMpi2DefaultRequestDescriptor_t; 318 319 /*defines for the RequestFlags field */ 320 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 321 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 322 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 323 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 324 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 325 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 326 #define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C) 327 328 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 329 330 /*High Priority Request Descriptor */ 331 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR { 332 U8 RequestFlags; /*0x00 */ 333 U8 MSIxIndex; /*0x01 */ 334 U16 SMID; /*0x02 */ 335 U16 LMID; /*0x04 */ 336 U16 Reserved1; /*0x06 */ 337 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 338 *PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 339 Mpi2HighPriorityRequestDescriptor_t, 340 *pMpi2HighPriorityRequestDescriptor_t; 341 342 /*SCSI IO Request Descriptor */ 343 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR { 344 U8 RequestFlags; /*0x00 */ 345 U8 MSIxIndex; /*0x01 */ 346 U16 SMID; /*0x02 */ 347 U16 LMID; /*0x04 */ 348 U16 DevHandle; /*0x06 */ 349 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 350 *PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 351 Mpi2SCSIIORequestDescriptor_t, 352 *pMpi2SCSIIORequestDescriptor_t; 353 354 /*SCSI Target Request Descriptor */ 355 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR { 356 U8 RequestFlags; /*0x00 */ 357 U8 MSIxIndex; /*0x01 */ 358 U16 SMID; /*0x02 */ 359 U16 LMID; /*0x04 */ 360 U16 IoIndex; /*0x06 */ 361 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 362 *PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 363 Mpi2SCSITargetRequestDescriptor_t, 364 *pMpi2SCSITargetRequestDescriptor_t; 365 366 /*RAID Accelerator Request Descriptor */ 367 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR { 368 U8 RequestFlags; /*0x00 */ 369 U8 MSIxIndex; /*0x01 */ 370 U16 SMID; /*0x02 */ 371 U16 LMID; /*0x04 */ 372 U16 Reserved; /*0x06 */ 373 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 374 *PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 375 Mpi2RAIDAcceleratorRequestDescriptor_t, 376 *pMpi2RAIDAcceleratorRequestDescriptor_t; 377 378 /*Fast Path SCSI IO Request Descriptor */ 379 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR 380 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR, 381 *PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR, 382 Mpi25FastPathSCSIIORequestDescriptor_t, 383 *pMpi25FastPathSCSIIORequestDescriptor_t; 384 385 /*union of Request Descriptors */ 386 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION { 387 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 388 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 389 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 390 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 391 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 392 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO; 393 U64 Words; 394 } MPI2_REQUEST_DESCRIPTOR_UNION, 395 *PTR_MPI2_REQUEST_DESCRIPTOR_UNION, 396 Mpi2RequestDescriptorUnion_t, 397 *pMpi2RequestDescriptorUnion_t; 398 399 /*Reply Descriptors */ 400 401 /*Default Reply Descriptor */ 402 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR { 403 U8 ReplyFlags; /*0x00 */ 404 U8 MSIxIndex; /*0x01 */ 405 U16 DescriptorTypeDependent1; /*0x02 */ 406 U32 DescriptorTypeDependent2; /*0x04 */ 407 } MPI2_DEFAULT_REPLY_DESCRIPTOR, 408 *PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 409 Mpi2DefaultReplyDescriptor_t, 410 *pMpi2DefaultReplyDescriptor_t; 411 412 /*defines for the ReplyFlags field */ 413 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 414 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 415 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 416 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 417 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 418 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 419 #define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06) 420 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 421 422 /*values for marking a reply descriptor as unused */ 423 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 424 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 425 426 /*Address Reply Descriptor */ 427 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR { 428 U8 ReplyFlags; /*0x00 */ 429 U8 MSIxIndex; /*0x01 */ 430 U16 SMID; /*0x02 */ 431 U32 ReplyFrameAddress; /*0x04 */ 432 } MPI2_ADDRESS_REPLY_DESCRIPTOR, 433 *PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 434 Mpi2AddressReplyDescriptor_t, 435 *pMpi2AddressReplyDescriptor_t; 436 437 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00) 438 439 /*SCSI IO Success Reply Descriptor */ 440 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR { 441 U8 ReplyFlags; /*0x00 */ 442 U8 MSIxIndex; /*0x01 */ 443 U16 SMID; /*0x02 */ 444 U16 TaskTag; /*0x04 */ 445 U16 Reserved1; /*0x06 */ 446 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 447 *PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 448 Mpi2SCSIIOSuccessReplyDescriptor_t, 449 *pMpi2SCSIIOSuccessReplyDescriptor_t; 450 451 /*TargetAssist Success Reply Descriptor */ 452 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR { 453 U8 ReplyFlags; /*0x00 */ 454 U8 MSIxIndex; /*0x01 */ 455 U16 SMID; /*0x02 */ 456 U8 SequenceNumber; /*0x04 */ 457 U8 Reserved1; /*0x05 */ 458 U16 IoIndex; /*0x06 */ 459 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 460 *PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 461 Mpi2TargetAssistSuccessReplyDescriptor_t, 462 *pMpi2TargetAssistSuccessReplyDescriptor_t; 463 464 /*Target Command Buffer Reply Descriptor */ 465 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR { 466 U8 ReplyFlags; /*0x00 */ 467 U8 MSIxIndex; /*0x01 */ 468 U8 VP_ID; /*0x02 */ 469 U8 Flags; /*0x03 */ 470 U16 InitiatorDevHandle; /*0x04 */ 471 U16 IoIndex; /*0x06 */ 472 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 473 *PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 474 Mpi2TargetCommandBufferReplyDescriptor_t, 475 *pMpi2TargetCommandBufferReplyDescriptor_t; 476 477 /*defines for Flags field */ 478 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F) 479 480 /*RAID Accelerator Success Reply Descriptor */ 481 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR { 482 U8 ReplyFlags; /*0x00 */ 483 U8 MSIxIndex; /*0x01 */ 484 U16 SMID; /*0x02 */ 485 U32 Reserved; /*0x04 */ 486 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 487 *PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 488 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, 489 *pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 490 491 /*Fast Path SCSI IO Success Reply Descriptor */ 492 typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 493 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 494 *PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 495 Mpi25FastPathSCSIIOSuccessReplyDescriptor_t, 496 *pMpi25FastPathSCSIIOSuccessReplyDescriptor_t; 497 498 /*union of Reply Descriptors */ 499 typedef union _MPI2_REPLY_DESCRIPTORS_UNION { 500 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 501 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 502 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 503 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 504 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 505 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 506 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess; 507 U64 Words; 508 } MPI2_REPLY_DESCRIPTORS_UNION, 509 *PTR_MPI2_REPLY_DESCRIPTORS_UNION, 510 Mpi2ReplyDescriptorsUnion_t, 511 *pMpi2ReplyDescriptorsUnion_t; 512 513 /***************************************************************************** 514 * 515 * Message Functions 516 * 517 *****************************************************************************/ 518 519 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) 520 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) 521 #define MPI2_FUNCTION_IOC_INIT (0x02) 522 #define MPI2_FUNCTION_IOC_FACTS (0x03) 523 #define MPI2_FUNCTION_CONFIG (0x04) 524 #define MPI2_FUNCTION_PORT_FACTS (0x05) 525 #define MPI2_FUNCTION_PORT_ENABLE (0x06) 526 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) 527 #define MPI2_FUNCTION_EVENT_ACK (0x08) 528 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) 529 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) 530 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) 531 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) 532 #define MPI2_FUNCTION_FW_UPLOAD (0x12) 533 #define MPI2_FUNCTION_RAID_ACTION (0x15) 534 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) 535 #define MPI2_FUNCTION_TOOLBOX (0x17) 536 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) 537 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) 538 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) 539 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) 540 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) 541 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) 542 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) 543 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) 544 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) 545 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) 546 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) 547 #define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31) 548 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) 549 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) 550 551 /*Doorbell functions */ 552 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 553 #define MPI2_FUNCTION_HANDSHAKE (0x42) 554 555 /***************************************************************************** 556 * 557 * IOC Status Values 558 * 559 *****************************************************************************/ 560 561 /*mask for IOCStatus status value */ 562 #define MPI2_IOCSTATUS_MASK (0x7FFF) 563 564 /**************************************************************************** 565 * Common IOCStatus values for all replies 566 ****************************************************************************/ 567 568 #define MPI2_IOCSTATUS_SUCCESS (0x0000) 569 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001) 570 #define MPI2_IOCSTATUS_BUSY (0x0002) 571 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003) 572 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004) 573 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005) 574 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 575 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007) 576 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008) 577 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) 578 579 /**************************************************************************** 580 * Config IOCStatus values 581 ****************************************************************************/ 582 583 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 584 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 585 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 586 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 587 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 588 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 589 590 /**************************************************************************** 591 * SCSI IO Reply 592 ****************************************************************************/ 593 594 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 595 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 596 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 597 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 598 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 599 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 600 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 601 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 602 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 603 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) 604 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) 605 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) 606 607 /**************************************************************************** 608 * For use by SCSI Initiator and SCSI Target end-to-end data protection 609 ****************************************************************************/ 610 611 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D) 612 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E) 613 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F) 614 615 /**************************************************************************** 616 * SCSI Target values 617 ****************************************************************************/ 618 619 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 620 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063) 621 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 622 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 623 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) 624 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D) 625 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E) 626 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F) 627 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 628 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 629 630 /**************************************************************************** 631 * Serial Attached SCSI values 632 ****************************************************************************/ 633 634 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 635 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 636 637 /**************************************************************************** 638 * Diagnostic Buffer Post / Diagnostic Release values 639 ****************************************************************************/ 640 641 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0) 642 643 /**************************************************************************** 644 * RAID Accelerator values 645 ****************************************************************************/ 646 647 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0) 648 649 /**************************************************************************** 650 * IOCStatus flag to indicate that log info is available 651 ****************************************************************************/ 652 653 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000) 654 655 /**************************************************************************** 656 * IOCLogInfo Types 657 ****************************************************************************/ 658 659 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000) 660 #define MPI2_IOCLOGINFO_TYPE_SHIFT (28) 661 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0) 662 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1) 663 #define MPI2_IOCLOGINFO_TYPE_FC (0x2) 664 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3) 665 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4) 666 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) 667 668 /***************************************************************************** 669 * 670 * Standard Message Structures 671 * 672 *****************************************************************************/ 673 674 /**************************************************************************** 675 *Request Message Header for all request messages 676 ****************************************************************************/ 677 678 typedef struct _MPI2_REQUEST_HEADER { 679 U16 FunctionDependent1; /*0x00 */ 680 U8 ChainOffset; /*0x02 */ 681 U8 Function; /*0x03 */ 682 U16 FunctionDependent2; /*0x04 */ 683 U8 FunctionDependent3; /*0x06 */ 684 U8 MsgFlags; /*0x07 */ 685 U8 VP_ID; /*0x08 */ 686 U8 VF_ID; /*0x09 */ 687 U16 Reserved1; /*0x0A */ 688 } MPI2_REQUEST_HEADER, *PTR_MPI2_REQUEST_HEADER, 689 MPI2RequestHeader_t, *pMPI2RequestHeader_t; 690 691 /**************************************************************************** 692 * Default Reply 693 ****************************************************************************/ 694 695 typedef struct _MPI2_DEFAULT_REPLY { 696 U16 FunctionDependent1; /*0x00 */ 697 U8 MsgLength; /*0x02 */ 698 U8 Function; /*0x03 */ 699 U16 FunctionDependent2; /*0x04 */ 700 U8 FunctionDependent3; /*0x06 */ 701 U8 MsgFlags; /*0x07 */ 702 U8 VP_ID; /*0x08 */ 703 U8 VF_ID; /*0x09 */ 704 U16 Reserved1; /*0x0A */ 705 U16 FunctionDependent5; /*0x0C */ 706 U16 IOCStatus; /*0x0E */ 707 U32 IOCLogInfo; /*0x10 */ 708 } MPI2_DEFAULT_REPLY, *PTR_MPI2_DEFAULT_REPLY, 709 MPI2DefaultReply_t, *pMPI2DefaultReply_t; 710 711 /*common version structure/union used in messages and configuration pages */ 712 713 typedef struct _MPI2_VERSION_STRUCT { 714 U8 Dev; /*0x00 */ 715 U8 Unit; /*0x01 */ 716 U8 Minor; /*0x02 */ 717 U8 Major; /*0x03 */ 718 } MPI2_VERSION_STRUCT; 719 720 typedef union _MPI2_VERSION_UNION { 721 MPI2_VERSION_STRUCT Struct; 722 U32 Word; 723 } MPI2_VERSION_UNION; 724 725 /*LUN field defines, common to many structures */ 726 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) 727 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) 728 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) 729 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) 730 #define MPI2_LUN_LEVEL_1_WORD (0xFF00) 731 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00) 732 733 /***************************************************************************** 734 * 735 * Fusion-MPT MPI Scatter Gather Elements 736 * 737 *****************************************************************************/ 738 739 /**************************************************************************** 740 * MPI Simple Element structures 741 ****************************************************************************/ 742 743 typedef struct _MPI2_SGE_SIMPLE32 { 744 U32 FlagsLength; 745 U32 Address; 746 } MPI2_SGE_SIMPLE32, *PTR_MPI2_SGE_SIMPLE32, 747 Mpi2SGESimple32_t, *pMpi2SGESimple32_t; 748 749 typedef struct _MPI2_SGE_SIMPLE64 { 750 U32 FlagsLength; 751 U64 Address; 752 } MPI2_SGE_SIMPLE64, *PTR_MPI2_SGE_SIMPLE64, 753 Mpi2SGESimple64_t, *pMpi2SGESimple64_t; 754 755 typedef struct _MPI2_SGE_SIMPLE_UNION { 756 U32 FlagsLength; 757 union { 758 U32 Address32; 759 U64 Address64; 760 } u; 761 } MPI2_SGE_SIMPLE_UNION, 762 *PTR_MPI2_SGE_SIMPLE_UNION, 763 Mpi2SGESimpleUnion_t, 764 *pMpi2SGESimpleUnion_t; 765 766 /**************************************************************************** 767 * MPI Chain Element structures - for MPI v2.0 products only 768 ****************************************************************************/ 769 770 typedef struct _MPI2_SGE_CHAIN32 { 771 U16 Length; 772 U8 NextChainOffset; 773 U8 Flags; 774 U32 Address; 775 } MPI2_SGE_CHAIN32, *PTR_MPI2_SGE_CHAIN32, 776 Mpi2SGEChain32_t, *pMpi2SGEChain32_t; 777 778 typedef struct _MPI2_SGE_CHAIN64 { 779 U16 Length; 780 U8 NextChainOffset; 781 U8 Flags; 782 U64 Address; 783 } MPI2_SGE_CHAIN64, *PTR_MPI2_SGE_CHAIN64, 784 Mpi2SGEChain64_t, *pMpi2SGEChain64_t; 785 786 typedef struct _MPI2_SGE_CHAIN_UNION { 787 U16 Length; 788 U8 NextChainOffset; 789 U8 Flags; 790 union { 791 U32 Address32; 792 U64 Address64; 793 } u; 794 } MPI2_SGE_CHAIN_UNION, 795 *PTR_MPI2_SGE_CHAIN_UNION, 796 Mpi2SGEChainUnion_t, 797 *pMpi2SGEChainUnion_t; 798 799 /**************************************************************************** 800 * MPI Transaction Context Element structures - for MPI v2.0 products only 801 ****************************************************************************/ 802 803 typedef struct _MPI2_SGE_TRANSACTION32 { 804 U8 Reserved; 805 U8 ContextSize; 806 U8 DetailsLength; 807 U8 Flags; 808 U32 TransactionContext[1]; 809 U32 TransactionDetails[1]; 810 } MPI2_SGE_TRANSACTION32, 811 *PTR_MPI2_SGE_TRANSACTION32, 812 Mpi2SGETransaction32_t, 813 *pMpi2SGETransaction32_t; 814 815 typedef struct _MPI2_SGE_TRANSACTION64 { 816 U8 Reserved; 817 U8 ContextSize; 818 U8 DetailsLength; 819 U8 Flags; 820 U32 TransactionContext[2]; 821 U32 TransactionDetails[1]; 822 } MPI2_SGE_TRANSACTION64, 823 *PTR_MPI2_SGE_TRANSACTION64, 824 Mpi2SGETransaction64_t, 825 *pMpi2SGETransaction64_t; 826 827 typedef struct _MPI2_SGE_TRANSACTION96 { 828 U8 Reserved; 829 U8 ContextSize; 830 U8 DetailsLength; 831 U8 Flags; 832 U32 TransactionContext[3]; 833 U32 TransactionDetails[1]; 834 } MPI2_SGE_TRANSACTION96, *PTR_MPI2_SGE_TRANSACTION96, 835 Mpi2SGETransaction96_t, *pMpi2SGETransaction96_t; 836 837 typedef struct _MPI2_SGE_TRANSACTION128 { 838 U8 Reserved; 839 U8 ContextSize; 840 U8 DetailsLength; 841 U8 Flags; 842 U32 TransactionContext[4]; 843 U32 TransactionDetails[1]; 844 } MPI2_SGE_TRANSACTION128, *PTR_MPI2_SGE_TRANSACTION128, 845 Mpi2SGETransaction_t128, *pMpi2SGETransaction_t128; 846 847 typedef struct _MPI2_SGE_TRANSACTION_UNION { 848 U8 Reserved; 849 U8 ContextSize; 850 U8 DetailsLength; 851 U8 Flags; 852 union { 853 U32 TransactionContext32[1]; 854 U32 TransactionContext64[2]; 855 U32 TransactionContext96[3]; 856 U32 TransactionContext128[4]; 857 } u; 858 U32 TransactionDetails[1]; 859 } MPI2_SGE_TRANSACTION_UNION, 860 *PTR_MPI2_SGE_TRANSACTION_UNION, 861 Mpi2SGETransactionUnion_t, 862 *pMpi2SGETransactionUnion_t; 863 864 /**************************************************************************** 865 * MPI SGE union for IO SGL's - for MPI v2.0 products only 866 ****************************************************************************/ 867 868 typedef struct _MPI2_MPI_SGE_IO_UNION { 869 union { 870 MPI2_SGE_SIMPLE_UNION Simple; 871 MPI2_SGE_CHAIN_UNION Chain; 872 } u; 873 } MPI2_MPI_SGE_IO_UNION, *PTR_MPI2_MPI_SGE_IO_UNION, 874 Mpi2MpiSGEIOUnion_t, *pMpi2MpiSGEIOUnion_t; 875 876 /**************************************************************************** 877 * MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only 878 ****************************************************************************/ 879 880 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION { 881 union { 882 MPI2_SGE_SIMPLE_UNION Simple; 883 MPI2_SGE_TRANSACTION_UNION Transaction; 884 } u; 885 } MPI2_SGE_TRANS_SIMPLE_UNION, 886 *PTR_MPI2_SGE_TRANS_SIMPLE_UNION, 887 Mpi2SGETransSimpleUnion_t, 888 *pMpi2SGETransSimpleUnion_t; 889 890 /**************************************************************************** 891 * All MPI SGE types union 892 ****************************************************************************/ 893 894 typedef struct _MPI2_MPI_SGE_UNION { 895 union { 896 MPI2_SGE_SIMPLE_UNION Simple; 897 MPI2_SGE_CHAIN_UNION Chain; 898 MPI2_SGE_TRANSACTION_UNION Transaction; 899 } u; 900 } MPI2_MPI_SGE_UNION, *PTR_MPI2_MPI_SGE_UNION, 901 Mpi2MpiSgeUnion_t, *pMpi2MpiSgeUnion_t; 902 903 /**************************************************************************** 904 * MPI SGE field definition and masks 905 ****************************************************************************/ 906 907 /*Flags field bit definitions */ 908 909 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80) 910 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40) 911 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30) 912 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08) 913 #define MPI2_SGE_FLAGS_DIRECTION (0x04) 914 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02) 915 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01) 916 917 #define MPI2_SGE_FLAGS_SHIFT (24) 918 919 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF) 920 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF) 921 922 /*Element Type */ 923 924 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) 925 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10) 926 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30) 927 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30) 928 929 /*Address location */ 930 931 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00) 932 933 /*Direction */ 934 935 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00) 936 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04) 937 938 #define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST) 939 #define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC) 940 941 /*Address Size */ 942 943 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 944 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 945 946 /*Context Size */ 947 948 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00) 949 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02) 950 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04) 951 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06) 952 953 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000) 954 #define MPI2_SGE_CHAIN_OFFSET_SHIFT (16) 955 956 /**************************************************************************** 957 * MPI SGE operation Macros 958 ****************************************************************************/ 959 960 /*SIMPLE FlagsLength manipulations... */ 961 #define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT) 962 #define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> \ 963 MPI2_SGE_FLAGS_SHIFT) 964 #define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK) 965 #define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK) 966 967 #define MPI2_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_SGE_SET_FLAGS(f) | \ 968 MPI2_SGE_LENGTH(l)) 969 970 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength) 971 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength) 972 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \ 973 MPI2_SGE_SET_FLAGS_LENGTH(f, l)) 974 975 /*CAUTION - The following are READ-MODIFY-WRITE! */ 976 #define MPI2_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \ 977 MPI2_SGE_SET_FLAGS(f)) 978 #define MPI2_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \ 979 MPI2_SGE_LENGTH(l)) 980 981 #define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> \ 982 MPI2_SGE_CHAIN_OFFSET_SHIFT) 983 984 /***************************************************************************** 985 * 986 * Fusion-MPT IEEE Scatter Gather Elements 987 * 988 *****************************************************************************/ 989 990 /**************************************************************************** 991 * IEEE Simple Element structures 992 ****************************************************************************/ 993 994 /*MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */ 995 typedef struct _MPI2_IEEE_SGE_SIMPLE32 { 996 U32 Address; 997 U32 FlagsLength; 998 } MPI2_IEEE_SGE_SIMPLE32, *PTR_MPI2_IEEE_SGE_SIMPLE32, 999 Mpi2IeeeSgeSimple32_t, *pMpi2IeeeSgeSimple32_t; 1000 1001 typedef struct _MPI2_IEEE_SGE_SIMPLE64 { 1002 U64 Address; 1003 U32 Length; 1004 U16 Reserved1; 1005 U8 Reserved2; 1006 U8 Flags; 1007 } MPI2_IEEE_SGE_SIMPLE64, *PTR_MPI2_IEEE_SGE_SIMPLE64, 1008 Mpi2IeeeSgeSimple64_t, *pMpi2IeeeSgeSimple64_t; 1009 1010 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION { 1011 MPI2_IEEE_SGE_SIMPLE32 Simple32; 1012 MPI2_IEEE_SGE_SIMPLE64 Simple64; 1013 } MPI2_IEEE_SGE_SIMPLE_UNION, 1014 *PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 1015 Mpi2IeeeSgeSimpleUnion_t, 1016 *pMpi2IeeeSgeSimpleUnion_t; 1017 1018 /**************************************************************************** 1019 * IEEE Chain Element structures 1020 ****************************************************************************/ 1021 1022 /*MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */ 1023 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 1024 1025 /*MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */ 1026 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 1027 1028 typedef union _MPI2_IEEE_SGE_CHAIN_UNION { 1029 MPI2_IEEE_SGE_CHAIN32 Chain32; 1030 MPI2_IEEE_SGE_CHAIN64 Chain64; 1031 } MPI2_IEEE_SGE_CHAIN_UNION, 1032 *PTR_MPI2_IEEE_SGE_CHAIN_UNION, 1033 Mpi2IeeeSgeChainUnion_t, 1034 *pMpi2IeeeSgeChainUnion_t; 1035 1036 /*MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 products only */ 1037 typedef struct _MPI25_IEEE_SGE_CHAIN64 { 1038 U64 Address; 1039 U32 Length; 1040 U16 Reserved1; 1041 U8 NextChainOffset; 1042 U8 Flags; 1043 } MPI25_IEEE_SGE_CHAIN64, 1044 *PTR_MPI25_IEEE_SGE_CHAIN64, 1045 Mpi25IeeeSgeChain64_t, 1046 *pMpi25IeeeSgeChain64_t; 1047 1048 /**************************************************************************** 1049 * All IEEE SGE types union 1050 ****************************************************************************/ 1051 1052 /*MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */ 1053 typedef struct _MPI2_IEEE_SGE_UNION { 1054 union { 1055 MPI2_IEEE_SGE_SIMPLE_UNION Simple; 1056 MPI2_IEEE_SGE_CHAIN_UNION Chain; 1057 } u; 1058 } MPI2_IEEE_SGE_UNION, *PTR_MPI2_IEEE_SGE_UNION, 1059 Mpi2IeeeSgeUnion_t, *pMpi2IeeeSgeUnion_t; 1060 1061 /**************************************************************************** 1062 * IEEE SGE union for IO SGL's 1063 ****************************************************************************/ 1064 1065 typedef union _MPI25_SGE_IO_UNION { 1066 MPI2_IEEE_SGE_SIMPLE64 IeeeSimple; 1067 MPI25_IEEE_SGE_CHAIN64 IeeeChain; 1068 } MPI25_SGE_IO_UNION, *PTR_MPI25_SGE_IO_UNION, 1069 Mpi25SGEIOUnion_t, *pMpi25SGEIOUnion_t; 1070 1071 /**************************************************************************** 1072 * IEEE SGE field definitions and masks 1073 ****************************************************************************/ 1074 1075 /*Flags field bit definitions */ 1076 1077 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1078 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1079 1080 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1081 1082 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1083 1084 /*Element Type */ 1085 1086 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1087 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1088 1089 /*Data Location Address Space */ 1090 1091 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1092 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1093 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1094 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1095 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1096 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03) 1097 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR \ 1098 (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) 1099 1100 /**************************************************************************** 1101 * IEEE SGE operation Macros 1102 ****************************************************************************/ 1103 1104 /*SIMPLE FlagsLength manipulations... */ 1105 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT) 1106 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) \ 1107 >> MPI2_IEEE32_SGE_FLAGS_SHIFT) 1108 #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK) 1109 1110 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) |\ 1111 MPI2_IEEE32_SGE_LENGTH(l)) 1112 1113 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) \ 1114 MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength) 1115 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) \ 1116 MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength) 1117 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \ 1118 MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l)) 1119 1120 /*CAUTION - The following are READ-MODIFY-WRITE! */ 1121 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \ 1122 MPI2_IEEE32_SGE_SET_FLAGS(f)) 1123 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \ 1124 MPI2_IEEE32_SGE_LENGTH(l)) 1125 1126 /***************************************************************************** 1127 * 1128 * Fusion-MPT MPI/IEEE Scatter Gather Unions 1129 * 1130 *****************************************************************************/ 1131 1132 typedef union _MPI2_SIMPLE_SGE_UNION { 1133 MPI2_SGE_SIMPLE_UNION MpiSimple; 1134 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1135 } MPI2_SIMPLE_SGE_UNION, *PTR_MPI2_SIMPLE_SGE_UNION, 1136 Mpi2SimpleSgeUntion_t, *pMpi2SimpleSgeUntion_t; 1137 1138 typedef union _MPI2_SGE_IO_UNION { 1139 MPI2_SGE_SIMPLE_UNION MpiSimple; 1140 MPI2_SGE_CHAIN_UNION MpiChain; 1141 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1142 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1143 } MPI2_SGE_IO_UNION, *PTR_MPI2_SGE_IO_UNION, 1144 Mpi2SGEIOUnion_t, *pMpi2SGEIOUnion_t; 1145 1146 /**************************************************************************** 1147 * 1148 * Values for SGLFlags field, used in many request messages with an SGL 1149 * 1150 ****************************************************************************/ 1151 1152 /*values for MPI SGL Data Location Address Space subfield */ 1153 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C) 1154 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00) 1155 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04) 1156 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) 1157 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) 1158 /*values for SGL Type subfield */ 1159 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03) 1160 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00) 1161 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) 1162 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02) 1163 1164 #endif 1165