1 /* 2 * arch/arm/mach-omap2/control.h 3 * 4 * OMAP2/3/4 System Control Module definitions 5 * 6 * Copyright (C) 2007-2010 Texas Instruments, Inc. 7 * Copyright (C) 2007-2008, 2010 Nokia Corporation 8 * 9 * Written by Paul Walmsley 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation. 14 */ 15 16 #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H 17 #define __ARCH_ARM_MACH_OMAP2_CONTROL_H 18 19 #include "ctrl_module_core_44xx.h" 20 #include "ctrl_module_wkup_44xx.h" 21 #include "ctrl_module_pad_core_44xx.h" 22 #include "ctrl_module_pad_wkup_44xx.h" 23 24 #include "am33xx.h" 25 26 #ifndef __ASSEMBLY__ 27 #define OMAP242X_CTRL_REGADDR(reg) \ 28 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) 29 #define OMAP243X_CTRL_REGADDR(reg) \ 30 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) 31 #define OMAP343X_CTRL_REGADDR(reg) \ 32 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) 33 #define AM33XX_CTRL_REGADDR(reg) \ 34 AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg)) 35 #else 36 #define OMAP242X_CTRL_REGADDR(reg) \ 37 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) 38 #define OMAP243X_CTRL_REGADDR(reg) \ 39 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) 40 #define OMAP343X_CTRL_REGADDR(reg) \ 41 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) 42 #define AM33XX_CTRL_REGADDR(reg) \ 43 AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg)) 44 #endif /* __ASSEMBLY__ */ 45 46 /* 47 * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for 48 * OMAP24XX and OMAP34XX. 49 */ 50 51 /* Control submodule offsets */ 52 53 #define OMAP2_CONTROL_INTERFACE 0x000 54 #define OMAP2_CONTROL_PADCONFS 0x030 55 #define OMAP2_CONTROL_GENERAL 0x270 56 #define OMAP343X_CONTROL_MEM_WKUP 0x600 57 #define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00 58 #define OMAP343X_CONTROL_GENERAL_WKUP 0xa60 59 60 /* TI81XX spefic control submodules */ 61 #define TI81XX_CONTROL_DEVCONF 0x600 62 63 /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */ 64 65 #define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10) 66 67 /* CONTROL_GENERAL register offsets common to OMAP2 & 3 */ 68 #define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004) 69 #define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020) 70 #define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024) 71 #define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028) 72 #define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c) 73 #define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030) 74 #define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034) 75 #define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040) 76 #define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090) 77 #define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094) 78 #define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098) 79 #define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c) 80 81 /* 242x-only CONTROL_GENERAL register offsets */ 82 #define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */ 83 #define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068) 84 85 /* 243x-only CONTROL_GENERAL register offsets */ 86 /* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */ 87 #define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078) 88 #define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c) 89 #define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) 90 #define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) 91 #define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198) 92 #define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230) 93 94 /* 24xx-only CONTROL_GENERAL register offsets */ 95 #define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000) 96 #define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008) 97 #define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044) 98 #define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048) 99 #define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c) 100 #define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050) 101 #define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060) 102 #define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064) 103 #define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c) 104 #define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070) 105 #define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074) 106 #define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) 107 #define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) 108 #define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088) 109 #define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c) 110 #define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0) 111 #define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4) 112 #define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8) 113 #define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac) 114 #define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0) 115 #define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4) 116 #define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0) 117 #define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4) 118 #define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8) 119 #define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc) 120 #define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0) 121 #define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4) 122 #define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8) 123 #define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc) 124 #define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0) 125 #define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4) 126 127 #define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0) 128 129 /* 34xx-only CONTROL_GENERAL register offsets */ 130 #define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000) 131 #define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008) 132 #define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c) 133 #define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068) 134 #define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c) 135 #define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070) 136 #define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074) 137 #define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078) 138 #define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) 139 #define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) 140 #define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0) 141 #define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8) 142 #define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac) 143 #define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0) 144 #define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4) 145 #define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8) 146 #define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc) 147 #define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0) 148 #define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4) 149 #define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8) 150 #define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc) 151 #define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0) 152 #define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4) 153 #define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8) 154 #define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec) 155 #define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0) 156 #define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4) 157 #define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8) 158 #define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) 159 #define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110) 160 #define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114) 161 #define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118) 162 #define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c) 163 #define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120) 164 #define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124) 165 #define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128) 166 #define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c) 167 #define OMAP343X_CONTROL_FUSE_SR (OMAP2_CONTROL_GENERAL + 0x0130) 168 #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) 169 #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) 170 #define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \ 171 + ((i) >> 1) * 4 + (!((i) & 1)) * 2) 172 #define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4) 173 #define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8) 174 #define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0) 175 #define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4) 176 #define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8) 177 #define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC) 178 #define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0) 179 #define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4) 180 #define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8) 181 #define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0) 182 #define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4) 183 184 /* OMAP3630 only CONTROL_GENERAL register offsets */ 185 #define OMAP3630_CONTROL_FUSE_OPP1G_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110) 186 #define OMAP3630_CONTROL_FUSE_OPP50_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114) 187 #define OMAP3630_CONTROL_FUSE_OPP100_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118) 188 #define OMAP3630_CONTROL_FUSE_OPP120_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120) 189 #define OMAP3630_CONTROL_FUSE_OPP50_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128) 190 #define OMAP3630_CONTROL_FUSE_OPP100_VDD2 (OMAP2_CONTROL_GENERAL + 0x012C) 191 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL (OMAP2_CONTROL_GENERAL + 0x02f0) 192 193 /* OMAP44xx control efuse offsets */ 194 #define OMAP44XX_CONTROL_FUSE_IVA_OPP50 0x22C 195 #define OMAP44XX_CONTROL_FUSE_IVA_OPP100 0x22F 196 #define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO 0x232 197 #define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO 0x235 198 #define OMAP44XX_CONTROL_FUSE_MPU_OPP50 0x240 199 #define OMAP44XX_CONTROL_FUSE_MPU_OPP100 0x243 200 #define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO 0x246 201 #define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO 0x249 202 #define OMAP44XX_CONTROL_FUSE_CORE_OPP50 0x254 203 #define OMAP44XX_CONTROL_FUSE_CORE_OPP100 0x257 204 #define OMAP44XX_CONTROL_FUSE_CORE_OPP100OV 0x25A 205 206 /* AM35XX only CONTROL_GENERAL register offsets */ 207 #define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038) 208 #define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310) 209 #define AM35XX_CONTROL_DEVCONF3 (OMAP2_CONTROL_GENERAL + 0x0314) 210 #define AM35XX_CONTROL_CBA_PRIORITY (OMAP2_CONTROL_GENERAL + 0x0320) 211 #define AM35XX_CONTROL_LVL_INTR_CLEAR (OMAP2_CONTROL_GENERAL + 0x0324) 212 #define AM35XX_CONTROL_IP_SW_RESET (OMAP2_CONTROL_GENERAL + 0x0328) 213 #define AM35XX_CONTROL_IPSS_CLK_CTRL (OMAP2_CONTROL_GENERAL + 0x032C) 214 215 /* 34xx PADCONF register offsets */ 216 #define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \ 217 (i)*2) 218 #define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0) 219 #define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1) 220 #define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2) 221 #define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3) 222 #define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4) 223 #define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5) 224 #define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6) 225 #define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7) 226 #define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8) 227 #define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9) 228 #define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10) 229 #define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11) 230 #define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12) 231 #define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13) 232 #define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14) 233 #define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15) 234 #define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16) 235 #define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17) 236 237 /* 34xx GENERAL_WKUP register offsets */ 238 #define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \ 239 0x008 + (i)) 240 #define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008) 241 #define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C) 242 #define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010) 243 #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014) 244 #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018) 245 246 /* 36xx-only RTA - Retention till Access control registers and bits */ 247 #define OMAP36XX_CONTROL_MEM_RTA_CTRL 0x40C 248 #define OMAP36XX_RTA_DISABLE 0x0 249 250 /* 34xx D2D idle-related pins, handled by PM core */ 251 #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 252 #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 253 254 /* TI81XX CONTROL_DEVCONF register offsets */ 255 #define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000) 256 257 /* OMAP54XX CONTROL STATUS register */ 258 #define OMAP5XXX_CONTROL_STATUS 0x134 259 #define OMAP5_DEVICETYPE_MASK (0x7 << 6) 260 261 /* 262 * REVISIT: This list of registers is not comprehensive - there are more 263 * that should be added. 264 */ 265 266 /* 267 * Control module register bit defines - these should eventually go into 268 * their own regbits file. Some of these will be complicated, depending 269 * on the device type (general-purpose, emulator, test, secure, bad, other) 270 * and the security mode (secure, non-secure, don't care) 271 */ 272 /* CONTROL_DEVCONF0 bits */ 273 #define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */ 274 #define OMAP24XX_USBSTANDBYCTRL (1 << 15) 275 #define OMAP2_MCBSP2_CLKS_MASK (1 << 6) 276 #define OMAP2_MCBSP1_FSR_MASK (1 << 4) 277 #define OMAP2_MCBSP1_CLKR_MASK (1 << 3) 278 #define OMAP2_MCBSP1_CLKS_MASK (1 << 2) 279 280 /* CONTROL_DEVCONF1 bits */ 281 #define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31) 282 #define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */ 283 #define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */ 284 #define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */ 285 #define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */ 286 287 /* CONTROL_STATUS bits */ 288 #define OMAP2_DEVICETYPE_MASK (0x7 << 8) 289 #define OMAP2_SYSBOOT_5_MASK (1 << 5) 290 #define OMAP2_SYSBOOT_4_MASK (1 << 4) 291 #define OMAP2_SYSBOOT_3_MASK (1 << 3) 292 #define OMAP2_SYSBOOT_2_MASK (1 << 2) 293 #define OMAP2_SYSBOOT_1_MASK (1 << 1) 294 #define OMAP2_SYSBOOT_0_MASK (1 << 0) 295 296 /* CONTROL_PBIAS_LITE bits */ 297 #define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15) 298 #define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11) 299 #define OMAP343X_PBIASSPEEDCTRL1 (1 << 10) 300 #define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9) 301 #define OMAP343X_PBIASLITEVMODE1 (1 << 8) 302 #define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7) 303 #define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3) 304 #define OMAP2_PBIASSPEEDCTRL0 (1 << 2) 305 #define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) 306 #define OMAP2_PBIASLITEVMODE0 (1 << 0) 307 308 /* CONTROL_PROG_IO1 bits */ 309 #define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20) 310 311 /* CONTROL_IVA2_BOOTMOD bits */ 312 #define OMAP3_IVA2_BOOTMOD_SHIFT 0 313 #define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0) 314 #define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0) 315 316 /* CONTROL_PADCONF_X bits */ 317 #define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15) 318 #define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14) 319 320 #define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860) 321 #define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910) 322 #define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C 323 #define OMAP343X_SCRATCHPAD_REGADDR(reg) OMAP2_L4_IO_ADDRESS(\ 324 OMAP343X_SCRATCHPAD + reg) 325 326 /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ 327 #define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 328 #define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1 329 #define AM35XX_VPFE_VBUSP_CLK_SHIFT 2 330 #define AM35XX_HECC_VBUSP_CLK_SHIFT 3 331 #define AM35XX_USBOTG_FCLK_SHIFT 8 332 #define AM35XX_CPGMAC_FCLK_SHIFT 9 333 #define AM35XX_VPFE_FCLK_SHIFT 10 334 335 /* AM35XX CONTROL_LVL_INTR_CLEAR bits */ 336 #define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0) 337 #define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1) 338 #define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2) 339 #define AM35XX_CPGMAC_C0_TX_PULSE_CLR BIT(3) 340 #define AM35XX_USBOTGSS_INT_CLR BIT(4) 341 #define AM35XX_VPFE_CCDC_VD0_INT_CLR BIT(5) 342 #define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6) 343 #define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7) 344 345 /* AM35XX CONTROL_IP_SW_RESET bits */ 346 #define AM35XX_USBOTGSS_SW_RST BIT(0) 347 #define AM35XX_CPGMACSS_SW_RST BIT(1) 348 #define AM35XX_VPFE_VBUSP_SW_RST BIT(2) 349 #define AM35XX_HECC_SW_RST BIT(3) 350 #define AM35XX_VPFE_PCLK_SW_RST BIT(4) 351 352 /* AM33XX CONTROL_STATUS register */ 353 #define AM33XX_CONTROL_STATUS 0x040 354 #define AM33XX_CONTROL_SEC_CLK_CTRL 0x1bc 355 356 /* AM33XX CONTROL_STATUS bitfields (partial) */ 357 #define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT 22 358 #define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH 0x2 359 #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22) 360 361 /* CONTROL OMAP STATUS register to identify OMAP3 features */ 362 #define OMAP3_CONTROL_OMAP_STATUS 0x044c 363 364 #define OMAP3_SGX_SHIFT 13 365 #define OMAP3_SGX_MASK (3 << OMAP3_SGX_SHIFT) 366 #define FEAT_SGX_FULL 0 367 #define FEAT_SGX_HALF 1 368 #define FEAT_SGX_NONE 2 369 370 #define OMAP3_IVA_SHIFT 12 371 #define OMAP3_IVA_MASK (1 << OMAP3_IVA_SHIFT) 372 #define FEAT_IVA 0 373 #define FEAT_IVA_NONE 1 374 375 #define OMAP3_L2CACHE_SHIFT 10 376 #define OMAP3_L2CACHE_MASK (3 << OMAP3_L2CACHE_SHIFT) 377 #define FEAT_L2CACHE_NONE 0 378 #define FEAT_L2CACHE_64KB 1 379 #define FEAT_L2CACHE_128KB 2 380 #define FEAT_L2CACHE_256KB 3 381 382 #define OMAP3_ISP_SHIFT 5 383 #define OMAP3_ISP_MASK (1 << OMAP3_ISP_SHIFT) 384 #define FEAT_ISP 0 385 #define FEAT_ISP_NONE 1 386 387 #define OMAP3_NEON_SHIFT 4 388 #define OMAP3_NEON_MASK (1 << OMAP3_NEON_SHIFT) 389 #define FEAT_NEON 0 390 #define FEAT_NEON_NONE 1 391 392 393 #ifndef __ASSEMBLY__ 394 #ifdef CONFIG_ARCH_OMAP2PLUS 395 extern void __iomem *omap_ctrl_base_get(void); 396 extern u8 omap_ctrl_readb(u16 offset); 397 extern u16 omap_ctrl_readw(u16 offset); 398 extern u32 omap_ctrl_readl(u16 offset); 399 extern u32 omap4_ctrl_pad_readl(u16 offset); 400 extern void omap_ctrl_writeb(u8 val, u16 offset); 401 extern void omap_ctrl_writew(u16 val, u16 offset); 402 extern void omap_ctrl_writel(u32 val, u16 offset); 403 extern void omap4_ctrl_pad_writel(u32 val, u16 offset); 404 405 extern void omap3_save_scratchpad_contents(void); 406 extern void omap3_clear_scratchpad_contents(void); 407 extern void omap3_restore(void); 408 extern void omap3_restore_es3(void); 409 extern void omap3_restore_3630(void); 410 extern u32 omap3_arm_context[128]; 411 extern void omap3_control_save_context(void); 412 extern void omap3_control_restore_context(void); 413 extern void omap3_ctrl_write_boot_mode(u8 bootmode); 414 extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr); 415 extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode); 416 extern void omap3630_ctrl_disable_rta(void); 417 extern int omap3_ctrl_save_padconf(void); 418 extern void omap2_set_globals_control(void __iomem *ctrl, 419 void __iomem *ctrl_pad); 420 #else 421 #define omap_ctrl_base_get() 0 422 #define omap_ctrl_readb(x) 0 423 #define omap_ctrl_readw(x) 0 424 #define omap_ctrl_readl(x) 0 425 #define omap4_ctrl_pad_readl(x) 0 426 #define omap_ctrl_writeb(x, y) WARN_ON(1) 427 #define omap_ctrl_writew(x, y) WARN_ON(1) 428 #define omap_ctrl_writel(x, y) WARN_ON(1) 429 #define omap4_ctrl_pad_writel(x, y) WARN_ON(1) 430 #endif 431 #endif /* __ASSEMBLY__ */ 432 433 #endif /* __ARCH_ARM_MACH_OMAP2_CONTROL_H */ 434 435