1 /* 2 * Copyright (c) 2003-2012 Broadcom Corporation 3 * All Rights Reserved 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the Broadcom 9 * license below: 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in 19 * the documentation and/or other materials provided with the 20 * distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #ifndef __NLM_HAL_PCIBUS_H__ 36 #define __NLM_HAL_PCIBUS_H__ 37 38 /* PCIE Memory and IO regions */ 39 #define PCIE_MEM_BASE 0xd0000000ULL 40 #define PCIE_MEM_LIMIT 0xdfffffffULL 41 #define PCIE_IO_BASE 0x14000000ULL 42 #define PCIE_IO_LIMIT 0x15ffffffULL 43 44 #define PCIE_BRIDGE_CMD 0x1 45 #define PCIE_BRIDGE_MSI_CAP 0x14 46 #define PCIE_BRIDGE_MSI_ADDRL 0x15 47 #define PCIE_BRIDGE_MSI_ADDRH 0x16 48 #define PCIE_BRIDGE_MSI_DATA 0x17 49 50 /* XLP Global PCIE configuration space registers */ 51 #define PCIE_BYTE_SWAP_MEM_BASE 0x247 52 #define PCIE_BYTE_SWAP_MEM_LIM 0x248 53 #define PCIE_BYTE_SWAP_IO_BASE 0x249 54 #define PCIE_BYTE_SWAP_IO_LIM 0x24A 55 #define PCIE_MSI_STATUS 0x25A 56 #define PCIE_MSI_EN 0x25B 57 #define PCIE_INT_EN0 0x261 58 59 /* PCIE_MSI_EN */ 60 #define PCIE_MSI_VECTOR_INT_EN 0xFFFFFFFF 61 62 /* PCIE_INT_EN0 */ 63 #define PCIE_MSI_INT_EN (1 << 9) 64 65 #ifndef __ASSEMBLY__ 66 67 #define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r) 68 #define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v) 69 #define nlm_get_pcie_base(node, inst) \ 70 nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, inst)) 71 #define nlm_get_pcie_regbase(node, inst) \ 72 (nlm_get_pcie_base(node, inst) + XLP_IO_PCI_HDRSZ) 73 74 int xlp_pcie_link_irt(int link); 75 #endif 76 #endif /* __NLM_HAL_PCIBUS_H__ */ 77