1 /* 2 * SuperH Pin Function Controller Support 3 * 4 * Copyright (c) 2008 Magnus Damm 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 11 #ifndef __SH_PFC_H 12 #define __SH_PFC_H 13 14 #include <linux/stringify.h> 15 #include <asm-generic/gpio.h> 16 17 typedef unsigned short pinmux_enum_t; 18 19 #define SH_PFC_MARK_INVALID ((pinmux_enum_t)-1) 20 21 enum { 22 PINMUX_TYPE_NONE, 23 24 PINMUX_TYPE_FUNCTION, 25 PINMUX_TYPE_GPIO, 26 PINMUX_TYPE_OUTPUT, 27 PINMUX_TYPE_INPUT, 28 PINMUX_TYPE_INPUT_PULLUP, 29 PINMUX_TYPE_INPUT_PULLDOWN, 30 31 PINMUX_FLAG_TYPE, /* must be last */ 32 }; 33 34 #define SH_PFC_PIN_CFG_INPUT (1 << 0) 35 #define SH_PFC_PIN_CFG_OUTPUT (1 << 1) 36 #define SH_PFC_PIN_CFG_PULL_UP (1 << 2) 37 #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3) 38 39 struct sh_pfc_pin { 40 const pinmux_enum_t enum_id; 41 const char *name; 42 unsigned int configs; 43 }; 44 45 #define SH_PFC_PIN_GROUP(n) \ 46 { \ 47 .name = #n, \ 48 .pins = n##_pins, \ 49 .mux = n##_mux, \ 50 .nr_pins = ARRAY_SIZE(n##_pins), \ 51 } 52 53 struct sh_pfc_pin_group { 54 const char *name; 55 const unsigned int *pins; 56 const unsigned int *mux; 57 unsigned int nr_pins; 58 }; 59 60 #define SH_PFC_FUNCTION(n) \ 61 { \ 62 .name = #n, \ 63 .groups = n##_groups, \ 64 .nr_groups = ARRAY_SIZE(n##_groups), \ 65 } 66 67 struct sh_pfc_function { 68 const char *name; 69 const char * const *groups; 70 unsigned int nr_groups; 71 }; 72 73 struct pinmux_func { 74 const pinmux_enum_t enum_id; 75 const char *name; 76 }; 77 78 #define PINMUX_GPIO(gpio, data_or_mark) \ 79 [gpio] = { \ 80 .name = __stringify(gpio), \ 81 .enum_id = data_or_mark, \ 82 } 83 #define PINMUX_GPIO_FN(gpio, base, data_or_mark) \ 84 [gpio - (base)] = { \ 85 .name = __stringify(gpio), \ 86 .enum_id = data_or_mark, \ 87 } 88 89 #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0 90 91 struct pinmux_cfg_reg { 92 unsigned long reg, reg_width, field_width; 93 const pinmux_enum_t *enum_ids; 94 const unsigned long *var_field_width; 95 }; 96 97 #define PINMUX_CFG_REG(name, r, r_width, f_width) \ 98 .reg = r, .reg_width = r_width, .field_width = f_width, \ 99 .enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)]) 100 101 #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ 102 .reg = r, .reg_width = r_width, \ 103 .var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \ 104 .enum_ids = (pinmux_enum_t []) 105 106 struct pinmux_data_reg { 107 unsigned long reg, reg_width; 108 const pinmux_enum_t *enum_ids; 109 }; 110 111 #define PINMUX_DATA_REG(name, r, r_width) \ 112 .reg = r, .reg_width = r_width, \ 113 .enum_ids = (pinmux_enum_t [r_width]) \ 114 115 struct pinmux_irq { 116 int irq; 117 unsigned short *gpios; 118 }; 119 120 #define PINMUX_IRQ(irq_nr, ids...) \ 121 { .irq = irq_nr, .gpios = (unsigned short []) { ids, 0 } } \ 122 123 struct pinmux_range { 124 pinmux_enum_t begin; 125 pinmux_enum_t end; 126 pinmux_enum_t force; 127 }; 128 129 struct sh_pfc; 130 131 struct sh_pfc_soc_operations { 132 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin); 133 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin, 134 unsigned int bias); 135 }; 136 137 struct sh_pfc_soc_info { 138 const char *name; 139 const struct sh_pfc_soc_operations *ops; 140 141 struct pinmux_range input; 142 struct pinmux_range input_pd; 143 struct pinmux_range input_pu; 144 struct pinmux_range output; 145 struct pinmux_range function; 146 147 const struct sh_pfc_pin *pins; 148 unsigned int nr_pins; 149 const struct pinmux_range *ranges; 150 unsigned int nr_ranges; 151 const struct sh_pfc_pin_group *groups; 152 unsigned int nr_groups; 153 const struct sh_pfc_function *functions; 154 unsigned int nr_functions; 155 156 const struct pinmux_func *func_gpios; 157 unsigned int nr_func_gpios; 158 159 const struct pinmux_cfg_reg *cfg_regs; 160 const struct pinmux_data_reg *data_regs; 161 162 const pinmux_enum_t *gpio_data; 163 unsigned int gpio_data_size; 164 165 const struct pinmux_irq *gpio_irq; 166 unsigned int gpio_irq_size; 167 168 unsigned long unlock_reg; 169 }; 170 171 enum { GPIO_CFG_REQ, GPIO_CFG_FREE }; 172 173 /* helper macro for port */ 174 #define PORT_1(fn, pfx, sfx) fn(pfx, sfx) 175 176 #define PORT_10(fn, pfx, sfx) \ 177 PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \ 178 PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \ 179 PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \ 180 PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \ 181 PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx) 182 183 #define PORT_10_REV(fn, pfx, sfx) \ 184 PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ 185 PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ 186 PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ 187 PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ 188 PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) 189 190 #define PORT_32(fn, pfx, sfx) \ 191 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ 192 PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ 193 PORT_1(fn, pfx##31, sfx) 194 195 #define PORT_32_REV(fn, pfx, sfx) \ 196 PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ 197 PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ 198 PORT_10_REV(fn, pfx, sfx) 199 200 #define PORT_90(fn, pfx, sfx) \ 201 PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx), \ 202 PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx), \ 203 PORT_10(fn, pfx##5, sfx), PORT_10(fn, pfx##6, sfx), \ 204 PORT_10(fn, pfx##7, sfx), PORT_10(fn, pfx##8, sfx), \ 205 PORT_10(fn, pfx##9, sfx) 206 207 #define _PORT_ALL(pfx, sfx) pfx##_##sfx 208 #define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA) 209 #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) 210 #define GPIO_PORT_ALL() CPU_ALL_PORT(_GPIO_PORT, , unused) 211 #define GPIO_FN(str) PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK) 212 213 /* helper macro for pinmux_enum_t */ 214 #define PORT_DATA_I(nr) \ 215 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN) 216 217 #define PORT_DATA_I_PD(nr) \ 218 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ 219 PORT##nr##_IN, PORT##nr##_IN_PD) 220 221 #define PORT_DATA_I_PU(nr) \ 222 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ 223 PORT##nr##_IN, PORT##nr##_IN_PU) 224 225 #define PORT_DATA_I_PU_PD(nr) \ 226 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ 227 PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU) 228 229 #define PORT_DATA_O(nr) \ 230 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT) 231 232 #define PORT_DATA_IO(nr) \ 233 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ 234 PORT##nr##_IN) 235 236 #define PORT_DATA_IO_PD(nr) \ 237 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ 238 PORT##nr##_IN, PORT##nr##_IN_PD) 239 240 #define PORT_DATA_IO_PU(nr) \ 241 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ 242 PORT##nr##_IN, PORT##nr##_IN_PU) 243 244 #define PORT_DATA_IO_PU_PD(nr) \ 245 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \ 246 PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU) 247 248 /* helper macro for top 4 bits in PORTnCR */ 249 #define _PCRH(in, in_pd, in_pu, out) \ 250 0, (out), (in), 0, \ 251 0, 0, 0, 0, \ 252 0, 0, (in_pd), 0, \ 253 0, 0, (in_pu), 0 254 255 #define PORTCR(nr, reg) \ 256 { \ 257 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ 258 _PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \ 259 PORT##nr##_IN_PU, PORT##nr##_OUT), \ 260 PORT##nr##_FN0, PORT##nr##_FN1, \ 261 PORT##nr##_FN2, PORT##nr##_FN3, \ 262 PORT##nr##_FN4, PORT##nr##_FN5, \ 263 PORT##nr##_FN6, PORT##nr##_FN7 } \ 264 } 265 266 #endif /* __SH_PFC_H */ 267