1 /* 2 * Copyright (C) 2012 ARM Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 #ifndef __ASM_PGTABLE_HWDEF_H 17 #define __ASM_PGTABLE_HWDEF_H 18 19 #ifdef CONFIG_ARM64_64K_PAGES 20 #include <asm/pgtable-2level-hwdef.h> 21 #else 22 #include <asm/pgtable-3level-hwdef.h> 23 #endif 24 25 /* 26 * Hardware page table definitions. 27 * 28 * Level 1 descriptor (PUD). 29 */ 30 31 #define PUD_TABLE_BIT (_AT(pgdval_t, 1) << 1) 32 33 /* 34 * Level 2 descriptor (PMD). 35 */ 36 #define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0) 37 #define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0) 38 #define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0) 39 #define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0) 40 #define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1) 41 42 /* 43 * Section 44 */ 45 #define PMD_SECT_VALID (_AT(pmdval_t, 1) << 0) 46 #define PMD_SECT_PROT_NONE (_AT(pmdval_t, 1) << 58) 47 #define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */ 48 #define PMD_SECT_RDONLY (_AT(pmdval_t, 1) << 7) /* AP[2] */ 49 #define PMD_SECT_S (_AT(pmdval_t, 3) << 8) 50 #define PMD_SECT_AF (_AT(pmdval_t, 1) << 10) 51 #define PMD_SECT_NG (_AT(pmdval_t, 1) << 11) 52 #define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53) 53 #define PMD_SECT_UXN (_AT(pmdval_t, 1) << 54) 54 55 /* 56 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 57 */ 58 #define PMD_ATTRINDX(t) (_AT(pmdval_t, (t)) << 2) 59 #define PMD_ATTRINDX_MASK (_AT(pmdval_t, 7) << 2) 60 61 /* 62 * Level 3 descriptor (PTE). 63 */ 64 #define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0) 65 #define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0) 66 #define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0) 67 #define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1) 68 #define PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ 69 #define PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */ 70 #define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ 71 #define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ 72 #define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */ 73 #define PTE_PXN (_AT(pteval_t, 1) << 53) /* Privileged XN */ 74 #define PTE_UXN (_AT(pteval_t, 1) << 54) /* User XN */ 75 76 /* 77 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 78 */ 79 #define PTE_ATTRINDX(t) (_AT(pteval_t, (t)) << 2) 80 #define PTE_ATTRINDX_MASK (_AT(pteval_t, 7) << 2) 81 82 /* 83 * 40-bit physical address supported. 84 */ 85 #define PHYS_MASK_SHIFT (40) 86 #define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1) 87 88 /* 89 * TCR flags. 90 */ 91 #define TCR_TxSZ(x) (((UL(64) - (x)) << 16) | ((UL(64) - (x)) << 0)) 92 #define TCR_IRGN_NC ((UL(0) << 8) | (UL(0) << 24)) 93 #define TCR_IRGN_WBWA ((UL(1) << 8) | (UL(1) << 24)) 94 #define TCR_IRGN_WT ((UL(2) << 8) | (UL(2) << 24)) 95 #define TCR_IRGN_WBnWA ((UL(3) << 8) | (UL(3) << 24)) 96 #define TCR_IRGN_MASK ((UL(3) << 8) | (UL(3) << 24)) 97 #define TCR_ORGN_NC ((UL(0) << 10) | (UL(0) << 26)) 98 #define TCR_ORGN_WBWA ((UL(1) << 10) | (UL(1) << 26)) 99 #define TCR_ORGN_WT ((UL(2) << 10) | (UL(2) << 26)) 100 #define TCR_ORGN_WBnWA ((UL(3) << 10) | (UL(3) << 26)) 101 #define TCR_ORGN_MASK ((UL(3) << 10) | (UL(3) << 26)) 102 #define TCR_SHARED ((UL(3) << 12) | (UL(3) << 28)) 103 #define TCR_TG0_64K (UL(1) << 14) 104 #define TCR_TG1_64K (UL(1) << 30) 105 #define TCR_IPS_40BIT (UL(2) << 32) 106 #define TCR_ASID16 (UL(1) << 36) 107 #define TCR_TBI0 (UL(1) << 37) 108 109 #endif 110