1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2010 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __T4_REGS_H 36 #define __T4_REGS_H 37 38 #define MYPF_BASE 0x1b000 39 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr)) 40 41 #define PF0_BASE 0x1e000 42 #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr)) 43 44 #define PF_STRIDE 0x400 45 #define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE) 46 #define PF_REG(idx, reg) (PF_BASE(idx) + (reg)) 47 48 #define MYPORT_BASE 0x1c000 49 #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr)) 50 51 #define PORT0_BASE 0x20000 52 #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr)) 53 54 #define PORT_STRIDE 0x2000 55 #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE) 56 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg)) 57 58 #define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR) 59 #define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx) 60 61 #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) 62 #define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) 63 #define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 64 #define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 65 66 #define SGE_PF_KDOORBELL 0x0 67 #define QID_MASK 0xffff8000U 68 #define QID_SHIFT 15 69 #define QID(x) ((x) << QID_SHIFT) 70 #define DBPRIO(x) ((x) << 14) 71 #define DBTYPE(x) ((x) << 13) 72 #define PIDX_MASK 0x00003fffU 73 #define PIDX_SHIFT 0 74 #define PIDX(x) ((x) << PIDX_SHIFT) 75 #define S_PIDX_T5 0 76 #define M_PIDX_T5 0x1fffU 77 #define PIDX_T5(x) (((x) >> S_PIDX_T5) & M_PIDX_T5) 78 79 80 #define SGE_PF_GTS 0x4 81 #define INGRESSQID_MASK 0xffff0000U 82 #define INGRESSQID_SHIFT 16 83 #define INGRESSQID(x) ((x) << INGRESSQID_SHIFT) 84 #define TIMERREG_MASK 0x0000e000U 85 #define TIMERREG_SHIFT 13 86 #define TIMERREG(x) ((x) << TIMERREG_SHIFT) 87 #define SEINTARM_MASK 0x00001000U 88 #define SEINTARM_SHIFT 12 89 #define SEINTARM(x) ((x) << SEINTARM_SHIFT) 90 #define CIDXINC_MASK 0x00000fffU 91 #define CIDXINC_SHIFT 0 92 #define CIDXINC(x) ((x) << CIDXINC_SHIFT) 93 94 #define X_RXPKTCPLMODE_SPLIT 1 95 #define X_INGPADBOUNDARY_SHIFT 5 96 97 #define SGE_CONTROL 0x1008 98 #define DCASYSTYPE 0x00080000U 99 #define RXPKTCPLMODE_MASK 0x00040000U 100 #define RXPKTCPLMODE_SHIFT 18 101 #define RXPKTCPLMODE(x) ((x) << RXPKTCPLMODE_SHIFT) 102 #define EGRSTATUSPAGESIZE_MASK 0x00020000U 103 #define EGRSTATUSPAGESIZE_SHIFT 17 104 #define EGRSTATUSPAGESIZE(x) ((x) << EGRSTATUSPAGESIZE_SHIFT) 105 #define PKTSHIFT_MASK 0x00001c00U 106 #define PKTSHIFT_SHIFT 10 107 #define PKTSHIFT(x) ((x) << PKTSHIFT_SHIFT) 108 #define PKTSHIFT_GET(x) (((x) & PKTSHIFT_MASK) >> PKTSHIFT_SHIFT) 109 #define INGPCIEBOUNDARY_MASK 0x00000380U 110 #define INGPCIEBOUNDARY_SHIFT 7 111 #define INGPCIEBOUNDARY(x) ((x) << INGPCIEBOUNDARY_SHIFT) 112 #define INGPADBOUNDARY_MASK 0x00000070U 113 #define INGPADBOUNDARY_SHIFT 4 114 #define INGPADBOUNDARY(x) ((x) << INGPADBOUNDARY_SHIFT) 115 #define INGPADBOUNDARY_GET(x) (((x) & INGPADBOUNDARY_MASK) \ 116 >> INGPADBOUNDARY_SHIFT) 117 #define EGRPCIEBOUNDARY_MASK 0x0000000eU 118 #define EGRPCIEBOUNDARY_SHIFT 1 119 #define EGRPCIEBOUNDARY(x) ((x) << EGRPCIEBOUNDARY_SHIFT) 120 #define GLOBALENABLE 0x00000001U 121 122 #define SGE_HOST_PAGE_SIZE 0x100c 123 124 #define HOSTPAGESIZEPF7_MASK 0x0000000fU 125 #define HOSTPAGESIZEPF7_SHIFT 28 126 #define HOSTPAGESIZEPF7(x) ((x) << HOSTPAGESIZEPF7_SHIFT) 127 128 #define HOSTPAGESIZEPF6_MASK 0x0000000fU 129 #define HOSTPAGESIZEPF6_SHIFT 24 130 #define HOSTPAGESIZEPF6(x) ((x) << HOSTPAGESIZEPF6_SHIFT) 131 132 #define HOSTPAGESIZEPF5_MASK 0x0000000fU 133 #define HOSTPAGESIZEPF5_SHIFT 20 134 #define HOSTPAGESIZEPF5(x) ((x) << HOSTPAGESIZEPF5_SHIFT) 135 136 #define HOSTPAGESIZEPF4_MASK 0x0000000fU 137 #define HOSTPAGESIZEPF4_SHIFT 16 138 #define HOSTPAGESIZEPF4(x) ((x) << HOSTPAGESIZEPF4_SHIFT) 139 140 #define HOSTPAGESIZEPF3_MASK 0x0000000fU 141 #define HOSTPAGESIZEPF3_SHIFT 12 142 #define HOSTPAGESIZEPF3(x) ((x) << HOSTPAGESIZEPF3_SHIFT) 143 144 #define HOSTPAGESIZEPF2_MASK 0x0000000fU 145 #define HOSTPAGESIZEPF2_SHIFT 8 146 #define HOSTPAGESIZEPF2(x) ((x) << HOSTPAGESIZEPF2_SHIFT) 147 148 #define HOSTPAGESIZEPF1_MASK 0x0000000fU 149 #define HOSTPAGESIZEPF1_SHIFT 4 150 #define HOSTPAGESIZEPF1(x) ((x) << HOSTPAGESIZEPF1_SHIFT) 151 152 #define HOSTPAGESIZEPF0_MASK 0x0000000fU 153 #define HOSTPAGESIZEPF0_SHIFT 0 154 #define HOSTPAGESIZEPF0(x) ((x) << HOSTPAGESIZEPF0_SHIFT) 155 156 #define SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010 157 #define QUEUESPERPAGEPF0_MASK 0x0000000fU 158 #define QUEUESPERPAGEPF0_GET(x) ((x) & QUEUESPERPAGEPF0_MASK) 159 160 #define QUEUESPERPAGEPF1 4 161 162 #define SGE_INT_CAUSE1 0x1024 163 #define SGE_INT_CAUSE2 0x1030 164 #define SGE_INT_CAUSE3 0x103c 165 #define ERR_FLM_DBP 0x80000000U 166 #define ERR_FLM_IDMA1 0x40000000U 167 #define ERR_FLM_IDMA0 0x20000000U 168 #define ERR_FLM_HINT 0x10000000U 169 #define ERR_PCIE_ERROR3 0x08000000U 170 #define ERR_PCIE_ERROR2 0x04000000U 171 #define ERR_PCIE_ERROR1 0x02000000U 172 #define ERR_PCIE_ERROR0 0x01000000U 173 #define ERR_TIMER_ABOVE_MAX_QID 0x00800000U 174 #define ERR_CPL_EXCEED_IQE_SIZE 0x00400000U 175 #define ERR_INVALID_CIDX_INC 0x00200000U 176 #define ERR_ITP_TIME_PAUSED 0x00100000U 177 #define ERR_CPL_OPCODE_0 0x00080000U 178 #define ERR_DROPPED_DB 0x00040000U 179 #define ERR_DATA_CPL_ON_HIGH_QID1 0x00020000U 180 #define ERR_DATA_CPL_ON_HIGH_QID0 0x00010000U 181 #define ERR_BAD_DB_PIDX3 0x00008000U 182 #define ERR_BAD_DB_PIDX2 0x00004000U 183 #define ERR_BAD_DB_PIDX1 0x00002000U 184 #define ERR_BAD_DB_PIDX0 0x00001000U 185 #define ERR_ING_PCIE_CHAN 0x00000800U 186 #define ERR_ING_CTXT_PRIO 0x00000400U 187 #define ERR_EGR_CTXT_PRIO 0x00000200U 188 #define DBFIFO_HP_INT 0x00000100U 189 #define DBFIFO_LP_INT 0x00000080U 190 #define REG_ADDRESS_ERR 0x00000040U 191 #define INGRESS_SIZE_ERR 0x00000020U 192 #define EGRESS_SIZE_ERR 0x00000010U 193 #define ERR_INV_CTXT3 0x00000008U 194 #define ERR_INV_CTXT2 0x00000004U 195 #define ERR_INV_CTXT1 0x00000002U 196 #define ERR_INV_CTXT0 0x00000001U 197 198 #define SGE_INT_ENABLE3 0x1040 199 #define SGE_FL_BUFFER_SIZE0 0x1044 200 #define SGE_FL_BUFFER_SIZE1 0x1048 201 #define SGE_FL_BUFFER_SIZE2 0x104c 202 #define SGE_FL_BUFFER_SIZE3 0x1050 203 #define SGE_FL_BUFFER_SIZE4 0x1054 204 #define SGE_FL_BUFFER_SIZE5 0x1058 205 #define SGE_FL_BUFFER_SIZE6 0x105c 206 #define SGE_FL_BUFFER_SIZE7 0x1060 207 #define SGE_FL_BUFFER_SIZE8 0x1064 208 209 #define SGE_INGRESS_RX_THRESHOLD 0x10a0 210 #define THRESHOLD_0_MASK 0x3f000000U 211 #define THRESHOLD_0_SHIFT 24 212 #define THRESHOLD_0(x) ((x) << THRESHOLD_0_SHIFT) 213 #define THRESHOLD_0_GET(x) (((x) & THRESHOLD_0_MASK) >> THRESHOLD_0_SHIFT) 214 #define THRESHOLD_1_MASK 0x003f0000U 215 #define THRESHOLD_1_SHIFT 16 216 #define THRESHOLD_1(x) ((x) << THRESHOLD_1_SHIFT) 217 #define THRESHOLD_1_GET(x) (((x) & THRESHOLD_1_MASK) >> THRESHOLD_1_SHIFT) 218 #define THRESHOLD_2_MASK 0x00003f00U 219 #define THRESHOLD_2_SHIFT 8 220 #define THRESHOLD_2(x) ((x) << THRESHOLD_2_SHIFT) 221 #define THRESHOLD_2_GET(x) (((x) & THRESHOLD_2_MASK) >> THRESHOLD_2_SHIFT) 222 #define THRESHOLD_3_MASK 0x0000003fU 223 #define THRESHOLD_3_SHIFT 0 224 #define THRESHOLD_3(x) ((x) << THRESHOLD_3_SHIFT) 225 #define THRESHOLD_3_GET(x) (((x) & THRESHOLD_3_MASK) >> THRESHOLD_3_SHIFT) 226 227 #define SGE_CONM_CTRL 0x1094 228 #define EGRTHRESHOLD_MASK 0x00003f00U 229 #define EGRTHRESHOLDshift 8 230 #define EGRTHRESHOLD(x) ((x) << EGRTHRESHOLDshift) 231 #define EGRTHRESHOLD_GET(x) (((x) & EGRTHRESHOLD_MASK) >> EGRTHRESHOLDshift) 232 233 #define SGE_DBFIFO_STATUS 0x10a4 234 #define HP_INT_THRESH_SHIFT 28 235 #define HP_INT_THRESH_MASK 0xfU 236 #define HP_INT_THRESH(x) ((x) << HP_INT_THRESH_SHIFT) 237 #define LP_INT_THRESH_SHIFT 12 238 #define LP_INT_THRESH_MASK 0xfU 239 #define LP_INT_THRESH(x) ((x) << LP_INT_THRESH_SHIFT) 240 241 #define SGE_DOORBELL_CONTROL 0x10a8 242 #define ENABLE_DROP (1 << 13) 243 244 #define S_NOCOALESCE 26 245 #define V_NOCOALESCE(x) ((x) << S_NOCOALESCE) 246 #define F_NOCOALESCE V_NOCOALESCE(1U) 247 248 #define SGE_TIMER_VALUE_0_AND_1 0x10b8 249 #define TIMERVALUE0_MASK 0xffff0000U 250 #define TIMERVALUE0_SHIFT 16 251 #define TIMERVALUE0(x) ((x) << TIMERVALUE0_SHIFT) 252 #define TIMERVALUE0_GET(x) (((x) & TIMERVALUE0_MASK) >> TIMERVALUE0_SHIFT) 253 #define TIMERVALUE1_MASK 0x0000ffffU 254 #define TIMERVALUE1_SHIFT 0 255 #define TIMERVALUE1(x) ((x) << TIMERVALUE1_SHIFT) 256 #define TIMERVALUE1_GET(x) (((x) & TIMERVALUE1_MASK) >> TIMERVALUE1_SHIFT) 257 258 #define SGE_TIMER_VALUE_2_AND_3 0x10bc 259 #define TIMERVALUE2_MASK 0xffff0000U 260 #define TIMERVALUE2_SHIFT 16 261 #define TIMERVALUE2(x) ((x) << TIMERVALUE2_SHIFT) 262 #define TIMERVALUE2_GET(x) (((x) & TIMERVALUE2_MASK) >> TIMERVALUE2_SHIFT) 263 #define TIMERVALUE3_MASK 0x0000ffffU 264 #define TIMERVALUE3_SHIFT 0 265 #define TIMERVALUE3(x) ((x) << TIMERVALUE3_SHIFT) 266 #define TIMERVALUE3_GET(x) (((x) & TIMERVALUE3_MASK) >> TIMERVALUE3_SHIFT) 267 268 #define SGE_TIMER_VALUE_4_AND_5 0x10c0 269 #define TIMERVALUE4_MASK 0xffff0000U 270 #define TIMERVALUE4_SHIFT 16 271 #define TIMERVALUE4(x) ((x) << TIMERVALUE4_SHIFT) 272 #define TIMERVALUE4_GET(x) (((x) & TIMERVALUE4_MASK) >> TIMERVALUE4_SHIFT) 273 #define TIMERVALUE5_MASK 0x0000ffffU 274 #define TIMERVALUE5_SHIFT 0 275 #define TIMERVALUE5(x) ((x) << TIMERVALUE5_SHIFT) 276 #define TIMERVALUE5_GET(x) (((x) & TIMERVALUE5_MASK) >> TIMERVALUE5_SHIFT) 277 278 #define SGE_DEBUG_INDEX 0x10cc 279 #define SGE_DEBUG_DATA_HIGH 0x10d0 280 #define SGE_DEBUG_DATA_LOW 0x10d4 281 #define SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4 282 283 #define S_HP_INT_THRESH 28 284 #define M_HP_INT_THRESH 0xfU 285 #define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH) 286 #define S_LP_INT_THRESH_T5 18 287 #define V_LP_INT_THRESH_T5(x) ((x) << S_LP_INT_THRESH_T5) 288 #define M_LP_COUNT_T5 0x3ffffU 289 #define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT) & M_LP_COUNT_T5) 290 #define M_HP_COUNT 0x7ffU 291 #define S_HP_COUNT 16 292 #define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT) 293 #define S_LP_INT_THRESH 12 294 #define M_LP_INT_THRESH 0xfU 295 #define M_LP_INT_THRESH_T5 0xfffU 296 #define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH) 297 #define M_LP_COUNT 0x7ffU 298 #define S_LP_COUNT 0 299 #define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT) 300 #define A_SGE_DBFIFO_STATUS 0x10a4 301 302 #define SGE_STAT_TOTAL 0x10e4 303 #define SGE_STAT_MATCH 0x10e8 304 305 #define SGE_STAT_CFG 0x10ec 306 #define S_STATSOURCE_T5 9 307 #define STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5) 308 309 #define SGE_DBFIFO_STATUS2 0x1118 310 #define M_HP_COUNT_T5 0x3ffU 311 #define G_HP_COUNT_T5(x) ((x) & M_HP_COUNT_T5) 312 #define S_HP_INT_THRESH_T5 10 313 #define M_HP_INT_THRESH_T5 0xfU 314 #define V_HP_INT_THRESH_T5(x) ((x) << S_HP_INT_THRESH_T5) 315 316 #define S_ENABLE_DROP 13 317 #define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP) 318 #define F_ENABLE_DROP V_ENABLE_DROP(1U) 319 #define S_DROPPED_DB 0 320 #define V_DROPPED_DB(x) ((x) << S_DROPPED_DB) 321 #define F_DROPPED_DB V_DROPPED_DB(1U) 322 #define A_SGE_DOORBELL_CONTROL 0x10a8 323 324 #define A_SGE_CTXT_CMD 0x11fc 325 #define A_SGE_DBQ_CTXT_BADDR 0x1084 326 327 #define PCIE_PF_CFG 0x40 328 #define AIVEC(x) ((x) << 4) 329 #define AIVEC_MASK 0x3ffU 330 331 #define PCIE_PF_CLI 0x44 332 #define PCIE_INT_CAUSE 0x3004 333 #define UNXSPLCPLERR 0x20000000U 334 #define PCIEPINT 0x10000000U 335 #define PCIESINT 0x08000000U 336 #define RPLPERR 0x04000000U 337 #define RXWRPERR 0x02000000U 338 #define RXCPLPERR 0x01000000U 339 #define PIOTAGPERR 0x00800000U 340 #define MATAGPERR 0x00400000U 341 #define INTXCLRPERR 0x00200000U 342 #define FIDPERR 0x00100000U 343 #define CFGSNPPERR 0x00080000U 344 #define HRSPPERR 0x00040000U 345 #define HREQPERR 0x00020000U 346 #define HCNTPERR 0x00010000U 347 #define DRSPPERR 0x00008000U 348 #define DREQPERR 0x00004000U 349 #define DCNTPERR 0x00002000U 350 #define CRSPPERR 0x00001000U 351 #define CREQPERR 0x00000800U 352 #define CCNTPERR 0x00000400U 353 #define TARTAGPERR 0x00000200U 354 #define PIOREQPERR 0x00000100U 355 #define PIOCPLPERR 0x00000080U 356 #define MSIXDIPERR 0x00000040U 357 #define MSIXDATAPERR 0x00000020U 358 #define MSIXADDRHPERR 0x00000010U 359 #define MSIXADDRLPERR 0x00000008U 360 #define MSIDATAPERR 0x00000004U 361 #define MSIADDRHPERR 0x00000002U 362 #define MSIADDRLPERR 0x00000001U 363 364 #define READRSPERR 0x20000000U 365 #define TRGT1GRPPERR 0x10000000U 366 #define IPSOTPERR 0x08000000U 367 #define IPRXDATAGRPPERR 0x02000000U 368 #define IPRXHDRGRPPERR 0x01000000U 369 #define MAGRPPERR 0x00400000U 370 #define VFIDPERR 0x00200000U 371 #define HREQWRPERR 0x00010000U 372 #define DREQWRPERR 0x00002000U 373 #define MSTTAGQPERR 0x00000400U 374 #define PIOREQGRPPERR 0x00000100U 375 #define PIOCPLGRPPERR 0x00000080U 376 #define MSIXSTIPERR 0x00000004U 377 #define MSTTIMEOUTPERR 0x00000002U 378 #define MSTGRPPERR 0x00000001U 379 380 #define PCIE_NONFAT_ERR 0x3010 381 #define PCIE_MEM_ACCESS_BASE_WIN 0x3068 382 #define S_PCIEOFST 10 383 #define M_PCIEOFST 0x3fffffU 384 #define GET_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST) 385 #define PCIEOFST_MASK 0xfffffc00U 386 #define BIR_MASK 0x00000300U 387 #define BIR_SHIFT 8 388 #define BIR(x) ((x) << BIR_SHIFT) 389 #define WINDOW_MASK 0x000000ffU 390 #define WINDOW_SHIFT 0 391 #define WINDOW(x) ((x) << WINDOW_SHIFT) 392 #define PCIE_MEM_ACCESS_OFFSET 0x306c 393 394 #define S_PFNUM 0 395 #define V_PFNUM(x) ((x) << S_PFNUM) 396 397 #define PCIE_FW 0x30b8 398 #define PCIE_FW_ERR 0x80000000U 399 #define PCIE_FW_INIT 0x40000000U 400 #define PCIE_FW_HALT 0x20000000U 401 #define PCIE_FW_MASTER_VLD 0x00008000U 402 #define PCIE_FW_MASTER(x) ((x) << 12) 403 #define PCIE_FW_MASTER_MASK 0x7 404 #define PCIE_FW_MASTER_GET(x) (((x) >> 12) & PCIE_FW_MASTER_MASK) 405 406 #define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908 407 #define RNPP 0x80000000U 408 #define RPCP 0x20000000U 409 #define RCIP 0x08000000U 410 #define RCCP 0x04000000U 411 #define RFTP 0x00800000U 412 #define PTRP 0x00100000U 413 414 #define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS 0x59a4 415 #define TPCP 0x40000000U 416 #define TNPP 0x20000000U 417 #define TFTP 0x10000000U 418 #define TCAP 0x08000000U 419 #define TCIP 0x04000000U 420 #define RCAP 0x02000000U 421 #define PLUP 0x00800000U 422 #define PLDN 0x00400000U 423 #define OTDD 0x00200000U 424 #define GTRP 0x00100000U 425 #define RDPE 0x00040000U 426 #define TDCE 0x00020000U 427 #define TDUE 0x00010000U 428 429 #define MC_INT_CAUSE 0x7518 430 #define ECC_UE_INT_CAUSE 0x00000004U 431 #define ECC_CE_INT_CAUSE 0x00000002U 432 #define PERR_INT_CAUSE 0x00000001U 433 434 #define MC_ECC_STATUS 0x751c 435 #define ECC_CECNT_MASK 0xffff0000U 436 #define ECC_CECNT_SHIFT 16 437 #define ECC_CECNT(x) ((x) << ECC_CECNT_SHIFT) 438 #define ECC_CECNT_GET(x) (((x) & ECC_CECNT_MASK) >> ECC_CECNT_SHIFT) 439 #define ECC_UECNT_MASK 0x0000ffffU 440 #define ECC_UECNT_SHIFT 0 441 #define ECC_UECNT(x) ((x) << ECC_UECNT_SHIFT) 442 #define ECC_UECNT_GET(x) (((x) & ECC_UECNT_MASK) >> ECC_UECNT_SHIFT) 443 444 #define MC_BIST_CMD 0x7600 445 #define START_BIST 0x80000000U 446 #define BIST_CMD_GAP_MASK 0x0000ff00U 447 #define BIST_CMD_GAP_SHIFT 8 448 #define BIST_CMD_GAP(x) ((x) << BIST_CMD_GAP_SHIFT) 449 #define BIST_OPCODE_MASK 0x00000003U 450 #define BIST_OPCODE_SHIFT 0 451 #define BIST_OPCODE(x) ((x) << BIST_OPCODE_SHIFT) 452 453 #define MC_BIST_CMD_ADDR 0x7604 454 #define MC_BIST_CMD_LEN 0x7608 455 #define MC_BIST_DATA_PATTERN 0x760c 456 #define BIST_DATA_TYPE_MASK 0x0000000fU 457 #define BIST_DATA_TYPE_SHIFT 0 458 #define BIST_DATA_TYPE(x) ((x) << BIST_DATA_TYPE_SHIFT) 459 460 #define MC_BIST_STATUS_RDATA 0x7688 461 462 #define MA_EDRAM0_BAR 0x77c0 463 #define MA_EDRAM1_BAR 0x77c4 464 #define EDRAM_SIZE_MASK 0xfffU 465 #define EDRAM_SIZE_GET(x) ((x) & EDRAM_SIZE_MASK) 466 467 #define MA_EXT_MEMORY_BAR 0x77c8 468 #define EXT_MEM_SIZE_MASK 0x00000fffU 469 #define EXT_MEM_SIZE_SHIFT 0 470 #define EXT_MEM_SIZE_GET(x) (((x) & EXT_MEM_SIZE_MASK) >> EXT_MEM_SIZE_SHIFT) 471 472 #define MA_TARGET_MEM_ENABLE 0x77d8 473 #define EXT_MEM1_ENABLE 0x00000010U 474 #define EXT_MEM_ENABLE 0x00000004U 475 #define EDRAM1_ENABLE 0x00000002U 476 #define EDRAM0_ENABLE 0x00000001U 477 478 #define MA_INT_CAUSE 0x77e0 479 #define MEM_PERR_INT_CAUSE 0x00000002U 480 #define MEM_WRAP_INT_CAUSE 0x00000001U 481 482 #define MA_INT_WRAP_STATUS 0x77e4 483 #define MEM_WRAP_ADDRESS_MASK 0xfffffff0U 484 #define MEM_WRAP_ADDRESS_SHIFT 4 485 #define MEM_WRAP_ADDRESS_GET(x) (((x) & MEM_WRAP_ADDRESS_MASK) >> MEM_WRAP_ADDRESS_SHIFT) 486 #define MEM_WRAP_CLIENT_NUM_MASK 0x0000000fU 487 #define MEM_WRAP_CLIENT_NUM_SHIFT 0 488 #define MEM_WRAP_CLIENT_NUM_GET(x) (((x) & MEM_WRAP_CLIENT_NUM_MASK) >> MEM_WRAP_CLIENT_NUM_SHIFT) 489 #define MA_PCIE_FW 0x30b8 490 #define MA_PARITY_ERROR_STATUS 0x77f4 491 492 #define MA_EXT_MEMORY1_BAR 0x7808 493 #define EDC_0_BASE_ADDR 0x7900 494 495 #define EDC_BIST_CMD 0x7904 496 #define EDC_BIST_CMD_ADDR 0x7908 497 #define EDC_BIST_CMD_LEN 0x790c 498 #define EDC_BIST_DATA_PATTERN 0x7910 499 #define EDC_BIST_STATUS_RDATA 0x7928 500 #define EDC_INT_CAUSE 0x7978 501 #define ECC_UE_PAR 0x00000020U 502 #define ECC_CE_PAR 0x00000010U 503 #define PERR_PAR_CAUSE 0x00000008U 504 505 #define EDC_ECC_STATUS 0x797c 506 507 #define EDC_1_BASE_ADDR 0x7980 508 509 #define CIM_BOOT_CFG 0x7b00 510 #define BOOTADDR_MASK 0xffffff00U 511 #define UPCRST 0x1U 512 513 #define CIM_PF_MAILBOX_DATA 0x240 514 #define CIM_PF_MAILBOX_CTRL 0x280 515 #define MBMSGVALID 0x00000008U 516 #define MBINTREQ 0x00000004U 517 #define MBOWNER_MASK 0x00000003U 518 #define MBOWNER_SHIFT 0 519 #define MBOWNER(x) ((x) << MBOWNER_SHIFT) 520 #define MBOWNER_GET(x) (((x) & MBOWNER_MASK) >> MBOWNER_SHIFT) 521 522 #define CIM_PF_HOST_INT_ENABLE 0x288 523 #define MBMSGRDYINTEN(x) ((x) << 19) 524 525 #define CIM_PF_HOST_INT_CAUSE 0x28c 526 #define MBMSGRDYINT 0x00080000U 527 528 #define CIM_HOST_INT_CAUSE 0x7b2c 529 #define TIEQOUTPARERRINT 0x00100000U 530 #define TIEQINPARERRINT 0x00080000U 531 #define MBHOSTPARERR 0x00040000U 532 #define MBUPPARERR 0x00020000U 533 #define IBQPARERR 0x0001f800U 534 #define IBQTP0PARERR 0x00010000U 535 #define IBQTP1PARERR 0x00008000U 536 #define IBQULPPARERR 0x00004000U 537 #define IBQSGELOPARERR 0x00002000U 538 #define IBQSGEHIPARERR 0x00001000U 539 #define IBQNCSIPARERR 0x00000800U 540 #define OBQPARERR 0x000007e0U 541 #define OBQULP0PARERR 0x00000400U 542 #define OBQULP1PARERR 0x00000200U 543 #define OBQULP2PARERR 0x00000100U 544 #define OBQULP3PARERR 0x00000080U 545 #define OBQSGEPARERR 0x00000040U 546 #define OBQNCSIPARERR 0x00000020U 547 #define PREFDROPINT 0x00000002U 548 #define UPACCNONZERO 0x00000001U 549 550 #define CIM_HOST_UPACC_INT_CAUSE 0x7b34 551 #define EEPROMWRINT 0x40000000U 552 #define TIMEOUTMAINT 0x20000000U 553 #define TIMEOUTINT 0x10000000U 554 #define RSPOVRLOOKUPINT 0x08000000U 555 #define REQOVRLOOKUPINT 0x04000000U 556 #define BLKWRPLINT 0x02000000U 557 #define BLKRDPLINT 0x01000000U 558 #define SGLWRPLINT 0x00800000U 559 #define SGLRDPLINT 0x00400000U 560 #define BLKWRCTLINT 0x00200000U 561 #define BLKRDCTLINT 0x00100000U 562 #define SGLWRCTLINT 0x00080000U 563 #define SGLRDCTLINT 0x00040000U 564 #define BLKWREEPROMINT 0x00020000U 565 #define BLKRDEEPROMINT 0x00010000U 566 #define SGLWREEPROMINT 0x00008000U 567 #define SGLRDEEPROMINT 0x00004000U 568 #define BLKWRFLASHINT 0x00002000U 569 #define BLKRDFLASHINT 0x00001000U 570 #define SGLWRFLASHINT 0x00000800U 571 #define SGLRDFLASHINT 0x00000400U 572 #define BLKWRBOOTINT 0x00000200U 573 #define BLKRDBOOTINT 0x00000100U 574 #define SGLWRBOOTINT 0x00000080U 575 #define SGLRDBOOTINT 0x00000040U 576 #define ILLWRBEINT 0x00000020U 577 #define ILLRDBEINT 0x00000010U 578 #define ILLRDINT 0x00000008U 579 #define ILLWRINT 0x00000004U 580 #define ILLTRANSINT 0x00000002U 581 #define RSVDSPACEINT 0x00000001U 582 583 #define TP_OUT_CONFIG 0x7d04 584 #define VLANEXTENABLE_MASK 0x0000f000U 585 #define VLANEXTENABLE_SHIFT 12 586 587 #define TP_GLOBAL_CONFIG 0x7d08 588 #define FIVETUPLELOOKUP_SHIFT 17 589 #define FIVETUPLELOOKUP_MASK 0x00060000U 590 #define FIVETUPLELOOKUP(x) ((x) << FIVETUPLELOOKUP_SHIFT) 591 #define FIVETUPLELOOKUP_GET(x) (((x) & FIVETUPLELOOKUP_MASK) >> \ 592 FIVETUPLELOOKUP_SHIFT) 593 594 #define TP_PARA_REG2 0x7d68 595 #define MAXRXDATA_MASK 0xffff0000U 596 #define MAXRXDATA_SHIFT 16 597 #define MAXRXDATA_GET(x) (((x) & MAXRXDATA_MASK) >> MAXRXDATA_SHIFT) 598 599 #define TP_TIMER_RESOLUTION 0x7d90 600 #define TIMERRESOLUTION_MASK 0x00ff0000U 601 #define TIMERRESOLUTION_SHIFT 16 602 #define TIMERRESOLUTION_GET(x) (((x) & TIMERRESOLUTION_MASK) >> TIMERRESOLUTION_SHIFT) 603 #define DELAYEDACKRESOLUTION_MASK 0x000000ffU 604 #define DELAYEDACKRESOLUTION_SHIFT 0 605 #define DELAYEDACKRESOLUTION_GET(x) \ 606 (((x) & DELAYEDACKRESOLUTION_MASK) >> DELAYEDACKRESOLUTION_SHIFT) 607 608 #define TP_SHIFT_CNT 0x7dc0 609 #define SYNSHIFTMAX_SHIFT 24 610 #define SYNSHIFTMAX_MASK 0xff000000U 611 #define SYNSHIFTMAX(x) ((x) << SYNSHIFTMAX_SHIFT) 612 #define SYNSHIFTMAX_GET(x) (((x) & SYNSHIFTMAX_MASK) >> \ 613 SYNSHIFTMAX_SHIFT) 614 #define RXTSHIFTMAXR1_SHIFT 20 615 #define RXTSHIFTMAXR1_MASK 0x00f00000U 616 #define RXTSHIFTMAXR1(x) ((x) << RXTSHIFTMAXR1_SHIFT) 617 #define RXTSHIFTMAXR1_GET(x) (((x) & RXTSHIFTMAXR1_MASK) >> \ 618 RXTSHIFTMAXR1_SHIFT) 619 #define RXTSHIFTMAXR2_SHIFT 16 620 #define RXTSHIFTMAXR2_MASK 0x000f0000U 621 #define RXTSHIFTMAXR2(x) ((x) << RXTSHIFTMAXR2_SHIFT) 622 #define RXTSHIFTMAXR2_GET(x) (((x) & RXTSHIFTMAXR2_MASK) >> \ 623 RXTSHIFTMAXR2_SHIFT) 624 #define PERSHIFTBACKOFFMAX_SHIFT 12 625 #define PERSHIFTBACKOFFMAX_MASK 0x0000f000U 626 #define PERSHIFTBACKOFFMAX(x) ((x) << PERSHIFTBACKOFFMAX_SHIFT) 627 #define PERSHIFTBACKOFFMAX_GET(x) (((x) & PERSHIFTBACKOFFMAX_MASK) >> \ 628 PERSHIFTBACKOFFMAX_SHIFT) 629 #define PERSHIFTMAX_SHIFT 8 630 #define PERSHIFTMAX_MASK 0x00000f00U 631 #define PERSHIFTMAX(x) ((x) << PERSHIFTMAX_SHIFT) 632 #define PERSHIFTMAX_GET(x) (((x) & PERSHIFTMAX_MASK) >> \ 633 PERSHIFTMAX_SHIFT) 634 #define KEEPALIVEMAXR1_SHIFT 4 635 #define KEEPALIVEMAXR1_MASK 0x000000f0U 636 #define KEEPALIVEMAXR1(x) ((x) << KEEPALIVEMAXR1_SHIFT) 637 #define KEEPALIVEMAXR1_GET(x) (((x) & KEEPALIVEMAXR1_MASK) >> \ 638 KEEPALIVEMAXR1_SHIFT) 639 #define KEEPALIVEMAXR2_SHIFT 0 640 #define KEEPALIVEMAXR2_MASK 0x0000000fU 641 #define KEEPALIVEMAXR2(x) ((x) << KEEPALIVEMAXR2_SHIFT) 642 #define KEEPALIVEMAXR2_GET(x) (((x) & KEEPALIVEMAXR2_MASK) >> \ 643 KEEPALIVEMAXR2_SHIFT) 644 645 #define TP_CCTRL_TABLE 0x7ddc 646 #define TP_MTU_TABLE 0x7de4 647 #define MTUINDEX_MASK 0xff000000U 648 #define MTUINDEX_SHIFT 24 649 #define MTUINDEX(x) ((x) << MTUINDEX_SHIFT) 650 #define MTUWIDTH_MASK 0x000f0000U 651 #define MTUWIDTH_SHIFT 16 652 #define MTUWIDTH(x) ((x) << MTUWIDTH_SHIFT) 653 #define MTUWIDTH_GET(x) (((x) & MTUWIDTH_MASK) >> MTUWIDTH_SHIFT) 654 #define MTUVALUE_MASK 0x00003fffU 655 #define MTUVALUE_SHIFT 0 656 #define MTUVALUE(x) ((x) << MTUVALUE_SHIFT) 657 #define MTUVALUE_GET(x) (((x) & MTUVALUE_MASK) >> MTUVALUE_SHIFT) 658 659 #define TP_RSS_LKP_TABLE 0x7dec 660 #define LKPTBLROWVLD 0x80000000U 661 #define LKPTBLQUEUE1_MASK 0x000ffc00U 662 #define LKPTBLQUEUE1_SHIFT 10 663 #define LKPTBLQUEUE1(x) ((x) << LKPTBLQUEUE1_SHIFT) 664 #define LKPTBLQUEUE1_GET(x) (((x) & LKPTBLQUEUE1_MASK) >> LKPTBLQUEUE1_SHIFT) 665 #define LKPTBLQUEUE0_MASK 0x000003ffU 666 #define LKPTBLQUEUE0_SHIFT 0 667 #define LKPTBLQUEUE0(x) ((x) << LKPTBLQUEUE0_SHIFT) 668 #define LKPTBLQUEUE0_GET(x) (((x) & LKPTBLQUEUE0_MASK) >> LKPTBLQUEUE0_SHIFT) 669 670 #define TP_PIO_ADDR 0x7e40 671 #define TP_PIO_DATA 0x7e44 672 #define TP_MIB_INDEX 0x7e50 673 #define TP_MIB_DATA 0x7e54 674 #define TP_INT_CAUSE 0x7e74 675 #define FLMTXFLSTEMPTY 0x40000000U 676 677 #define TP_VLAN_PRI_MAP 0x140 678 #define FRAGMENTATION_SHIFT 9 679 #define FRAGMENTATION_MASK 0x00000200U 680 #define MPSHITTYPE_MASK 0x00000100U 681 #define MACMATCH_MASK 0x00000080U 682 #define ETHERTYPE_MASK 0x00000040U 683 #define PROTOCOL_MASK 0x00000020U 684 #define TOS_MASK 0x00000010U 685 #define VLAN_MASK 0x00000008U 686 #define VNIC_ID_MASK 0x00000004U 687 #define PORT_MASK 0x00000002U 688 #define FCOE_SHIFT 0 689 #define FCOE_MASK 0x00000001U 690 691 #define TP_INGRESS_CONFIG 0x141 692 #define VNIC 0x00000800U 693 #define CSUM_HAS_PSEUDO_HDR 0x00000400U 694 #define RM_OVLAN 0x00000200U 695 #define LOOKUPEVERYPKT 0x00000100U 696 697 #define TP_MIB_MAC_IN_ERR_0 0x0 698 #define TP_MIB_TCP_OUT_RST 0xc 699 #define TP_MIB_TCP_IN_SEG_HI 0x10 700 #define TP_MIB_TCP_IN_SEG_LO 0x11 701 #define TP_MIB_TCP_OUT_SEG_HI 0x12 702 #define TP_MIB_TCP_OUT_SEG_LO 0x13 703 #define TP_MIB_TCP_RXT_SEG_HI 0x14 704 #define TP_MIB_TCP_RXT_SEG_LO 0x15 705 #define TP_MIB_TNL_CNG_DROP_0 0x18 706 #define TP_MIB_TCP_V6IN_ERR_0 0x28 707 #define TP_MIB_TCP_V6OUT_RST 0x2c 708 #define TP_MIB_OFD_ARP_DROP 0x36 709 #define TP_MIB_TNL_DROP_0 0x44 710 #define TP_MIB_OFD_VLN_DROP_0 0x58 711 712 #define ULP_TX_INT_CAUSE 0x8dcc 713 #define PBL_BOUND_ERR_CH3 0x80000000U 714 #define PBL_BOUND_ERR_CH2 0x40000000U 715 #define PBL_BOUND_ERR_CH1 0x20000000U 716 #define PBL_BOUND_ERR_CH0 0x10000000U 717 718 #define PM_RX_INT_CAUSE 0x8fdc 719 #define ZERO_E_CMD_ERROR 0x00400000U 720 #define PMRX_FRAMING_ERROR 0x003ffff0U 721 #define OCSPI_PAR_ERROR 0x00000008U 722 #define DB_OPTIONS_PAR_ERROR 0x00000004U 723 #define IESPI_PAR_ERROR 0x00000002U 724 #define E_PCMD_PAR_ERROR 0x00000001U 725 726 #define PM_TX_INT_CAUSE 0x8ffc 727 #define PCMD_LEN_OVFL0 0x80000000U 728 #define PCMD_LEN_OVFL1 0x40000000U 729 #define PCMD_LEN_OVFL2 0x20000000U 730 #define ZERO_C_CMD_ERROR 0x10000000U 731 #define PMTX_FRAMING_ERROR 0x0ffffff0U 732 #define OESPI_PAR_ERROR 0x00000008U 733 #define ICSPI_PAR_ERROR 0x00000002U 734 #define C_PCMD_PAR_ERROR 0x00000001U 735 736 #define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400 737 #define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404 738 #define MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408 739 #define MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c 740 #define MPS_PORT_STAT_TX_PORT_BCAST_L 0x410 741 #define MPS_PORT_STAT_TX_PORT_BCAST_H 0x414 742 #define MPS_PORT_STAT_TX_PORT_MCAST_L 0x418 743 #define MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c 744 #define MPS_PORT_STAT_TX_PORT_UCAST_L 0x420 745 #define MPS_PORT_STAT_TX_PORT_UCAST_H 0x424 746 #define MPS_PORT_STAT_TX_PORT_ERROR_L 0x428 747 #define MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c 748 #define MPS_PORT_STAT_TX_PORT_64B_L 0x430 749 #define MPS_PORT_STAT_TX_PORT_64B_H 0x434 750 #define MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438 751 #define MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c 752 #define MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440 753 #define MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444 754 #define MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448 755 #define MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c 756 #define MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450 757 #define MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454 758 #define MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458 759 #define MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c 760 #define MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460 761 #define MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464 762 #define MPS_PORT_STAT_TX_PORT_DROP_L 0x468 763 #define MPS_PORT_STAT_TX_PORT_DROP_H 0x46c 764 #define MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470 765 #define MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474 766 #define MPS_PORT_STAT_TX_PORT_PPP0_L 0x478 767 #define MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c 768 #define MPS_PORT_STAT_TX_PORT_PPP1_L 0x480 769 #define MPS_PORT_STAT_TX_PORT_PPP1_H 0x484 770 #define MPS_PORT_STAT_TX_PORT_PPP2_L 0x488 771 #define MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c 772 #define MPS_PORT_STAT_TX_PORT_PPP3_L 0x490 773 #define MPS_PORT_STAT_TX_PORT_PPP3_H 0x494 774 #define MPS_PORT_STAT_TX_PORT_PPP4_L 0x498 775 #define MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c 776 #define MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0 777 #define MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4 778 #define MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8 779 #define MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac 780 #define MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0 781 #define MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4 782 #define MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0 783 #define MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4 784 #define MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8 785 #define MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc 786 #define MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0 787 #define MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4 788 #define MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8 789 #define MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc 790 #define MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0 791 #define MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4 792 #define MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8 793 #define MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec 794 #define MPS_PORT_STAT_LB_PORT_64B_L 0x4f0 795 #define MPS_PORT_STAT_LB_PORT_64B_H 0x4f4 796 #define MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8 797 #define MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc 798 #define MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500 799 #define MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504 800 #define MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508 801 #define MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c 802 #define MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510 803 #define MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514 804 #define MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518 805 #define MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c 806 #define MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520 807 #define MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524 808 #define MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528 809 #define MPS_PORT_STAT_RX_PORT_BYTES_L 0x540 810 #define MPS_PORT_STAT_RX_PORT_BYTES_H 0x544 811 #define MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548 812 #define MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c 813 #define MPS_PORT_STAT_RX_PORT_BCAST_L 0x550 814 #define MPS_PORT_STAT_RX_PORT_BCAST_H 0x554 815 #define MPS_PORT_STAT_RX_PORT_MCAST_L 0x558 816 #define MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c 817 #define MPS_PORT_STAT_RX_PORT_UCAST_L 0x560 818 #define MPS_PORT_STAT_RX_PORT_UCAST_H 0x564 819 #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568 820 #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c 821 #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570 822 #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574 823 #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578 824 #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c 825 #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580 826 #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584 827 #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588 828 #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c 829 #define MPS_PORT_STAT_RX_PORT_64B_L 0x590 830 #define MPS_PORT_STAT_RX_PORT_64B_H 0x594 831 #define MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598 832 #define MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c 833 #define MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0 834 #define MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4 835 #define MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8 836 #define MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac 837 #define MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0 838 #define MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4 839 #define MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8 840 #define MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc 841 #define MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0 842 #define MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4 843 #define MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8 844 #define MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc 845 #define MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0 846 #define MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4 847 #define MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8 848 #define MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc 849 #define MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0 850 #define MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4 851 #define MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8 852 #define MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec 853 #define MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0 854 #define MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4 855 #define MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8 856 #define MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc 857 #define MPS_PORT_STAT_RX_PORT_PPP6_L 0x600 858 #define MPS_PORT_STAT_RX_PORT_PPP6_H 0x604 859 #define MPS_PORT_STAT_RX_PORT_PPP7_L 0x608 860 #define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c 861 #define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610 862 #define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614 863 #define MAC_PORT_CFG2 0x818 864 #define MAC_PORT_MAGIC_MACID_LO 0x824 865 #define MAC_PORT_MAGIC_MACID_HI 0x828 866 #define MAC_PORT_EPIO_DATA0 0x8c0 867 #define MAC_PORT_EPIO_DATA1 0x8c4 868 #define MAC_PORT_EPIO_DATA2 0x8c8 869 #define MAC_PORT_EPIO_DATA3 0x8cc 870 #define MAC_PORT_EPIO_OP 0x8d0 871 872 #define MPS_CMN_CTL 0x9000 873 #define NUMPORTS_MASK 0x00000003U 874 #define NUMPORTS_SHIFT 0 875 #define NUMPORTS_GET(x) (((x) & NUMPORTS_MASK) >> NUMPORTS_SHIFT) 876 877 #define MPS_INT_CAUSE 0x9008 878 #define STATINT 0x00000020U 879 #define TXINT 0x00000010U 880 #define RXINT 0x00000008U 881 #define TRCINT 0x00000004U 882 #define CLSINT 0x00000002U 883 #define PLINT 0x00000001U 884 885 #define MPS_TX_INT_CAUSE 0x9408 886 #define PORTERR 0x00010000U 887 #define FRMERR 0x00008000U 888 #define SECNTERR 0x00004000U 889 #define BUBBLE 0x00002000U 890 #define TXDESCFIFO 0x00001e00U 891 #define TXDATAFIFO 0x000001e0U 892 #define NCSIFIFO 0x00000010U 893 #define TPFIFO 0x0000000fU 894 895 #define MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614 896 #define MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620 897 #define MPS_STAT_PERR_INT_CAUSE_RX_FIFO 0x962c 898 899 #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640 900 #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644 901 #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648 902 #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c 903 #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650 904 #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654 905 #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658 906 #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c 907 #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660 908 #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664 909 #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668 910 #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c 911 #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670 912 #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674 913 #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678 914 #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c 915 #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680 916 #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684 917 #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688 918 #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c 919 #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690 920 #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694 921 #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698 922 #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c 923 #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0 924 #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4 925 #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8 926 #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac 927 #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0 928 #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4 929 #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8 930 #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc 931 #define MPS_TRC_CFG 0x9800 932 #define TRCFIFOEMPTY 0x00000010U 933 #define TRCIGNOREDROPINPUT 0x00000008U 934 #define TRCKEEPDUPLICATES 0x00000004U 935 #define TRCEN 0x00000002U 936 #define TRCMULTIFILTER 0x00000001U 937 938 #define MPS_TRC_RSS_CONTROL 0x9808 939 #define RSSCONTROL_MASK 0x00ff0000U 940 #define RSSCONTROL_SHIFT 16 941 #define RSSCONTROL(x) ((x) << RSSCONTROL_SHIFT) 942 #define QUEUENUMBER_MASK 0x0000ffffU 943 #define QUEUENUMBER_SHIFT 0 944 #define QUEUENUMBER(x) ((x) << QUEUENUMBER_SHIFT) 945 946 #define MPS_TRC_FILTER_MATCH_CTL_A 0x9810 947 #define TFINVERTMATCH 0x01000000U 948 #define TFPKTTOOLARGE 0x00800000U 949 #define TFEN 0x00400000U 950 #define TFPORT_MASK 0x003c0000U 951 #define TFPORT_SHIFT 18 952 #define TFPORT(x) ((x) << TFPORT_SHIFT) 953 #define TFPORT_GET(x) (((x) & TFPORT_MASK) >> TFPORT_SHIFT) 954 #define TFDROP 0x00020000U 955 #define TFSOPEOPERR 0x00010000U 956 #define TFLENGTH_MASK 0x00001f00U 957 #define TFLENGTH_SHIFT 8 958 #define TFLENGTH(x) ((x) << TFLENGTH_SHIFT) 959 #define TFLENGTH_GET(x) (((x) & TFLENGTH_MASK) >> TFLENGTH_SHIFT) 960 #define TFOFFSET_MASK 0x0000001fU 961 #define TFOFFSET_SHIFT 0 962 #define TFOFFSET(x) ((x) << TFOFFSET_SHIFT) 963 #define TFOFFSET_GET(x) (((x) & TFOFFSET_MASK) >> TFOFFSET_SHIFT) 964 965 #define MPS_TRC_FILTER_MATCH_CTL_B 0x9820 966 #define TFMINPKTSIZE_MASK 0x01ff0000U 967 #define TFMINPKTSIZE_SHIFT 16 968 #define TFMINPKTSIZE(x) ((x) << TFMINPKTSIZE_SHIFT) 969 #define TFMINPKTSIZE_GET(x) (((x) & TFMINPKTSIZE_MASK) >> TFMINPKTSIZE_SHIFT) 970 #define TFCAPTUREMAX_MASK 0x00003fffU 971 #define TFCAPTUREMAX_SHIFT 0 972 #define TFCAPTUREMAX(x) ((x) << TFCAPTUREMAX_SHIFT) 973 #define TFCAPTUREMAX_GET(x) (((x) & TFCAPTUREMAX_MASK) >> TFCAPTUREMAX_SHIFT) 974 975 #define MPS_TRC_INT_CAUSE 0x985c 976 #define MISCPERR 0x00000100U 977 #define PKTFIFO 0x000000f0U 978 #define FILTMEM 0x0000000fU 979 980 #define MPS_TRC_FILTER0_MATCH 0x9c00 981 #define MPS_TRC_FILTER0_DONT_CARE 0x9c80 982 #define MPS_TRC_FILTER1_MATCH 0x9d00 983 #define MPS_CLS_INT_CAUSE 0xd028 984 #define PLERRENB 0x00000008U 985 #define HASHSRAM 0x00000004U 986 #define MATCHTCAM 0x00000002U 987 #define MATCHSRAM 0x00000001U 988 989 #define MPS_RX_PERR_INT_CAUSE 0x11074 990 991 #define CPL_INTR_CAUSE 0x19054 992 #define CIM_OP_MAP_PERR 0x00000020U 993 #define CIM_OVFL_ERROR 0x00000010U 994 #define TP_FRAMING_ERROR 0x00000008U 995 #define SGE_FRAMING_ERROR 0x00000004U 996 #define CIM_FRAMING_ERROR 0x00000002U 997 #define ZERO_SWITCH_ERROR 0x00000001U 998 999 #define SMB_INT_CAUSE 0x19090 1000 #define MSTTXFIFOPARINT 0x00200000U 1001 #define MSTRXFIFOPARINT 0x00100000U 1002 #define SLVFIFOPARINT 0x00080000U 1003 1004 #define ULP_RX_INT_CAUSE 0x19158 1005 #define ULP_RX_ISCSI_TAGMASK 0x19164 1006 #define ULP_RX_ISCSI_PSZ 0x19168 1007 #define HPZ3_MASK 0x0f000000U 1008 #define HPZ3_SHIFT 24 1009 #define HPZ3(x) ((x) << HPZ3_SHIFT) 1010 #define HPZ2_MASK 0x000f0000U 1011 #define HPZ2_SHIFT 16 1012 #define HPZ2(x) ((x) << HPZ2_SHIFT) 1013 #define HPZ1_MASK 0x00000f00U 1014 #define HPZ1_SHIFT 8 1015 #define HPZ1(x) ((x) << HPZ1_SHIFT) 1016 #define HPZ0_MASK 0x0000000fU 1017 #define HPZ0_SHIFT 0 1018 #define HPZ0(x) ((x) << HPZ0_SHIFT) 1019 1020 #define ULP_RX_TDDP_PSZ 0x19178 1021 1022 #define SF_DATA 0x193f8 1023 #define SF_OP 0x193fc 1024 #define SF_BUSY 0x80000000U 1025 #define SF_LOCK 0x00000010U 1026 #define SF_CONT 0x00000008U 1027 #define BYTECNT_MASK 0x00000006U 1028 #define BYTECNT_SHIFT 1 1029 #define BYTECNT(x) ((x) << BYTECNT_SHIFT) 1030 #define OP_WR 0x00000001U 1031 1032 #define PL_PF_INT_CAUSE 0x3c0 1033 #define PFSW 0x00000008U 1034 #define PFSGE 0x00000004U 1035 #define PFCIM 0x00000002U 1036 #define PFMPS 0x00000001U 1037 1038 #define PL_PF_INT_ENABLE 0x3c4 1039 #define PL_PF_CTL 0x3c8 1040 #define SWINT 0x00000001U 1041 1042 #define PL_WHOAMI 0x19400 1043 #define SOURCEPF_MASK 0x00000700U 1044 #define SOURCEPF_SHIFT 8 1045 #define SOURCEPF(x) ((x) << SOURCEPF_SHIFT) 1046 #define SOURCEPF_GET(x) (((x) & SOURCEPF_MASK) >> SOURCEPF_SHIFT) 1047 #define ISVF 0x00000080U 1048 #define VFID_MASK 0x0000007fU 1049 #define VFID_SHIFT 0 1050 #define VFID(x) ((x) << VFID_SHIFT) 1051 #define VFID_GET(x) (((x) & VFID_MASK) >> VFID_SHIFT) 1052 1053 #define PL_INT_CAUSE 0x1940c 1054 #define ULP_TX 0x08000000U 1055 #define SGE 0x04000000U 1056 #define HMA 0x02000000U 1057 #define CPL_SWITCH 0x01000000U 1058 #define ULP_RX 0x00800000U 1059 #define PM_RX 0x00400000U 1060 #define PM_TX 0x00200000U 1061 #define MA 0x00100000U 1062 #define TP 0x00080000U 1063 #define LE 0x00040000U 1064 #define EDC1 0x00020000U 1065 #define EDC0 0x00010000U 1066 #define MC 0x00008000U 1067 #define PCIE 0x00004000U 1068 #define PMU 0x00002000U 1069 #define XGMAC_KR1 0x00001000U 1070 #define XGMAC_KR0 0x00000800U 1071 #define XGMAC1 0x00000400U 1072 #define XGMAC0 0x00000200U 1073 #define SMB 0x00000100U 1074 #define SF 0x00000080U 1075 #define PL 0x00000040U 1076 #define NCSI 0x00000020U 1077 #define MPS 0x00000010U 1078 #define MI 0x00000008U 1079 #define DBG 0x00000004U 1080 #define I2CM 0x00000002U 1081 #define CIM 0x00000001U 1082 1083 #define PL_INT_ENABLE 0x19410 1084 #define PL_INT_MAP0 0x19414 1085 #define PL_RST 0x19428 1086 #define PIORST 0x00000002U 1087 #define PIORSTMODE 0x00000001U 1088 1089 #define PL_PL_INT_CAUSE 0x19430 1090 #define FATALPERR 0x00000010U 1091 #define PERRVFID 0x00000001U 1092 1093 #define PL_REV 0x1943c 1094 1095 #define LE_DB_CONFIG 0x19c04 1096 #define HASHEN 0x00100000U 1097 1098 #define LE_DB_SERVER_INDEX 0x19c18 1099 #define LE_DB_ACT_CNT_IPV4 0x19c20 1100 #define LE_DB_ACT_CNT_IPV6 0x19c24 1101 1102 #define LE_DB_INT_CAUSE 0x19c3c 1103 #define REQQPARERR 0x00010000U 1104 #define UNKNOWNCMD 0x00008000U 1105 #define PARITYERR 0x00000040U 1106 #define LIPMISS 0x00000020U 1107 #define LIP0 0x00000010U 1108 1109 #define LE_DB_TID_HASHBASE 0x19df8 1110 1111 #define NCSI_INT_CAUSE 0x1a0d8 1112 #define CIM_DM_PRTY_ERR 0x00000100U 1113 #define MPS_DM_PRTY_ERR 0x00000080U 1114 #define TXFIFO_PRTY_ERR 0x00000002U 1115 #define RXFIFO_PRTY_ERR 0x00000001U 1116 1117 #define XGMAC_PORT_CFG2 0x1018 1118 #define PATEN 0x00040000U 1119 #define MAGICEN 0x00020000U 1120 1121 #define XGMAC_PORT_MAGIC_MACID_LO 0x1024 1122 #define XGMAC_PORT_MAGIC_MACID_HI 0x1028 1123 1124 #define XGMAC_PORT_EPIO_DATA0 0x10c0 1125 #define XGMAC_PORT_EPIO_DATA1 0x10c4 1126 #define XGMAC_PORT_EPIO_DATA2 0x10c8 1127 #define XGMAC_PORT_EPIO_DATA3 0x10cc 1128 #define XGMAC_PORT_EPIO_OP 0x10d0 1129 #define EPIOWR 0x00000100U 1130 #define ADDRESS_MASK 0x000000ffU 1131 #define ADDRESS_SHIFT 0 1132 #define ADDRESS(x) ((x) << ADDRESS_SHIFT) 1133 1134 #define MAC_PORT_INT_CAUSE 0x8dc 1135 #define XGMAC_PORT_INT_CAUSE 0x10dc 1136 1137 #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x7e28 1138 1139 #define A_TP_TX_MOD_CHANNEL_WEIGHT 0x7e34 1140 1141 #define S_TX_MOD_QUEUE_REQ_MAP 0 1142 #define M_TX_MOD_QUEUE_REQ_MAP 0xffffU 1143 #define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP) 1144 1145 #define A_TP_TX_MOD_QUEUE_WEIGHT0 0x7e30 1146 1147 #define S_TX_MODQ_WEIGHT3 24 1148 #define M_TX_MODQ_WEIGHT3 0xffU 1149 #define V_TX_MODQ_WEIGHT3(x) ((x) << S_TX_MODQ_WEIGHT3) 1150 1151 #define S_TX_MODQ_WEIGHT2 16 1152 #define M_TX_MODQ_WEIGHT2 0xffU 1153 #define V_TX_MODQ_WEIGHT2(x) ((x) << S_TX_MODQ_WEIGHT2) 1154 1155 #define S_TX_MODQ_WEIGHT1 8 1156 #define M_TX_MODQ_WEIGHT1 0xffU 1157 #define V_TX_MODQ_WEIGHT1(x) ((x) << S_TX_MODQ_WEIGHT1) 1158 1159 #define S_TX_MODQ_WEIGHT0 0 1160 #define M_TX_MODQ_WEIGHT0 0xffU 1161 #define V_TX_MODQ_WEIGHT0(x) ((x) << S_TX_MODQ_WEIGHT0) 1162 1163 #define A_TP_TX_SCHED_HDR 0x23 1164 1165 #define A_TP_TX_SCHED_FIFO 0x24 1166 1167 #define A_TP_TX_SCHED_PCMD 0x25 1168 1169 #define S_PORT 1 1170 #define V_PORT(x) ((x) << S_PORT) 1171 #define F_PORT V_PORT(1U) 1172 1173 #define NUM_MPS_CLS_SRAM_L_INSTANCES 336 1174 #define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512 1175 1176 #define T5_PORT0_BASE 0x30000 1177 #define T5_PORT_STRIDE 0x4000 1178 #define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE) 1179 #define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg)) 1180 1181 #define MC_0_BASE_ADDR 0x40000 1182 #define MC_1_BASE_ADDR 0x48000 1183 #define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR) 1184 #define MC_REG(reg, idx) (reg + MC_STRIDE * idx) 1185 1186 #define MC_P_BIST_CMD 0x41400 1187 #define MC_P_BIST_CMD_ADDR 0x41404 1188 #define MC_P_BIST_CMD_LEN 0x41408 1189 #define MC_P_BIST_DATA_PATTERN 0x4140c 1190 #define MC_P_BIST_STATUS_RDATA 0x41488 1191 #define EDC_T50_BASE_ADDR 0x50000 1192 #define EDC_H_BIST_CMD 0x50004 1193 #define EDC_H_BIST_CMD_ADDR 0x50008 1194 #define EDC_H_BIST_CMD_LEN 0x5000c 1195 #define EDC_H_BIST_DATA_PATTERN 0x50010 1196 #define EDC_H_BIST_STATUS_RDATA 0x50028 1197 1198 #define EDC_T51_BASE_ADDR 0x50800 1199 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) 1200 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) 1201 1202 #endif /* __T4_REGS_H */ 1203