1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2013 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #ifndef __QLA_DEF_H 8 #define __QLA_DEF_H 9 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/types.h> 13 #include <linux/module.h> 14 #include <linux/list.h> 15 #include <linux/pci.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/sched.h> 18 #include <linux/slab.h> 19 #include <linux/dmapool.h> 20 #include <linux/mempool.h> 21 #include <linux/spinlock.h> 22 #include <linux/completion.h> 23 #include <linux/interrupt.h> 24 #include <linux/workqueue.h> 25 #include <linux/firmware.h> 26 #include <linux/aer.h> 27 #include <linux/mutex.h> 28 29 #include <scsi/scsi.h> 30 #include <scsi/scsi_host.h> 31 #include <scsi/scsi_device.h> 32 #include <scsi/scsi_cmnd.h> 33 #include <scsi/scsi_transport_fc.h> 34 #include <scsi/scsi_bsg_fc.h> 35 36 #include "qla_bsg.h" 37 #include "qla_nx.h" 38 #define QLA2XXX_DRIVER_NAME "qla2xxx" 39 #define QLA2XXX_APIDEV "ql2xapidev" 40 #define QLA2XXX_MANUFACTURER "QLogic Corporation" 41 42 /* 43 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places, 44 * but that's fine as we don't look at the last 24 ones for 45 * ISP2100 HBAs. 46 */ 47 #define MAILBOX_REGISTER_COUNT_2100 8 48 #define MAILBOX_REGISTER_COUNT_2200 24 49 #define MAILBOX_REGISTER_COUNT 32 50 51 #define QLA2200A_RISC_ROM_VER 4 52 #define FPM_2300 6 53 #define FPM_2310 7 54 55 #include "qla_settings.h" 56 57 /* 58 * Data bit definitions 59 */ 60 #define BIT_0 0x1 61 #define BIT_1 0x2 62 #define BIT_2 0x4 63 #define BIT_3 0x8 64 #define BIT_4 0x10 65 #define BIT_5 0x20 66 #define BIT_6 0x40 67 #define BIT_7 0x80 68 #define BIT_8 0x100 69 #define BIT_9 0x200 70 #define BIT_10 0x400 71 #define BIT_11 0x800 72 #define BIT_12 0x1000 73 #define BIT_13 0x2000 74 #define BIT_14 0x4000 75 #define BIT_15 0x8000 76 #define BIT_16 0x10000 77 #define BIT_17 0x20000 78 #define BIT_18 0x40000 79 #define BIT_19 0x80000 80 #define BIT_20 0x100000 81 #define BIT_21 0x200000 82 #define BIT_22 0x400000 83 #define BIT_23 0x800000 84 #define BIT_24 0x1000000 85 #define BIT_25 0x2000000 86 #define BIT_26 0x4000000 87 #define BIT_27 0x8000000 88 #define BIT_28 0x10000000 89 #define BIT_29 0x20000000 90 #define BIT_30 0x40000000 91 #define BIT_31 0x80000000 92 93 #define LSB(x) ((uint8_t)(x)) 94 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) 95 96 #define LSW(x) ((uint16_t)(x)) 97 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) 98 99 #define LSD(x) ((uint32_t)((uint64_t)(x))) 100 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) 101 102 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y))) 103 104 /* 105 * I/O register 106 */ 107 108 #define RD_REG_BYTE(addr) readb(addr) 109 #define RD_REG_WORD(addr) readw(addr) 110 #define RD_REG_DWORD(addr) readl(addr) 111 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr) 112 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr) 113 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr) 114 #define WRT_REG_BYTE(addr, data) writeb(data,addr) 115 #define WRT_REG_WORD(addr, data) writew(data,addr) 116 #define WRT_REG_DWORD(addr, data) writel(data,addr) 117 118 /* 119 * ISP83XX specific remote register addresses 120 */ 121 #define QLA83XX_LED_PORT0 0x00201320 122 #define QLA83XX_LED_PORT1 0x00201328 123 #define QLA83XX_IDC_DEV_STATE 0x22102384 124 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380 125 #define QLA83XX_IDC_MINOR_VERSION 0x22102398 126 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388 127 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c 128 #define QLA83XX_IDC_CONTROL 0x22102390 129 #define QLA83XX_IDC_AUDIT 0x22102394 130 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c 131 #define QLA83XX_DRIVER_LOCKID 0x22102104 132 #define QLA83XX_DRIVER_LOCK 0x8111c028 133 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c 134 #define QLA83XX_FLASH_LOCKID 0x22102100 135 #define QLA83XX_FLASH_LOCK 0x8111c010 136 #define QLA83XX_FLASH_UNLOCK 0x8111c014 137 #define QLA83XX_DEV_PARTINFO1 0x221023e0 138 #define QLA83XX_DEV_PARTINFO2 0x221023e4 139 #define QLA83XX_FW_HEARTBEAT 0x221020b0 140 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8 141 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac 142 143 /* 83XX: Macros defining 8200 AEN Reason codes */ 144 #define IDC_DEVICE_STATE_CHANGE BIT_0 145 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1 146 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2 147 #define IDC_HEARTBEAT_FAILURE BIT_3 148 149 /* 83XX: Macros defining 8200 AEN Error-levels */ 150 #define ERR_LEVEL_NON_FATAL 0x1 151 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2 152 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4 153 154 /* 83XX: Macros for IDC Version */ 155 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01 156 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0 157 158 /* 83XX: Macros for scheduling dpc tasks */ 159 #define QLA83XX_NIC_CORE_RESET 0x1 160 #define QLA83XX_IDC_STATE_HANDLER 0x2 161 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3 162 163 /* 83XX: Macros for defining IDC-Control bits */ 164 #define QLA83XX_IDC_RESET_DISABLED BIT_0 165 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1 166 167 /* 83XX: Macros for different timeouts */ 168 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30 169 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10 170 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ) 171 172 /* 83XX: Macros for defining class in DEV-Partition Info register */ 173 #define QLA83XX_CLASS_TYPE_NONE 0x0 174 #define QLA83XX_CLASS_TYPE_NIC 0x1 175 #define QLA83XX_CLASS_TYPE_FCOE 0x2 176 #define QLA83XX_CLASS_TYPE_ISCSI 0x3 177 178 /* 83XX: Macros for IDC Lock-Recovery stages */ 179 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for 180 * lock-recovery 181 */ 182 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */ 183 184 /* 83XX: Macros for IDC Audit type */ 185 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of 186 * dev-state change to NEED-RESET 187 * or NEED-QUIESCENT 188 */ 189 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of 190 * reset-recovery completion is 191 * second 192 */ 193 194 /* 195 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an 196 * 133Mhz slot. 197 */ 198 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr)) 199 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr)) 200 201 /* 202 * Fibre Channel device definitions. 203 */ 204 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */ 205 #define MAX_FIBRE_DEVICES_2100 512 206 #define MAX_FIBRE_DEVICES_2400 2048 207 #define MAX_FIBRE_DEVICES_LOOP 128 208 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400 209 #define LOOPID_MAP_SIZE (ha->max_fibre_devices) 210 #define MAX_FIBRE_LUNS 0xFFFF 211 #define MAX_HOST_COUNT 16 212 213 /* 214 * Host adapter default definitions. 215 */ 216 #define MAX_BUSES 1 /* We only have one bus today */ 217 #define MIN_LUNS 8 218 #define MAX_LUNS MAX_FIBRE_LUNS 219 #define MAX_CMDS_PER_LUN 255 220 221 /* 222 * Fibre Channel device definitions. 223 */ 224 #define SNS_LAST_LOOP_ID_2100 0xfe 225 #define SNS_LAST_LOOP_ID_2300 0x7ff 226 227 #define LAST_LOCAL_LOOP_ID 0x7d 228 #define SNS_FL_PORT 0x7e 229 #define FABRIC_CONTROLLER 0x7f 230 #define SIMPLE_NAME_SERVER 0x80 231 #define SNS_FIRST_LOOP_ID 0x81 232 #define MANAGEMENT_SERVER 0xfe 233 #define BROADCAST 0xff 234 235 /* 236 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the 237 * valid range of an N-PORT id is 0 through 0x7ef. 238 */ 239 #define NPH_LAST_HANDLE 0x7ef 240 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */ 241 #define NPH_SNS 0x7fc /* FFFFFC */ 242 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */ 243 #define NPH_F_PORT 0x7fe /* FFFFFE */ 244 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */ 245 246 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */ 247 #include "qla_fw.h" 248 /* 249 * Timeout timer counts in seconds 250 */ 251 #define PORT_RETRY_TIME 1 252 #define LOOP_DOWN_TIMEOUT 60 253 #define LOOP_DOWN_TIME 255 /* 240 */ 254 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30) 255 256 #define DEFAULT_OUTSTANDING_COMMANDS 1024 257 #define MIN_OUTSTANDING_COMMANDS 128 258 259 /* ISP request and response entry counts (37-65535) */ 260 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */ 261 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */ 262 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */ 263 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/ 264 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/ 265 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/ 266 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */ 267 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/ 268 269 struct req_que; 270 271 /* 272 * (sd.h is not exported, hence local inclusion) 273 * Data Integrity Field tuple. 274 */ 275 struct sd_dif_tuple { 276 __be16 guard_tag; /* Checksum */ 277 __be16 app_tag; /* Opaque storage */ 278 __be32 ref_tag; /* Target LBA or indirect LBA */ 279 }; 280 281 /* 282 * SCSI Request Block 283 */ 284 struct srb_cmd { 285 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */ 286 uint32_t request_sense_length; 287 uint32_t fw_sense_length; 288 uint8_t *request_sense_ptr; 289 void *ctx; 290 }; 291 292 /* 293 * SRB flag definitions 294 */ 295 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */ 296 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */ 297 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */ 298 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */ 299 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */ 300 301 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */ 302 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID) 303 304 /* 305 * SRB extensions. 306 */ 307 struct srb_iocb { 308 union { 309 struct { 310 uint16_t flags; 311 #define SRB_LOGIN_RETRIED BIT_0 312 #define SRB_LOGIN_COND_PLOGI BIT_1 313 #define SRB_LOGIN_SKIP_PRLI BIT_2 314 uint16_t data[2]; 315 } logio; 316 struct { 317 /* 318 * Values for flags field below are as 319 * defined in tsk_mgmt_entry struct 320 * for control_flags field in qla_fw.h. 321 */ 322 uint32_t flags; 323 uint32_t lun; 324 uint32_t data; 325 struct completion comp; 326 uint32_t comp_status; 327 } tmf; 328 struct { 329 #define SRB_FXDISC_REQ_DMA_VALID BIT_0 330 #define SRB_FXDISC_RESP_DMA_VALID BIT_1 331 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2 332 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3 333 #define FXDISC_TIMEOUT 20 334 uint8_t flags; 335 uint32_t req_len; 336 uint32_t rsp_len; 337 void *req_addr; 338 void *rsp_addr; 339 dma_addr_t req_dma_handle; 340 dma_addr_t rsp_dma_handle; 341 uint32_t adapter_id; 342 uint32_t adapter_id_hi; 343 uint32_t req_func_type; 344 uint32_t req_data; 345 uint32_t req_data_extra; 346 uint32_t result; 347 uint32_t seq_number; 348 uint32_t fw_flags; 349 struct completion fxiocb_comp; 350 uint32_t reserved_0; 351 uint8_t reserved_1; 352 } fxiocb; 353 struct { 354 uint32_t cmd_hndl; 355 uint32_t comp_status; 356 struct completion comp; 357 } abt; 358 } u; 359 360 struct timer_list timer; 361 void (*timeout)(void *); 362 }; 363 364 /* Values for srb_ctx type */ 365 #define SRB_LOGIN_CMD 1 366 #define SRB_LOGOUT_CMD 2 367 #define SRB_ELS_CMD_RPT 3 368 #define SRB_ELS_CMD_HST 4 369 #define SRB_CT_CMD 5 370 #define SRB_ADISC_CMD 6 371 #define SRB_TM_CMD 7 372 #define SRB_SCSI_CMD 8 373 #define SRB_BIDI_CMD 9 374 #define SRB_FXIOCB_DCMD 10 375 #define SRB_FXIOCB_BCMD 11 376 #define SRB_ABT_CMD 12 377 378 379 typedef struct srb { 380 atomic_t ref_count; 381 struct fc_port *fcport; 382 uint32_t handle; 383 uint16_t flags; 384 uint16_t type; 385 char *name; 386 int iocbs; 387 union { 388 struct srb_iocb iocb_cmd; 389 struct fc_bsg_job *bsg_job; 390 struct srb_cmd scmd; 391 } u; 392 void (*done)(void *, void *, int); 393 void (*free)(void *, void *); 394 } srb_t; 395 396 #define GET_CMD_SP(sp) (sp->u.scmd.cmd) 397 #define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd) 398 #define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx) 399 400 #define GET_CMD_SENSE_LEN(sp) \ 401 (sp->u.scmd.request_sense_length) 402 #define SET_CMD_SENSE_LEN(sp, len) \ 403 (sp->u.scmd.request_sense_length = len) 404 #define GET_CMD_SENSE_PTR(sp) \ 405 (sp->u.scmd.request_sense_ptr) 406 #define SET_CMD_SENSE_PTR(sp, ptr) \ 407 (sp->u.scmd.request_sense_ptr = ptr) 408 #define GET_FW_SENSE_LEN(sp) \ 409 (sp->u.scmd.fw_sense_length) 410 #define SET_FW_SENSE_LEN(sp, len) \ 411 (sp->u.scmd.fw_sense_length = len) 412 413 struct msg_echo_lb { 414 dma_addr_t send_dma; 415 dma_addr_t rcv_dma; 416 uint16_t req_sg_cnt; 417 uint16_t rsp_sg_cnt; 418 uint16_t options; 419 uint32_t transfer_size; 420 uint32_t iteration_count; 421 }; 422 423 /* 424 * ISP I/O Register Set structure definitions. 425 */ 426 struct device_reg_2xxx { 427 uint16_t flash_address; /* Flash BIOS address */ 428 uint16_t flash_data; /* Flash BIOS data */ 429 uint16_t unused_1[1]; /* Gap */ 430 uint16_t ctrl_status; /* Control/Status */ 431 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ 432 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 433 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ 434 435 uint16_t ictrl; /* Interrupt control */ 436 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */ 437 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ 438 439 uint16_t istatus; /* Interrupt status */ 440 #define ISR_RISC_INT BIT_3 /* RISC interrupt */ 441 442 uint16_t semaphore; /* Semaphore */ 443 uint16_t nvram; /* NVRAM register. */ 444 #define NVR_DESELECT 0 445 #define NVR_BUSY BIT_15 446 #define NVR_WRT_ENABLE BIT_14 /* Write enable */ 447 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */ 448 #define NVR_DATA_IN BIT_3 449 #define NVR_DATA_OUT BIT_2 450 #define NVR_SELECT BIT_1 451 #define NVR_CLOCK BIT_0 452 453 #define NVR_WAIT_CNT 20000 454 455 union { 456 struct { 457 uint16_t mailbox0; 458 uint16_t mailbox1; 459 uint16_t mailbox2; 460 uint16_t mailbox3; 461 uint16_t mailbox4; 462 uint16_t mailbox5; 463 uint16_t mailbox6; 464 uint16_t mailbox7; 465 uint16_t unused_2[59]; /* Gap */ 466 } __attribute__((packed)) isp2100; 467 struct { 468 /* Request Queue */ 469 uint16_t req_q_in; /* In-Pointer */ 470 uint16_t req_q_out; /* Out-Pointer */ 471 /* Response Queue */ 472 uint16_t rsp_q_in; /* In-Pointer */ 473 uint16_t rsp_q_out; /* Out-Pointer */ 474 475 /* RISC to Host Status */ 476 uint32_t host_status; 477 #define HSR_RISC_INT BIT_15 /* RISC interrupt */ 478 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */ 479 480 /* Host to Host Semaphore */ 481 uint16_t host_semaphore; 482 uint16_t unused_3[17]; /* Gap */ 483 uint16_t mailbox0; 484 uint16_t mailbox1; 485 uint16_t mailbox2; 486 uint16_t mailbox3; 487 uint16_t mailbox4; 488 uint16_t mailbox5; 489 uint16_t mailbox6; 490 uint16_t mailbox7; 491 uint16_t mailbox8; 492 uint16_t mailbox9; 493 uint16_t mailbox10; 494 uint16_t mailbox11; 495 uint16_t mailbox12; 496 uint16_t mailbox13; 497 uint16_t mailbox14; 498 uint16_t mailbox15; 499 uint16_t mailbox16; 500 uint16_t mailbox17; 501 uint16_t mailbox18; 502 uint16_t mailbox19; 503 uint16_t mailbox20; 504 uint16_t mailbox21; 505 uint16_t mailbox22; 506 uint16_t mailbox23; 507 uint16_t mailbox24; 508 uint16_t mailbox25; 509 uint16_t mailbox26; 510 uint16_t mailbox27; 511 uint16_t mailbox28; 512 uint16_t mailbox29; 513 uint16_t mailbox30; 514 uint16_t mailbox31; 515 uint16_t fb_cmd; 516 uint16_t unused_4[10]; /* Gap */ 517 } __attribute__((packed)) isp2300; 518 } u; 519 520 uint16_t fpm_diag_config; 521 uint16_t unused_5[0x4]; /* Gap */ 522 uint16_t risc_hw; 523 uint16_t unused_5_1; /* Gap */ 524 uint16_t pcr; /* Processor Control Register. */ 525 uint16_t unused_6[0x5]; /* Gap */ 526 uint16_t mctr; /* Memory Configuration and Timing. */ 527 uint16_t unused_7[0x3]; /* Gap */ 528 uint16_t fb_cmd_2100; /* Unused on 23XX */ 529 uint16_t unused_8[0x3]; /* Gap */ 530 uint16_t hccr; /* Host command & control register. */ 531 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */ 532 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ 533 /* HCCR commands */ 534 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */ 535 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */ 536 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 537 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */ 538 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 539 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 540 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */ 541 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ 542 543 uint16_t unused_9[5]; /* Gap */ 544 uint16_t gpiod; /* GPIO Data register. */ 545 uint16_t gpioe; /* GPIO Enable register. */ 546 #define GPIO_LED_MASK 0x00C0 547 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 548 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 549 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080 550 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0 551 #define GPIO_LED_ALL_OFF 0x0000 552 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */ 553 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */ 554 555 union { 556 struct { 557 uint16_t unused_10[8]; /* Gap */ 558 uint16_t mailbox8; 559 uint16_t mailbox9; 560 uint16_t mailbox10; 561 uint16_t mailbox11; 562 uint16_t mailbox12; 563 uint16_t mailbox13; 564 uint16_t mailbox14; 565 uint16_t mailbox15; 566 uint16_t mailbox16; 567 uint16_t mailbox17; 568 uint16_t mailbox18; 569 uint16_t mailbox19; 570 uint16_t mailbox20; 571 uint16_t mailbox21; 572 uint16_t mailbox22; 573 uint16_t mailbox23; /* Also probe reg. */ 574 } __attribute__((packed)) isp2200; 575 } u_end; 576 }; 577 578 struct device_reg_25xxmq { 579 uint32_t req_q_in; 580 uint32_t req_q_out; 581 uint32_t rsp_q_in; 582 uint32_t rsp_q_out; 583 uint32_t atio_q_in; 584 uint32_t atio_q_out; 585 }; 586 587 588 struct device_reg_fx00 { 589 uint32_t mailbox0; /* 00 */ 590 uint32_t mailbox1; /* 04 */ 591 uint32_t mailbox2; /* 08 */ 592 uint32_t mailbox3; /* 0C */ 593 uint32_t mailbox4; /* 10 */ 594 uint32_t mailbox5; /* 14 */ 595 uint32_t mailbox6; /* 18 */ 596 uint32_t mailbox7; /* 1C */ 597 uint32_t mailbox8; /* 20 */ 598 uint32_t mailbox9; /* 24 */ 599 uint32_t mailbox10; /* 28 */ 600 uint32_t mailbox11; 601 uint32_t mailbox12; 602 uint32_t mailbox13; 603 uint32_t mailbox14; 604 uint32_t mailbox15; 605 uint32_t mailbox16; 606 uint32_t mailbox17; 607 uint32_t mailbox18; 608 uint32_t mailbox19; 609 uint32_t mailbox20; 610 uint32_t mailbox21; 611 uint32_t mailbox22; 612 uint32_t mailbox23; 613 uint32_t mailbox24; 614 uint32_t mailbox25; 615 uint32_t mailbox26; 616 uint32_t mailbox27; 617 uint32_t mailbox28; 618 uint32_t mailbox29; 619 uint32_t mailbox30; 620 uint32_t mailbox31; 621 uint32_t aenmailbox0; 622 uint32_t aenmailbox1; 623 uint32_t aenmailbox2; 624 uint32_t aenmailbox3; 625 uint32_t aenmailbox4; 626 uint32_t aenmailbox5; 627 uint32_t aenmailbox6; 628 uint32_t aenmailbox7; 629 /* Request Queue. */ 630 uint32_t req_q_in; /* A0 - Request Queue In-Pointer */ 631 uint32_t req_q_out; /* A4 - Request Queue Out-Pointer */ 632 /* Response Queue. */ 633 uint32_t rsp_q_in; /* A8 - Response Queue In-Pointer */ 634 uint32_t rsp_q_out; /* AC - Response Queue Out-Pointer */ 635 /* Init values shadowed on FW Up Event */ 636 uint32_t initval0; /* B0 */ 637 uint32_t initval1; /* B4 */ 638 uint32_t initval2; /* B8 */ 639 uint32_t initval3; /* BC */ 640 uint32_t initval4; /* C0 */ 641 uint32_t initval5; /* C4 */ 642 uint32_t initval6; /* C8 */ 643 uint32_t initval7; /* CC */ 644 uint32_t fwheartbeat; /* D0 */ 645 }; 646 647 648 649 typedef union { 650 struct device_reg_2xxx isp; 651 struct device_reg_24xx isp24; 652 struct device_reg_25xxmq isp25mq; 653 struct device_reg_82xx isp82; 654 struct device_reg_fx00 ispfx00; 655 } device_reg_t; 656 657 #define ISP_REQ_Q_IN(ha, reg) \ 658 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 659 &(reg)->u.isp2100.mailbox4 : \ 660 &(reg)->u.isp2300.req_q_in) 661 #define ISP_REQ_Q_OUT(ha, reg) \ 662 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 663 &(reg)->u.isp2100.mailbox4 : \ 664 &(reg)->u.isp2300.req_q_out) 665 #define ISP_RSP_Q_IN(ha, reg) \ 666 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 667 &(reg)->u.isp2100.mailbox5 : \ 668 &(reg)->u.isp2300.rsp_q_in) 669 #define ISP_RSP_Q_OUT(ha, reg) \ 670 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 671 &(reg)->u.isp2100.mailbox5 : \ 672 &(reg)->u.isp2300.rsp_q_out) 673 674 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in) 675 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out) 676 677 #define MAILBOX_REG(ha, reg, num) \ 678 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 679 (num < 8 ? \ 680 &(reg)->u.isp2100.mailbox0 + (num) : \ 681 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \ 682 &(reg)->u.isp2300.mailbox0 + (num)) 683 #define RD_MAILBOX_REG(ha, reg, num) \ 684 RD_REG_WORD(MAILBOX_REG(ha, reg, num)) 685 #define WRT_MAILBOX_REG(ha, reg, num, data) \ 686 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data) 687 688 #define FB_CMD_REG(ha, reg) \ 689 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 690 &(reg)->fb_cmd_2100 : \ 691 &(reg)->u.isp2300.fb_cmd) 692 #define RD_FB_CMD_REG(ha, reg) \ 693 RD_REG_WORD(FB_CMD_REG(ha, reg)) 694 #define WRT_FB_CMD_REG(ha, reg, data) \ 695 WRT_REG_WORD(FB_CMD_REG(ha, reg), data) 696 697 typedef struct { 698 uint32_t out_mb; /* outbound from driver */ 699 uint32_t in_mb; /* Incoming from RISC */ 700 uint16_t mb[MAILBOX_REGISTER_COUNT]; 701 long buf_size; 702 void *bufp; 703 uint32_t tov; 704 uint8_t flags; 705 #define MBX_DMA_IN BIT_0 706 #define MBX_DMA_OUT BIT_1 707 #define IOCTL_CMD BIT_2 708 } mbx_cmd_t; 709 710 struct mbx_cmd_32 { 711 uint32_t out_mb; /* outbound from driver */ 712 uint32_t in_mb; /* Incoming from RISC */ 713 uint32_t mb[MAILBOX_REGISTER_COUNT]; 714 long buf_size; 715 void *bufp; 716 uint32_t tov; 717 uint8_t flags; 718 #define MBX_DMA_IN BIT_0 719 #define MBX_DMA_OUT BIT_1 720 #define IOCTL_CMD BIT_2 721 }; 722 723 724 #define MBX_TOV_SECONDS 30 725 726 /* 727 * ISP product identification definitions in mailboxes after reset. 728 */ 729 #define PROD_ID_1 0x4953 730 #define PROD_ID_2 0x0000 731 #define PROD_ID_2a 0x5020 732 #define PROD_ID_3 0x2020 733 734 /* 735 * ISP mailbox Self-Test status codes 736 */ 737 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ 738 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ 739 #define MBS_BUSY 4 /* Busy. */ 740 741 /* 742 * ISP mailbox command complete status codes 743 */ 744 #define MBS_COMMAND_COMPLETE 0x4000 745 #define MBS_INVALID_COMMAND 0x4001 746 #define MBS_HOST_INTERFACE_ERROR 0x4002 747 #define MBS_TEST_FAILED 0x4003 748 #define MBS_COMMAND_ERROR 0x4005 749 #define MBS_COMMAND_PARAMETER_ERROR 0x4006 750 #define MBS_PORT_ID_USED 0x4007 751 #define MBS_LOOP_ID_USED 0x4008 752 #define MBS_ALL_IDS_IN_USE 0x4009 753 #define MBS_NOT_LOGGED_IN 0x400A 754 #define MBS_LINK_DOWN_ERROR 0x400B 755 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C 756 757 /* 758 * ISP mailbox asynchronous event status codes 759 */ 760 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 761 #define MBA_RESET 0x8001 /* Reset Detected. */ 762 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 763 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 764 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 765 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 766 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ 767 /* occurred. */ 768 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ 769 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ 770 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ 771 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ 772 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */ 773 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ 774 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */ 775 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */ 776 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ 777 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ 778 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ 779 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */ 780 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ 781 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ 782 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ 783 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ 784 /* used. */ 785 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */ 786 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ 787 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ 788 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ 789 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ 790 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ 791 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ 792 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ 793 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */ 794 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */ 795 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ 796 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */ 797 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */ 798 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */ 799 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */ 800 #define MBA_FW_STARTING 0x8051 /* Firmware starting */ 801 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */ 802 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */ 803 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */ 804 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */ 805 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change 806 Notification */ 807 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */ 808 809 /* 83XX FCoE specific */ 810 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */ 811 812 /* Interrupt type codes */ 813 #define INTR_ROM_MB_SUCCESS 0x1 814 #define INTR_ROM_MB_FAILED 0x2 815 #define INTR_MB_SUCCESS 0x10 816 #define INTR_MB_FAILED 0x11 817 #define INTR_ASYNC_EVENT 0x12 818 #define INTR_RSP_QUE_UPDATE 0x13 819 #define INTR_RSP_QUE_UPDATE_83XX 0x14 820 #define INTR_ATIO_QUE_UPDATE 0x1C 821 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D 822 823 /* ISP mailbox loopback echo diagnostic error code */ 824 #define MBS_LB_RESET 0x17 825 /* 826 * Firmware options 1, 2, 3. 827 */ 828 #define FO1_AE_ON_LIPF8 BIT_0 829 #define FO1_AE_ALL_LIP_RESET BIT_1 830 #define FO1_CTIO_RETRY BIT_3 831 #define FO1_DISABLE_LIP_F7_SW BIT_4 832 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5 833 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */ 834 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7 835 #define FO1_SET_EMPHASIS_SWING BIT_8 836 #define FO1_AE_AUTO_BYPASS BIT_9 837 #define FO1_ENABLE_PURE_IOCB BIT_10 838 #define FO1_AE_PLOGI_RJT BIT_11 839 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12 840 #define FO1_AE_QUEUE_FULL BIT_13 841 842 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 843 #define FO2_REV_LOOPBACK BIT_1 844 845 #define FO3_ENABLE_EMERG_IOCB BIT_0 846 #define FO3_AE_RND_ERROR BIT_1 847 848 /* 24XX additional firmware options */ 849 #define ADD_FO_COUNT 3 850 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */ 851 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10 852 853 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5 854 855 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14 856 857 /* 858 * ISP mailbox commands 859 */ 860 #define MBC_LOAD_RAM 1 /* Load RAM. */ 861 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 862 #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */ 863 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */ 864 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 865 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 866 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */ 867 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */ 868 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */ 869 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */ 870 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */ 871 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */ 872 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ 873 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */ 874 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */ 875 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */ 876 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ 877 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ 878 #define MBC_RESET 0x18 /* Reset. */ 879 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */ 880 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */ 881 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */ 882 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */ 883 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */ 884 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */ 885 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ 886 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ 887 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ 888 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ 889 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */ 890 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ 891 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ 892 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */ 893 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */ 894 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ 895 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */ 896 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */ 897 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ 898 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */ 899 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */ 900 #define MBC_DATA_RATE 0x5d /* Data Rate */ 901 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 902 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */ 903 /* Initialization Procedure */ 904 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ 905 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ 906 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ 907 #define MBC_TARGET_RESET 0x66 /* Target Reset. */ 908 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ 909 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ 910 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 911 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */ 912 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */ 913 #define MBC_LIP_RESET 0x6c /* LIP reset. */ 914 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ 915 /* commandd. */ 916 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ 917 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ 918 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ 919 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ 920 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ 921 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */ 922 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */ 923 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */ 924 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */ 925 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */ 926 #define MBC_LUN_RESET 0x7E /* Send LUN reset */ 927 928 /* 929 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones 930 * should be defined with MBC_MR_* 931 */ 932 #define MBC_MR_DRV_SHUTDOWN 0x6A 933 934 /* 935 * ISP24xx mailbox commands 936 */ 937 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */ 938 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */ 939 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */ 940 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */ 941 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */ 942 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */ 943 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */ 944 #define MBC_READ_SFP 0x31 /* Read SFP Data. */ 945 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */ 946 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */ 947 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */ 948 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */ 949 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */ 950 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */ 951 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */ 952 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */ 953 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */ 954 #define MBC_PORT_RESET 0x120 /* Port Reset */ 955 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */ 956 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */ 957 958 /* 959 * ISP81xx mailbox commands 960 */ 961 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */ 962 963 /* Firmware return data sizes */ 964 #define FCAL_MAP_SIZE 128 965 966 /* Mailbox bit definitions for out_mb and in_mb */ 967 #define MBX_31 BIT_31 968 #define MBX_30 BIT_30 969 #define MBX_29 BIT_29 970 #define MBX_28 BIT_28 971 #define MBX_27 BIT_27 972 #define MBX_26 BIT_26 973 #define MBX_25 BIT_25 974 #define MBX_24 BIT_24 975 #define MBX_23 BIT_23 976 #define MBX_22 BIT_22 977 #define MBX_21 BIT_21 978 #define MBX_20 BIT_20 979 #define MBX_19 BIT_19 980 #define MBX_18 BIT_18 981 #define MBX_17 BIT_17 982 #define MBX_16 BIT_16 983 #define MBX_15 BIT_15 984 #define MBX_14 BIT_14 985 #define MBX_13 BIT_13 986 #define MBX_12 BIT_12 987 #define MBX_11 BIT_11 988 #define MBX_10 BIT_10 989 #define MBX_9 BIT_9 990 #define MBX_8 BIT_8 991 #define MBX_7 BIT_7 992 #define MBX_6 BIT_6 993 #define MBX_5 BIT_5 994 #define MBX_4 BIT_4 995 #define MBX_3 BIT_3 996 #define MBX_2 BIT_2 997 #define MBX_1 BIT_1 998 #define MBX_0 BIT_0 999 1000 #define RNID_TYPE_ASIC_TEMP 0xC 1001 1002 /* 1003 * Firmware state codes from get firmware state mailbox command 1004 */ 1005 #define FSTATE_CONFIG_WAIT 0 1006 #define FSTATE_WAIT_AL_PA 1 1007 #define FSTATE_WAIT_LOGIN 2 1008 #define FSTATE_READY 3 1009 #define FSTATE_LOSS_OF_SYNC 4 1010 #define FSTATE_ERROR 5 1011 #define FSTATE_REINIT 6 1012 #define FSTATE_NON_PART 7 1013 1014 #define FSTATE_CONFIG_CORRECT 0 1015 #define FSTATE_P2P_RCV_LIP 1 1016 #define FSTATE_P2P_CHOOSE_LOOP 2 1017 #define FSTATE_P2P_RCV_UNIDEN_LIP 3 1018 #define FSTATE_FATAL_ERROR 4 1019 #define FSTATE_LOOP_BACK_CONN 5 1020 1021 /* 1022 * Port Database structure definition 1023 * Little endian except where noted. 1024 */ 1025 #define PORT_DATABASE_SIZE 128 /* bytes */ 1026 typedef struct { 1027 uint8_t options; 1028 uint8_t control; 1029 uint8_t master_state; 1030 uint8_t slave_state; 1031 uint8_t reserved[2]; 1032 uint8_t hard_address; 1033 uint8_t reserved_1; 1034 uint8_t port_id[4]; 1035 uint8_t node_name[WWN_SIZE]; 1036 uint8_t port_name[WWN_SIZE]; 1037 uint16_t execution_throttle; 1038 uint16_t execution_count; 1039 uint8_t reset_count; 1040 uint8_t reserved_2; 1041 uint16_t resource_allocation; 1042 uint16_t current_allocation; 1043 uint16_t queue_head; 1044 uint16_t queue_tail; 1045 uint16_t transmit_execution_list_next; 1046 uint16_t transmit_execution_list_previous; 1047 uint16_t common_features; 1048 uint16_t total_concurrent_sequences; 1049 uint16_t RO_by_information_category; 1050 uint8_t recipient; 1051 uint8_t initiator; 1052 uint16_t receive_data_size; 1053 uint16_t concurrent_sequences; 1054 uint16_t open_sequences_per_exchange; 1055 uint16_t lun_abort_flags; 1056 uint16_t lun_stop_flags; 1057 uint16_t stop_queue_head; 1058 uint16_t stop_queue_tail; 1059 uint16_t port_retry_timer; 1060 uint16_t next_sequence_id; 1061 uint16_t frame_count; 1062 uint16_t PRLI_payload_length; 1063 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 1064 /* Bits 15-0 of word 0 */ 1065 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 1066 /* Bits 15-0 of word 3 */ 1067 uint16_t loop_id; 1068 uint16_t extended_lun_info_list_pointer; 1069 uint16_t extended_lun_stop_list_pointer; 1070 } port_database_t; 1071 1072 /* 1073 * Port database slave/master states 1074 */ 1075 #define PD_STATE_DISCOVERY 0 1076 #define PD_STATE_WAIT_DISCOVERY_ACK 1 1077 #define PD_STATE_PORT_LOGIN 2 1078 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3 1079 #define PD_STATE_PROCESS_LOGIN 4 1080 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 1081 #define PD_STATE_PORT_LOGGED_IN 6 1082 #define PD_STATE_PORT_UNAVAILABLE 7 1083 #define PD_STATE_PROCESS_LOGOUT 8 1084 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 1085 #define PD_STATE_PORT_LOGOUT 10 1086 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 1087 1088 1089 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1) 1090 #define QLA_ZIO_DISABLED 0 1091 #define QLA_ZIO_DEFAULT_TIMER 2 1092 1093 /* 1094 * ISP Initialization Control Block. 1095 * Little endian except where noted. 1096 */ 1097 #define ICB_VERSION 1 1098 typedef struct { 1099 uint8_t version; 1100 uint8_t reserved_1; 1101 1102 /* 1103 * LSB BIT 0 = Enable Hard Loop Id 1104 * LSB BIT 1 = Enable Fairness 1105 * LSB BIT 2 = Enable Full-Duplex 1106 * LSB BIT 3 = Enable Fast Posting 1107 * LSB BIT 4 = Enable Target Mode 1108 * LSB BIT 5 = Disable Initiator Mode 1109 * LSB BIT 6 = Enable ADISC 1110 * LSB BIT 7 = Enable Target Inquiry Data 1111 * 1112 * MSB BIT 0 = Enable PDBC Notify 1113 * MSB BIT 1 = Non Participating LIP 1114 * MSB BIT 2 = Descending Loop ID Search 1115 * MSB BIT 3 = Acquire Loop ID in LIPA 1116 * MSB BIT 4 = Stop PortQ on Full Status 1117 * MSB BIT 5 = Full Login after LIP 1118 * MSB BIT 6 = Node Name Option 1119 * MSB BIT 7 = Ext IFWCB enable bit 1120 */ 1121 uint8_t firmware_options[2]; 1122 1123 uint16_t frame_payload_size; 1124 uint16_t max_iocb_allocation; 1125 uint16_t execution_throttle; 1126 uint8_t retry_count; 1127 uint8_t retry_delay; /* unused */ 1128 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1129 uint16_t hard_address; 1130 uint8_t inquiry_data; 1131 uint8_t login_timeout; 1132 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1133 1134 uint16_t request_q_outpointer; 1135 uint16_t response_q_inpointer; 1136 uint16_t request_q_length; 1137 uint16_t response_q_length; 1138 uint32_t request_q_address[2]; 1139 uint32_t response_q_address[2]; 1140 1141 uint16_t lun_enables; 1142 uint8_t command_resource_count; 1143 uint8_t immediate_notify_resource_count; 1144 uint16_t timeout; 1145 uint8_t reserved_2[2]; 1146 1147 /* 1148 * LSB BIT 0 = Timer Operation mode bit 0 1149 * LSB BIT 1 = Timer Operation mode bit 1 1150 * LSB BIT 2 = Timer Operation mode bit 2 1151 * LSB BIT 3 = Timer Operation mode bit 3 1152 * LSB BIT 4 = Init Config Mode bit 0 1153 * LSB BIT 5 = Init Config Mode bit 1 1154 * LSB BIT 6 = Init Config Mode bit 2 1155 * LSB BIT 7 = Enable Non part on LIHA failure 1156 * 1157 * MSB BIT 0 = Enable class 2 1158 * MSB BIT 1 = Enable ACK0 1159 * MSB BIT 2 = 1160 * MSB BIT 3 = 1161 * MSB BIT 4 = FC Tape Enable 1162 * MSB BIT 5 = Enable FC Confirm 1163 * MSB BIT 6 = Enable command queuing in target mode 1164 * MSB BIT 7 = No Logo On Link Down 1165 */ 1166 uint8_t add_firmware_options[2]; 1167 1168 uint8_t response_accumulation_timer; 1169 uint8_t interrupt_delay_timer; 1170 1171 /* 1172 * LSB BIT 0 = Enable Read xfr_rdy 1173 * LSB BIT 1 = Soft ID only 1174 * LSB BIT 2 = 1175 * LSB BIT 3 = 1176 * LSB BIT 4 = FCP RSP Payload [0] 1177 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1178 * LSB BIT 6 = Enable Out-of-Order frame handling 1179 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1180 * 1181 * MSB BIT 0 = Sbus enable - 2300 1182 * MSB BIT 1 = 1183 * MSB BIT 2 = 1184 * MSB BIT 3 = 1185 * MSB BIT 4 = LED mode 1186 * MSB BIT 5 = enable 50 ohm termination 1187 * MSB BIT 6 = Data Rate (2300 only) 1188 * MSB BIT 7 = Data Rate (2300 only) 1189 */ 1190 uint8_t special_options[2]; 1191 1192 uint8_t reserved_3[26]; 1193 } init_cb_t; 1194 1195 1196 struct init_cb_fx { 1197 uint16_t version; 1198 uint16_t reserved_1[13]; 1199 uint16_t request_q_outpointer; 1200 uint16_t response_q_inpointer; 1201 uint16_t reserved_2[2]; 1202 uint16_t response_q_length; 1203 uint16_t request_q_length; 1204 uint16_t reserved_3[2]; 1205 uint32_t request_q_address[2]; 1206 uint32_t response_q_address[2]; 1207 uint16_t reserved_4[4]; 1208 uint8_t response_q_msivec; 1209 uint8_t reserved_5[19]; 1210 uint16_t interrupt_delay_timer; 1211 uint16_t reserved_6; 1212 uint32_t fwoptions1; 1213 uint32_t fwoptions2; 1214 uint32_t fwoptions3; 1215 uint8_t reserved_7[24]; 1216 }; 1217 1218 1219 /* 1220 * Get Link Status mailbox command return buffer. 1221 */ 1222 #define GLSO_SEND_RPS BIT_0 1223 #define GLSO_USE_DID BIT_3 1224 1225 struct link_statistics { 1226 uint32_t link_fail_cnt; 1227 uint32_t loss_sync_cnt; 1228 uint32_t loss_sig_cnt; 1229 uint32_t prim_seq_err_cnt; 1230 uint32_t inval_xmit_word_cnt; 1231 uint32_t inval_crc_cnt; 1232 uint32_t lip_cnt; 1233 uint32_t unused1[0x1a]; 1234 uint32_t tx_frames; 1235 uint32_t rx_frames; 1236 uint32_t dumped_frames; 1237 uint32_t unused2[2]; 1238 uint32_t nos_rcvd; 1239 }; 1240 1241 /* 1242 * NVRAM Command values. 1243 */ 1244 #define NV_START_BIT BIT_2 1245 #define NV_WRITE_OP (BIT_26+BIT_24) 1246 #define NV_READ_OP (BIT_26+BIT_25) 1247 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24) 1248 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24) 1249 #define NV_DELAY_COUNT 10 1250 1251 /* 1252 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition. 1253 */ 1254 typedef struct { 1255 /* 1256 * NVRAM header 1257 */ 1258 uint8_t id[4]; 1259 uint8_t nvram_version; 1260 uint8_t reserved_0; 1261 1262 /* 1263 * NVRAM RISC parameter block 1264 */ 1265 uint8_t parameter_block_version; 1266 uint8_t reserved_1; 1267 1268 /* 1269 * LSB BIT 0 = Enable Hard Loop Id 1270 * LSB BIT 1 = Enable Fairness 1271 * LSB BIT 2 = Enable Full-Duplex 1272 * LSB BIT 3 = Enable Fast Posting 1273 * LSB BIT 4 = Enable Target Mode 1274 * LSB BIT 5 = Disable Initiator Mode 1275 * LSB BIT 6 = Enable ADISC 1276 * LSB BIT 7 = Enable Target Inquiry Data 1277 * 1278 * MSB BIT 0 = Enable PDBC Notify 1279 * MSB BIT 1 = Non Participating LIP 1280 * MSB BIT 2 = Descending Loop ID Search 1281 * MSB BIT 3 = Acquire Loop ID in LIPA 1282 * MSB BIT 4 = Stop PortQ on Full Status 1283 * MSB BIT 5 = Full Login after LIP 1284 * MSB BIT 6 = Node Name Option 1285 * MSB BIT 7 = Ext IFWCB enable bit 1286 */ 1287 uint8_t firmware_options[2]; 1288 1289 uint16_t frame_payload_size; 1290 uint16_t max_iocb_allocation; 1291 uint16_t execution_throttle; 1292 uint8_t retry_count; 1293 uint8_t retry_delay; /* unused */ 1294 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1295 uint16_t hard_address; 1296 uint8_t inquiry_data; 1297 uint8_t login_timeout; 1298 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1299 1300 /* 1301 * LSB BIT 0 = Timer Operation mode bit 0 1302 * LSB BIT 1 = Timer Operation mode bit 1 1303 * LSB BIT 2 = Timer Operation mode bit 2 1304 * LSB BIT 3 = Timer Operation mode bit 3 1305 * LSB BIT 4 = Init Config Mode bit 0 1306 * LSB BIT 5 = Init Config Mode bit 1 1307 * LSB BIT 6 = Init Config Mode bit 2 1308 * LSB BIT 7 = Enable Non part on LIHA failure 1309 * 1310 * MSB BIT 0 = Enable class 2 1311 * MSB BIT 1 = Enable ACK0 1312 * MSB BIT 2 = 1313 * MSB BIT 3 = 1314 * MSB BIT 4 = FC Tape Enable 1315 * MSB BIT 5 = Enable FC Confirm 1316 * MSB BIT 6 = Enable command queuing in target mode 1317 * MSB BIT 7 = No Logo On Link Down 1318 */ 1319 uint8_t add_firmware_options[2]; 1320 1321 uint8_t response_accumulation_timer; 1322 uint8_t interrupt_delay_timer; 1323 1324 /* 1325 * LSB BIT 0 = Enable Read xfr_rdy 1326 * LSB BIT 1 = Soft ID only 1327 * LSB BIT 2 = 1328 * LSB BIT 3 = 1329 * LSB BIT 4 = FCP RSP Payload [0] 1330 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1331 * LSB BIT 6 = Enable Out-of-Order frame handling 1332 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1333 * 1334 * MSB BIT 0 = Sbus enable - 2300 1335 * MSB BIT 1 = 1336 * MSB BIT 2 = 1337 * MSB BIT 3 = 1338 * MSB BIT 4 = LED mode 1339 * MSB BIT 5 = enable 50 ohm termination 1340 * MSB BIT 6 = Data Rate (2300 only) 1341 * MSB BIT 7 = Data Rate (2300 only) 1342 */ 1343 uint8_t special_options[2]; 1344 1345 /* Reserved for expanded RISC parameter block */ 1346 uint8_t reserved_2[22]; 1347 1348 /* 1349 * LSB BIT 0 = Tx Sensitivity 1G bit 0 1350 * LSB BIT 1 = Tx Sensitivity 1G bit 1 1351 * LSB BIT 2 = Tx Sensitivity 1G bit 2 1352 * LSB BIT 3 = Tx Sensitivity 1G bit 3 1353 * LSB BIT 4 = Rx Sensitivity 1G bit 0 1354 * LSB BIT 5 = Rx Sensitivity 1G bit 1 1355 * LSB BIT 6 = Rx Sensitivity 1G bit 2 1356 * LSB BIT 7 = Rx Sensitivity 1G bit 3 1357 * 1358 * MSB BIT 0 = Tx Sensitivity 2G bit 0 1359 * MSB BIT 1 = Tx Sensitivity 2G bit 1 1360 * MSB BIT 2 = Tx Sensitivity 2G bit 2 1361 * MSB BIT 3 = Tx Sensitivity 2G bit 3 1362 * MSB BIT 4 = Rx Sensitivity 2G bit 0 1363 * MSB BIT 5 = Rx Sensitivity 2G bit 1 1364 * MSB BIT 6 = Rx Sensitivity 2G bit 2 1365 * MSB BIT 7 = Rx Sensitivity 2G bit 3 1366 * 1367 * LSB BIT 0 = Output Swing 1G bit 0 1368 * LSB BIT 1 = Output Swing 1G bit 1 1369 * LSB BIT 2 = Output Swing 1G bit 2 1370 * LSB BIT 3 = Output Emphasis 1G bit 0 1371 * LSB BIT 4 = Output Emphasis 1G bit 1 1372 * LSB BIT 5 = Output Swing 2G bit 0 1373 * LSB BIT 6 = Output Swing 2G bit 1 1374 * LSB BIT 7 = Output Swing 2G bit 2 1375 * 1376 * MSB BIT 0 = Output Emphasis 2G bit 0 1377 * MSB BIT 1 = Output Emphasis 2G bit 1 1378 * MSB BIT 2 = Output Enable 1379 * MSB BIT 3 = 1380 * MSB BIT 4 = 1381 * MSB BIT 5 = 1382 * MSB BIT 6 = 1383 * MSB BIT 7 = 1384 */ 1385 uint8_t seriallink_options[4]; 1386 1387 /* 1388 * NVRAM host parameter block 1389 * 1390 * LSB BIT 0 = Enable spinup delay 1391 * LSB BIT 1 = Disable BIOS 1392 * LSB BIT 2 = Enable Memory Map BIOS 1393 * LSB BIT 3 = Enable Selectable Boot 1394 * LSB BIT 4 = Disable RISC code load 1395 * LSB BIT 5 = Set cache line size 1 1396 * LSB BIT 6 = PCI Parity Disable 1397 * LSB BIT 7 = Enable extended logging 1398 * 1399 * MSB BIT 0 = Enable 64bit addressing 1400 * MSB BIT 1 = Enable lip reset 1401 * MSB BIT 2 = Enable lip full login 1402 * MSB BIT 3 = Enable target reset 1403 * MSB BIT 4 = Enable database storage 1404 * MSB BIT 5 = Enable cache flush read 1405 * MSB BIT 6 = Enable database load 1406 * MSB BIT 7 = Enable alternate WWN 1407 */ 1408 uint8_t host_p[2]; 1409 1410 uint8_t boot_node_name[WWN_SIZE]; 1411 uint8_t boot_lun_number; 1412 uint8_t reset_delay; 1413 uint8_t port_down_retry_count; 1414 uint8_t boot_id_number; 1415 uint16_t max_luns_per_target; 1416 uint8_t fcode_boot_port_name[WWN_SIZE]; 1417 uint8_t alternate_port_name[WWN_SIZE]; 1418 uint8_t alternate_node_name[WWN_SIZE]; 1419 1420 /* 1421 * BIT 0 = Selective Login 1422 * BIT 1 = Alt-Boot Enable 1423 * BIT 2 = 1424 * BIT 3 = Boot Order List 1425 * BIT 4 = 1426 * BIT 5 = Selective LUN 1427 * BIT 6 = 1428 * BIT 7 = unused 1429 */ 1430 uint8_t efi_parameters; 1431 1432 uint8_t link_down_timeout; 1433 1434 uint8_t adapter_id[16]; 1435 1436 uint8_t alt1_boot_node_name[WWN_SIZE]; 1437 uint16_t alt1_boot_lun_number; 1438 uint8_t alt2_boot_node_name[WWN_SIZE]; 1439 uint16_t alt2_boot_lun_number; 1440 uint8_t alt3_boot_node_name[WWN_SIZE]; 1441 uint16_t alt3_boot_lun_number; 1442 uint8_t alt4_boot_node_name[WWN_SIZE]; 1443 uint16_t alt4_boot_lun_number; 1444 uint8_t alt5_boot_node_name[WWN_SIZE]; 1445 uint16_t alt5_boot_lun_number; 1446 uint8_t alt6_boot_node_name[WWN_SIZE]; 1447 uint16_t alt6_boot_lun_number; 1448 uint8_t alt7_boot_node_name[WWN_SIZE]; 1449 uint16_t alt7_boot_lun_number; 1450 1451 uint8_t reserved_3[2]; 1452 1453 /* Offset 200-215 : Model Number */ 1454 uint8_t model_number[16]; 1455 1456 /* OEM related items */ 1457 uint8_t oem_specific[16]; 1458 1459 /* 1460 * NVRAM Adapter Features offset 232-239 1461 * 1462 * LSB BIT 0 = External GBIC 1463 * LSB BIT 1 = Risc RAM parity 1464 * LSB BIT 2 = Buffer Plus Module 1465 * LSB BIT 3 = Multi Chip Adapter 1466 * LSB BIT 4 = Internal connector 1467 * LSB BIT 5 = 1468 * LSB BIT 6 = 1469 * LSB BIT 7 = 1470 * 1471 * MSB BIT 0 = 1472 * MSB BIT 1 = 1473 * MSB BIT 2 = 1474 * MSB BIT 3 = 1475 * MSB BIT 4 = 1476 * MSB BIT 5 = 1477 * MSB BIT 6 = 1478 * MSB BIT 7 = 1479 */ 1480 uint8_t adapter_features[2]; 1481 1482 uint8_t reserved_4[16]; 1483 1484 /* Subsystem vendor ID for ISP2200 */ 1485 uint16_t subsystem_vendor_id_2200; 1486 1487 /* Subsystem device ID for ISP2200 */ 1488 uint16_t subsystem_device_id_2200; 1489 1490 uint8_t reserved_5; 1491 uint8_t checksum; 1492 } nvram_t; 1493 1494 /* 1495 * ISP queue - response queue entry definition. 1496 */ 1497 typedef struct { 1498 uint8_t entry_type; /* Entry type. */ 1499 uint8_t entry_count; /* Entry count. */ 1500 uint8_t sys_define; /* System defined. */ 1501 uint8_t entry_status; /* Entry Status. */ 1502 uint32_t handle; /* System defined handle */ 1503 uint8_t data[52]; 1504 uint32_t signature; 1505 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ 1506 } response_t; 1507 1508 /* 1509 * ISP queue - ATIO queue entry definition. 1510 */ 1511 struct atio { 1512 uint8_t entry_type; /* Entry type. */ 1513 uint8_t entry_count; /* Entry count. */ 1514 uint8_t data[58]; 1515 uint32_t signature; 1516 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */ 1517 }; 1518 1519 typedef union { 1520 uint16_t extended; 1521 struct { 1522 uint8_t reserved; 1523 uint8_t standard; 1524 } id; 1525 } target_id_t; 1526 1527 #define SET_TARGET_ID(ha, to, from) \ 1528 do { \ 1529 if (HAS_EXTENDED_IDS(ha)) \ 1530 to.extended = cpu_to_le16(from); \ 1531 else \ 1532 to.id.standard = (uint8_t)from; \ 1533 } while (0) 1534 1535 /* 1536 * ISP queue - command entry structure definition. 1537 */ 1538 #define COMMAND_TYPE 0x11 /* Command entry */ 1539 typedef struct { 1540 uint8_t entry_type; /* Entry type. */ 1541 uint8_t entry_count; /* Entry count. */ 1542 uint8_t sys_define; /* System defined. */ 1543 uint8_t entry_status; /* Entry Status. */ 1544 uint32_t handle; /* System handle. */ 1545 target_id_t target; /* SCSI ID */ 1546 uint16_t lun; /* SCSI LUN */ 1547 uint16_t control_flags; /* Control flags. */ 1548 #define CF_WRITE BIT_6 1549 #define CF_READ BIT_5 1550 #define CF_SIMPLE_TAG BIT_3 1551 #define CF_ORDERED_TAG BIT_2 1552 #define CF_HEAD_TAG BIT_1 1553 uint16_t reserved_1; 1554 uint16_t timeout; /* Command timeout. */ 1555 uint16_t dseg_count; /* Data segment count. */ 1556 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1557 uint32_t byte_count; /* Total byte count. */ 1558 uint32_t dseg_0_address; /* Data segment 0 address. */ 1559 uint32_t dseg_0_length; /* Data segment 0 length. */ 1560 uint32_t dseg_1_address; /* Data segment 1 address. */ 1561 uint32_t dseg_1_length; /* Data segment 1 length. */ 1562 uint32_t dseg_2_address; /* Data segment 2 address. */ 1563 uint32_t dseg_2_length; /* Data segment 2 length. */ 1564 } cmd_entry_t; 1565 1566 /* 1567 * ISP queue - 64-Bit addressing, command entry structure definition. 1568 */ 1569 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */ 1570 typedef struct { 1571 uint8_t entry_type; /* Entry type. */ 1572 uint8_t entry_count; /* Entry count. */ 1573 uint8_t sys_define; /* System defined. */ 1574 uint8_t entry_status; /* Entry Status. */ 1575 uint32_t handle; /* System handle. */ 1576 target_id_t target; /* SCSI ID */ 1577 uint16_t lun; /* SCSI LUN */ 1578 uint16_t control_flags; /* Control flags. */ 1579 uint16_t reserved_1; 1580 uint16_t timeout; /* Command timeout. */ 1581 uint16_t dseg_count; /* Data segment count. */ 1582 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1583 uint32_t byte_count; /* Total byte count. */ 1584 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1585 uint32_t dseg_0_length; /* Data segment 0 length. */ 1586 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1587 uint32_t dseg_1_length; /* Data segment 1 length. */ 1588 } cmd_a64_entry_t, request_t; 1589 1590 /* 1591 * ISP queue - continuation entry structure definition. 1592 */ 1593 #define CONTINUE_TYPE 0x02 /* Continuation entry. */ 1594 typedef struct { 1595 uint8_t entry_type; /* Entry type. */ 1596 uint8_t entry_count; /* Entry count. */ 1597 uint8_t sys_define; /* System defined. */ 1598 uint8_t entry_status; /* Entry Status. */ 1599 uint32_t reserved; 1600 uint32_t dseg_0_address; /* Data segment 0 address. */ 1601 uint32_t dseg_0_length; /* Data segment 0 length. */ 1602 uint32_t dseg_1_address; /* Data segment 1 address. */ 1603 uint32_t dseg_1_length; /* Data segment 1 length. */ 1604 uint32_t dseg_2_address; /* Data segment 2 address. */ 1605 uint32_t dseg_2_length; /* Data segment 2 length. */ 1606 uint32_t dseg_3_address; /* Data segment 3 address. */ 1607 uint32_t dseg_3_length; /* Data segment 3 length. */ 1608 uint32_t dseg_4_address; /* Data segment 4 address. */ 1609 uint32_t dseg_4_length; /* Data segment 4 length. */ 1610 uint32_t dseg_5_address; /* Data segment 5 address. */ 1611 uint32_t dseg_5_length; /* Data segment 5 length. */ 1612 uint32_t dseg_6_address; /* Data segment 6 address. */ 1613 uint32_t dseg_6_length; /* Data segment 6 length. */ 1614 } cont_entry_t; 1615 1616 /* 1617 * ISP queue - 64-Bit addressing, continuation entry structure definition. 1618 */ 1619 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */ 1620 typedef struct { 1621 uint8_t entry_type; /* Entry type. */ 1622 uint8_t entry_count; /* Entry count. */ 1623 uint8_t sys_define; /* System defined. */ 1624 uint8_t entry_status; /* Entry Status. */ 1625 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1626 uint32_t dseg_0_length; /* Data segment 0 length. */ 1627 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1628 uint32_t dseg_1_length; /* Data segment 1 length. */ 1629 uint32_t dseg_2_address [2]; /* Data segment 2 address. */ 1630 uint32_t dseg_2_length; /* Data segment 2 length. */ 1631 uint32_t dseg_3_address[2]; /* Data segment 3 address. */ 1632 uint32_t dseg_3_length; /* Data segment 3 length. */ 1633 uint32_t dseg_4_address[2]; /* Data segment 4 address. */ 1634 uint32_t dseg_4_length; /* Data segment 4 length. */ 1635 } cont_a64_entry_t; 1636 1637 #define PO_MODE_DIF_INSERT 0 1638 #define PO_MODE_DIF_REMOVE 1 1639 #define PO_MODE_DIF_PASS 2 1640 #define PO_MODE_DIF_REPLACE 3 1641 #define PO_MODE_DIF_TCP_CKSUM 6 1642 #define PO_ENABLE_DIF_BUNDLING BIT_8 1643 #define PO_ENABLE_INCR_GUARD_SEED BIT_3 1644 #define PO_DISABLE_INCR_REF_TAG BIT_5 1645 #define PO_DISABLE_GUARD_CHECK BIT_4 1646 /* 1647 * ISP queue - 64-Bit addressing, continuation crc entry structure definition. 1648 */ 1649 struct crc_context { 1650 uint32_t handle; /* System handle. */ 1651 uint32_t ref_tag; 1652 uint16_t app_tag; 1653 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/ 1654 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/ 1655 uint16_t guard_seed; /* Initial Guard Seed */ 1656 uint16_t prot_opts; /* Requested Data Protection Mode */ 1657 uint16_t blk_size; /* Data size in bytes */ 1658 uint16_t runt_blk_guard; /* Guard value for runt block (tape 1659 * only) */ 1660 uint32_t byte_count; /* Total byte count/ total data 1661 * transfer count */ 1662 union { 1663 struct { 1664 uint32_t reserved_1; 1665 uint16_t reserved_2; 1666 uint16_t reserved_3; 1667 uint32_t reserved_4; 1668 uint32_t data_address[2]; 1669 uint32_t data_length; 1670 uint32_t reserved_5[2]; 1671 uint32_t reserved_6; 1672 } nobundling; 1673 struct { 1674 uint32_t dif_byte_count; /* Total DIF byte 1675 * count */ 1676 uint16_t reserved_1; 1677 uint16_t dseg_count; /* Data segment count */ 1678 uint32_t reserved_2; 1679 uint32_t data_address[2]; 1680 uint32_t data_length; 1681 uint32_t dif_address[2]; 1682 uint32_t dif_length; /* Data segment 0 1683 * length */ 1684 } bundling; 1685 } u; 1686 1687 struct fcp_cmnd fcp_cmnd; 1688 dma_addr_t crc_ctx_dma; 1689 /* List of DMA context transfers */ 1690 struct list_head dsd_list; 1691 1692 /* This structure should not exceed 512 bytes */ 1693 }; 1694 1695 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun)) 1696 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun)) 1697 1698 /* 1699 * ISP queue - status entry structure definition. 1700 */ 1701 #define STATUS_TYPE 0x03 /* Status entry. */ 1702 typedef struct { 1703 uint8_t entry_type; /* Entry type. */ 1704 uint8_t entry_count; /* Entry count. */ 1705 uint8_t sys_define; /* System defined. */ 1706 uint8_t entry_status; /* Entry Status. */ 1707 uint32_t handle; /* System handle. */ 1708 uint16_t scsi_status; /* SCSI status. */ 1709 uint16_t comp_status; /* Completion status. */ 1710 uint16_t state_flags; /* State flags. */ 1711 uint16_t status_flags; /* Status flags. */ 1712 uint16_t rsp_info_len; /* Response Info Length. */ 1713 uint16_t req_sense_length; /* Request sense data length. */ 1714 uint32_t residual_length; /* Residual transfer length. */ 1715 uint8_t rsp_info[8]; /* FCP response information. */ 1716 uint8_t req_sense_data[32]; /* Request sense data. */ 1717 } sts_entry_t; 1718 1719 /* 1720 * Status entry entry status 1721 */ 1722 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */ 1723 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ 1724 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ 1725 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ 1726 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ 1727 #define RF_BUSY BIT_1 /* Busy */ 1728 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \ 1729 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY) 1730 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \ 1731 RF_INV_E_TYPE) 1732 1733 /* 1734 * Status entry SCSI status bit definitions. 1735 */ 1736 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/ 1737 #define SS_RESIDUAL_UNDER BIT_11 1738 #define SS_RESIDUAL_OVER BIT_10 1739 #define SS_SENSE_LEN_VALID BIT_9 1740 #define SS_RESPONSE_INFO_LEN_VALID BIT_8 1741 1742 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) 1743 #define SS_BUSY_CONDITION BIT_3 1744 #define SS_CONDITION_MET BIT_2 1745 #define SS_CHECK_CONDITION BIT_1 1746 1747 /* 1748 * Status entry completion status 1749 */ 1750 #define CS_COMPLETE 0x0 /* No errors */ 1751 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ 1752 #define CS_DMA 0x2 /* A DMA direction error. */ 1753 #define CS_TRANSPORT 0x3 /* Transport error. */ 1754 #define CS_RESET 0x4 /* SCSI bus reset occurred */ 1755 #define CS_ABORTED 0x5 /* System aborted command. */ 1756 #define CS_TIMEOUT 0x6 /* Timeout error. */ 1757 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */ 1758 #define CS_DIF_ERROR 0xC /* DIF error detected */ 1759 1760 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ 1761 #define CS_QUEUE_FULL 0x1C /* Queue Full. */ 1762 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */ 1763 /* (selection timeout) */ 1764 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */ 1765 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */ 1766 #define CS_PORT_BUSY 0x2B /* Port Busy */ 1767 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */ 1768 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */ 1769 #define CS_UNKNOWN 0x81 /* Driver defined */ 1770 #define CS_RETRY 0x82 /* Driver defined */ 1771 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */ 1772 1773 #define CS_BIDIR_RD_OVERRUN 0x700 1774 #define CS_BIDIR_RD_WR_OVERRUN 0x707 1775 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715 1776 #define CS_BIDIR_RD_UNDERRUN 0x1500 1777 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507 1778 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515 1779 #define CS_BIDIR_DMA 0x200 1780 /* 1781 * Status entry status flags 1782 */ 1783 #define SF_ABTS_TERMINATED BIT_10 1784 #define SF_LOGOUT_SENT BIT_13 1785 1786 /* 1787 * ISP queue - status continuation entry structure definition. 1788 */ 1789 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */ 1790 typedef struct { 1791 uint8_t entry_type; /* Entry type. */ 1792 uint8_t entry_count; /* Entry count. */ 1793 uint8_t sys_define; /* System defined. */ 1794 uint8_t entry_status; /* Entry Status. */ 1795 uint8_t data[60]; /* data */ 1796 } sts_cont_entry_t; 1797 1798 /* 1799 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles) 1800 * structure definition. 1801 */ 1802 #define STATUS_TYPE_21 0x21 /* Status entry. */ 1803 typedef struct { 1804 uint8_t entry_type; /* Entry type. */ 1805 uint8_t entry_count; /* Entry count. */ 1806 uint8_t handle_count; /* Handle count. */ 1807 uint8_t entry_status; /* Entry Status. */ 1808 uint32_t handle[15]; /* System handles. */ 1809 } sts21_entry_t; 1810 1811 /* 1812 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles) 1813 * structure definition. 1814 */ 1815 #define STATUS_TYPE_22 0x22 /* Status entry. */ 1816 typedef struct { 1817 uint8_t entry_type; /* Entry type. */ 1818 uint8_t entry_count; /* Entry count. */ 1819 uint8_t handle_count; /* Handle count. */ 1820 uint8_t entry_status; /* Entry Status. */ 1821 uint16_t handle[30]; /* System handles. */ 1822 } sts22_entry_t; 1823 1824 /* 1825 * ISP queue - marker entry structure definition. 1826 */ 1827 #define MARKER_TYPE 0x04 /* Marker entry. */ 1828 typedef struct { 1829 uint8_t entry_type; /* Entry type. */ 1830 uint8_t entry_count; /* Entry count. */ 1831 uint8_t handle_count; /* Handle count. */ 1832 uint8_t entry_status; /* Entry Status. */ 1833 uint32_t sys_define_2; /* System defined. */ 1834 target_id_t target; /* SCSI ID */ 1835 uint8_t modifier; /* Modifier (7-0). */ 1836 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 1837 #define MK_SYNC_ID 1 /* Synchronize ID */ 1838 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 1839 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */ 1840 /* clear port changed, */ 1841 /* use sequence number. */ 1842 uint8_t reserved_1; 1843 uint16_t sequence_number; /* Sequence number of event */ 1844 uint16_t lun; /* SCSI LUN */ 1845 uint8_t reserved_2[48]; 1846 } mrk_entry_t; 1847 1848 /* 1849 * ISP queue - Management Server entry structure definition. 1850 */ 1851 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */ 1852 typedef struct { 1853 uint8_t entry_type; /* Entry type. */ 1854 uint8_t entry_count; /* Entry count. */ 1855 uint8_t handle_count; /* Handle count. */ 1856 uint8_t entry_status; /* Entry Status. */ 1857 uint32_t handle1; /* System handle. */ 1858 target_id_t loop_id; 1859 uint16_t status; 1860 uint16_t control_flags; /* Control flags. */ 1861 uint16_t reserved2; 1862 uint16_t timeout; 1863 uint16_t cmd_dsd_count; 1864 uint16_t total_dsd_count; 1865 uint8_t type; 1866 uint8_t r_ctl; 1867 uint16_t rx_id; 1868 uint16_t reserved3; 1869 uint32_t handle2; 1870 uint32_t rsp_bytecount; 1871 uint32_t req_bytecount; 1872 uint32_t dseg_req_address[2]; /* Data segment 0 address. */ 1873 uint32_t dseg_req_length; /* Data segment 0 length. */ 1874 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */ 1875 uint32_t dseg_rsp_length; /* Data segment 1 length. */ 1876 } ms_iocb_entry_t; 1877 1878 1879 /* 1880 * ISP queue - Mailbox Command entry structure definition. 1881 */ 1882 #define MBX_IOCB_TYPE 0x39 1883 struct mbx_entry { 1884 uint8_t entry_type; 1885 uint8_t entry_count; 1886 uint8_t sys_define1; 1887 /* Use sys_define1 for source type */ 1888 #define SOURCE_SCSI 0x00 1889 #define SOURCE_IP 0x01 1890 #define SOURCE_VI 0x02 1891 #define SOURCE_SCTP 0x03 1892 #define SOURCE_MP 0x04 1893 #define SOURCE_MPIOCTL 0x05 1894 #define SOURCE_ASYNC_IOCB 0x07 1895 1896 uint8_t entry_status; 1897 1898 uint32_t handle; 1899 target_id_t loop_id; 1900 1901 uint16_t status; 1902 uint16_t state_flags; 1903 uint16_t status_flags; 1904 1905 uint32_t sys_define2[2]; 1906 1907 uint16_t mb0; 1908 uint16_t mb1; 1909 uint16_t mb2; 1910 uint16_t mb3; 1911 uint16_t mb6; 1912 uint16_t mb7; 1913 uint16_t mb9; 1914 uint16_t mb10; 1915 uint32_t reserved_2[2]; 1916 uint8_t node_name[WWN_SIZE]; 1917 uint8_t port_name[WWN_SIZE]; 1918 }; 1919 1920 /* 1921 * ISP request and response queue entry sizes 1922 */ 1923 #define RESPONSE_ENTRY_SIZE (sizeof(response_t)) 1924 #define REQUEST_ENTRY_SIZE (sizeof(request_t)) 1925 1926 1927 /* 1928 * 24 bit port ID type definition. 1929 */ 1930 typedef union { 1931 uint32_t b24 : 24; 1932 1933 struct { 1934 #ifdef __BIG_ENDIAN 1935 uint8_t domain; 1936 uint8_t area; 1937 uint8_t al_pa; 1938 #elif defined(__LITTLE_ENDIAN) 1939 uint8_t al_pa; 1940 uint8_t area; 1941 uint8_t domain; 1942 #else 1943 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!" 1944 #endif 1945 uint8_t rsvd_1; 1946 } b; 1947 } port_id_t; 1948 #define INVALID_PORT_ID 0xFFFFFF 1949 1950 /* 1951 * Switch info gathering structure. 1952 */ 1953 typedef struct { 1954 port_id_t d_id; 1955 uint8_t node_name[WWN_SIZE]; 1956 uint8_t port_name[WWN_SIZE]; 1957 uint8_t fabric_port_name[WWN_SIZE]; 1958 uint16_t fp_speed; 1959 uint8_t fc4_type; 1960 } sw_info_t; 1961 1962 /* FCP-4 types */ 1963 #define FC4_TYPE_FCP_SCSI 0x08 1964 #define FC4_TYPE_OTHER 0x0 1965 #define FC4_TYPE_UNKNOWN 0xff 1966 1967 /* 1968 * Fibre channel port type. 1969 */ 1970 typedef enum { 1971 FCT_UNKNOWN, 1972 FCT_RSCN, 1973 FCT_SWITCH, 1974 FCT_BROADCAST, 1975 FCT_INITIATOR, 1976 FCT_TARGET 1977 } fc_port_type_t; 1978 1979 /* 1980 * Fibre channel port structure. 1981 */ 1982 typedef struct fc_port { 1983 struct list_head list; 1984 struct scsi_qla_host *vha; 1985 1986 uint8_t node_name[WWN_SIZE]; 1987 uint8_t port_name[WWN_SIZE]; 1988 port_id_t d_id; 1989 uint16_t loop_id; 1990 uint16_t old_loop_id; 1991 1992 uint16_t tgt_id; 1993 uint16_t old_tgt_id; 1994 1995 uint8_t fcp_prio; 1996 1997 uint8_t fabric_port_name[WWN_SIZE]; 1998 uint16_t fp_speed; 1999 2000 fc_port_type_t port_type; 2001 2002 atomic_t state; 2003 uint32_t flags; 2004 2005 int login_retry; 2006 2007 struct fc_rport *rport, *drport; 2008 u32 supported_classes; 2009 2010 uint8_t fc4_type; 2011 uint8_t scan_state; 2012 2013 unsigned long last_queue_full; 2014 unsigned long last_ramp_up; 2015 2016 uint16_t port_id; 2017 } fc_port_t; 2018 2019 #include "qla_mr.h" 2020 2021 /* 2022 * Fibre channel port/lun states. 2023 */ 2024 #define FCS_UNCONFIGURED 1 2025 #define FCS_DEVICE_DEAD 2 2026 #define FCS_DEVICE_LOST 3 2027 #define FCS_ONLINE 4 2028 2029 static const char * const port_state_str[] = { 2030 "Unknown", 2031 "UNCONFIGURED", 2032 "DEAD", 2033 "LOST", 2034 "ONLINE" 2035 }; 2036 2037 /* 2038 * FC port flags. 2039 */ 2040 #define FCF_FABRIC_DEVICE BIT_0 2041 #define FCF_LOGIN_NEEDED BIT_1 2042 #define FCF_FCP2_DEVICE BIT_2 2043 #define FCF_ASYNC_SENT BIT_3 2044 #define FCF_CONF_COMP_SUPPORTED BIT_4 2045 2046 /* No loop ID flag. */ 2047 #define FC_NO_LOOP_ID 0x1000 2048 2049 /* 2050 * FC-CT interface 2051 * 2052 * NOTE: All structures are big-endian in form. 2053 */ 2054 2055 #define CT_REJECT_RESPONSE 0x8001 2056 #define CT_ACCEPT_RESPONSE 0x8002 2057 #define CT_REASON_INVALID_COMMAND_CODE 0x01 2058 #define CT_REASON_CANNOT_PERFORM 0x09 2059 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b 2060 #define CT_EXPL_ALREADY_REGISTERED 0x10 2061 2062 #define NS_N_PORT_TYPE 0x01 2063 #define NS_NL_PORT_TYPE 0x02 2064 #define NS_NX_PORT_TYPE 0x7F 2065 2066 #define GA_NXT_CMD 0x100 2067 #define GA_NXT_REQ_SIZE (16 + 4) 2068 #define GA_NXT_RSP_SIZE (16 + 620) 2069 2070 #define GID_PT_CMD 0x1A1 2071 #define GID_PT_REQ_SIZE (16 + 4) 2072 2073 #define GPN_ID_CMD 0x112 2074 #define GPN_ID_REQ_SIZE (16 + 4) 2075 #define GPN_ID_RSP_SIZE (16 + 8) 2076 2077 #define GNN_ID_CMD 0x113 2078 #define GNN_ID_REQ_SIZE (16 + 4) 2079 #define GNN_ID_RSP_SIZE (16 + 8) 2080 2081 #define GFT_ID_CMD 0x117 2082 #define GFT_ID_REQ_SIZE (16 + 4) 2083 #define GFT_ID_RSP_SIZE (16 + 32) 2084 2085 #define RFT_ID_CMD 0x217 2086 #define RFT_ID_REQ_SIZE (16 + 4 + 32) 2087 #define RFT_ID_RSP_SIZE 16 2088 2089 #define RFF_ID_CMD 0x21F 2090 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1) 2091 #define RFF_ID_RSP_SIZE 16 2092 2093 #define RNN_ID_CMD 0x213 2094 #define RNN_ID_REQ_SIZE (16 + 4 + 8) 2095 #define RNN_ID_RSP_SIZE 16 2096 2097 #define RSNN_NN_CMD 0x239 2098 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255) 2099 #define RSNN_NN_RSP_SIZE 16 2100 2101 #define GFPN_ID_CMD 0x11C 2102 #define GFPN_ID_REQ_SIZE (16 + 4) 2103 #define GFPN_ID_RSP_SIZE (16 + 8) 2104 2105 #define GPSC_CMD 0x127 2106 #define GPSC_REQ_SIZE (16 + 8) 2107 #define GPSC_RSP_SIZE (16 + 2 + 2) 2108 2109 #define GFF_ID_CMD 0x011F 2110 #define GFF_ID_REQ_SIZE (16 + 4) 2111 #define GFF_ID_RSP_SIZE (16 + 128) 2112 2113 /* 2114 * HBA attribute types. 2115 */ 2116 #define FDMI_HBA_ATTR_COUNT 9 2117 #define FDMI_HBA_NODE_NAME 1 2118 #define FDMI_HBA_MANUFACTURER 2 2119 #define FDMI_HBA_SERIAL_NUMBER 3 2120 #define FDMI_HBA_MODEL 4 2121 #define FDMI_HBA_MODEL_DESCRIPTION 5 2122 #define FDMI_HBA_HARDWARE_VERSION 6 2123 #define FDMI_HBA_DRIVER_VERSION 7 2124 #define FDMI_HBA_OPTION_ROM_VERSION 8 2125 #define FDMI_HBA_FIRMWARE_VERSION 9 2126 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa 2127 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb 2128 2129 struct ct_fdmi_hba_attr { 2130 uint16_t type; 2131 uint16_t len; 2132 union { 2133 uint8_t node_name[WWN_SIZE]; 2134 uint8_t manufacturer[32]; 2135 uint8_t serial_num[8]; 2136 uint8_t model[16]; 2137 uint8_t model_desc[80]; 2138 uint8_t hw_version[16]; 2139 uint8_t driver_version[32]; 2140 uint8_t orom_version[16]; 2141 uint8_t fw_version[16]; 2142 uint8_t os_version[128]; 2143 uint8_t max_ct_len[4]; 2144 } a; 2145 }; 2146 2147 struct ct_fdmi_hba_attributes { 2148 uint32_t count; 2149 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT]; 2150 }; 2151 2152 /* 2153 * Port attribute types. 2154 */ 2155 #define FDMI_PORT_ATTR_COUNT 6 2156 #define FDMI_PORT_FC4_TYPES 1 2157 #define FDMI_PORT_SUPPORT_SPEED 2 2158 #define FDMI_PORT_CURRENT_SPEED 3 2159 #define FDMI_PORT_MAX_FRAME_SIZE 4 2160 #define FDMI_PORT_OS_DEVICE_NAME 5 2161 #define FDMI_PORT_HOST_NAME 6 2162 2163 #define FDMI_PORT_SPEED_1GB 0x1 2164 #define FDMI_PORT_SPEED_2GB 0x2 2165 #define FDMI_PORT_SPEED_10GB 0x4 2166 #define FDMI_PORT_SPEED_4GB 0x8 2167 #define FDMI_PORT_SPEED_8GB 0x10 2168 #define FDMI_PORT_SPEED_16GB 0x20 2169 #define FDMI_PORT_SPEED_UNKNOWN 0x8000 2170 2171 struct ct_fdmi_port_attr { 2172 uint16_t type; 2173 uint16_t len; 2174 union { 2175 uint8_t fc4_types[32]; 2176 uint32_t sup_speed; 2177 uint32_t cur_speed; 2178 uint32_t max_frame_size; 2179 uint8_t os_dev_name[32]; 2180 uint8_t host_name[32]; 2181 } a; 2182 }; 2183 2184 /* 2185 * Port Attribute Block. 2186 */ 2187 struct ct_fdmi_port_attributes { 2188 uint32_t count; 2189 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT]; 2190 }; 2191 2192 /* FDMI definitions. */ 2193 #define GRHL_CMD 0x100 2194 #define GHAT_CMD 0x101 2195 #define GRPL_CMD 0x102 2196 #define GPAT_CMD 0x110 2197 2198 #define RHBA_CMD 0x200 2199 #define RHBA_RSP_SIZE 16 2200 2201 #define RHAT_CMD 0x201 2202 #define RPRT_CMD 0x210 2203 2204 #define RPA_CMD 0x211 2205 #define RPA_RSP_SIZE 16 2206 2207 #define DHBA_CMD 0x300 2208 #define DHBA_REQ_SIZE (16 + 8) 2209 #define DHBA_RSP_SIZE 16 2210 2211 #define DHAT_CMD 0x301 2212 #define DPRT_CMD 0x310 2213 #define DPA_CMD 0x311 2214 2215 /* CT command header -- request/response common fields */ 2216 struct ct_cmd_hdr { 2217 uint8_t revision; 2218 uint8_t in_id[3]; 2219 uint8_t gs_type; 2220 uint8_t gs_subtype; 2221 uint8_t options; 2222 uint8_t reserved; 2223 }; 2224 2225 /* CT command request */ 2226 struct ct_sns_req { 2227 struct ct_cmd_hdr header; 2228 uint16_t command; 2229 uint16_t max_rsp_size; 2230 uint8_t fragment_id; 2231 uint8_t reserved[3]; 2232 2233 union { 2234 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */ 2235 struct { 2236 uint8_t reserved; 2237 uint8_t port_id[3]; 2238 } port_id; 2239 2240 struct { 2241 uint8_t port_type; 2242 uint8_t domain; 2243 uint8_t area; 2244 uint8_t reserved; 2245 } gid_pt; 2246 2247 struct { 2248 uint8_t reserved; 2249 uint8_t port_id[3]; 2250 uint8_t fc4_types[32]; 2251 } rft_id; 2252 2253 struct { 2254 uint8_t reserved; 2255 uint8_t port_id[3]; 2256 uint16_t reserved2; 2257 uint8_t fc4_feature; 2258 uint8_t fc4_type; 2259 } rff_id; 2260 2261 struct { 2262 uint8_t reserved; 2263 uint8_t port_id[3]; 2264 uint8_t node_name[8]; 2265 } rnn_id; 2266 2267 struct { 2268 uint8_t node_name[8]; 2269 uint8_t name_len; 2270 uint8_t sym_node_name[255]; 2271 } rsnn_nn; 2272 2273 struct { 2274 uint8_t hba_indentifier[8]; 2275 } ghat; 2276 2277 struct { 2278 uint8_t hba_identifier[8]; 2279 uint32_t entry_count; 2280 uint8_t port_name[8]; 2281 struct ct_fdmi_hba_attributes attrs; 2282 } rhba; 2283 2284 struct { 2285 uint8_t hba_identifier[8]; 2286 struct ct_fdmi_hba_attributes attrs; 2287 } rhat; 2288 2289 struct { 2290 uint8_t port_name[8]; 2291 struct ct_fdmi_port_attributes attrs; 2292 } rpa; 2293 2294 struct { 2295 uint8_t port_name[8]; 2296 } dhba; 2297 2298 struct { 2299 uint8_t port_name[8]; 2300 } dhat; 2301 2302 struct { 2303 uint8_t port_name[8]; 2304 } dprt; 2305 2306 struct { 2307 uint8_t port_name[8]; 2308 } dpa; 2309 2310 struct { 2311 uint8_t port_name[8]; 2312 } gpsc; 2313 2314 struct { 2315 uint8_t reserved; 2316 uint8_t port_name[3]; 2317 } gff_id; 2318 } req; 2319 }; 2320 2321 /* CT command response header */ 2322 struct ct_rsp_hdr { 2323 struct ct_cmd_hdr header; 2324 uint16_t response; 2325 uint16_t residual; 2326 uint8_t fragment_id; 2327 uint8_t reason_code; 2328 uint8_t explanation_code; 2329 uint8_t vendor_unique; 2330 }; 2331 2332 struct ct_sns_gid_pt_data { 2333 uint8_t control_byte; 2334 uint8_t port_id[3]; 2335 }; 2336 2337 struct ct_sns_rsp { 2338 struct ct_rsp_hdr header; 2339 2340 union { 2341 struct { 2342 uint8_t port_type; 2343 uint8_t port_id[3]; 2344 uint8_t port_name[8]; 2345 uint8_t sym_port_name_len; 2346 uint8_t sym_port_name[255]; 2347 uint8_t node_name[8]; 2348 uint8_t sym_node_name_len; 2349 uint8_t sym_node_name[255]; 2350 uint8_t init_proc_assoc[8]; 2351 uint8_t node_ip_addr[16]; 2352 uint8_t class_of_service[4]; 2353 uint8_t fc4_types[32]; 2354 uint8_t ip_address[16]; 2355 uint8_t fabric_port_name[8]; 2356 uint8_t reserved; 2357 uint8_t hard_address[3]; 2358 } ga_nxt; 2359 2360 struct { 2361 /* Assume the largest number of targets for the union */ 2362 struct ct_sns_gid_pt_data 2363 entries[MAX_FIBRE_DEVICES_MAX]; 2364 } gid_pt; 2365 2366 struct { 2367 uint8_t port_name[8]; 2368 } gpn_id; 2369 2370 struct { 2371 uint8_t node_name[8]; 2372 } gnn_id; 2373 2374 struct { 2375 uint8_t fc4_types[32]; 2376 } gft_id; 2377 2378 struct { 2379 uint32_t entry_count; 2380 uint8_t port_name[8]; 2381 struct ct_fdmi_hba_attributes attrs; 2382 } ghat; 2383 2384 struct { 2385 uint8_t port_name[8]; 2386 } gfpn_id; 2387 2388 struct { 2389 uint16_t speeds; 2390 uint16_t speed; 2391 } gpsc; 2392 2393 #define GFF_FCP_SCSI_OFFSET 7 2394 struct { 2395 uint8_t fc4_features[128]; 2396 } gff_id; 2397 } rsp; 2398 }; 2399 2400 struct ct_sns_pkt { 2401 union { 2402 struct ct_sns_req req; 2403 struct ct_sns_rsp rsp; 2404 } p; 2405 }; 2406 2407 /* 2408 * SNS command structures -- for 2200 compatibility. 2409 */ 2410 #define RFT_ID_SNS_SCMD_LEN 22 2411 #define RFT_ID_SNS_CMD_SIZE 60 2412 #define RFT_ID_SNS_DATA_SIZE 16 2413 2414 #define RNN_ID_SNS_SCMD_LEN 10 2415 #define RNN_ID_SNS_CMD_SIZE 36 2416 #define RNN_ID_SNS_DATA_SIZE 16 2417 2418 #define GA_NXT_SNS_SCMD_LEN 6 2419 #define GA_NXT_SNS_CMD_SIZE 28 2420 #define GA_NXT_SNS_DATA_SIZE (620 + 16) 2421 2422 #define GID_PT_SNS_SCMD_LEN 6 2423 #define GID_PT_SNS_CMD_SIZE 28 2424 /* 2425 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older 2426 * adapters. 2427 */ 2428 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16) 2429 2430 #define GPN_ID_SNS_SCMD_LEN 6 2431 #define GPN_ID_SNS_CMD_SIZE 28 2432 #define GPN_ID_SNS_DATA_SIZE (8 + 16) 2433 2434 #define GNN_ID_SNS_SCMD_LEN 6 2435 #define GNN_ID_SNS_CMD_SIZE 28 2436 #define GNN_ID_SNS_DATA_SIZE (8 + 16) 2437 2438 struct sns_cmd_pkt { 2439 union { 2440 struct { 2441 uint16_t buffer_length; 2442 uint16_t reserved_1; 2443 uint32_t buffer_address[2]; 2444 uint16_t subcommand_length; 2445 uint16_t reserved_2; 2446 uint16_t subcommand; 2447 uint16_t size; 2448 uint32_t reserved_3; 2449 uint8_t param[36]; 2450 } cmd; 2451 2452 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE]; 2453 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE]; 2454 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE]; 2455 uint8_t gid_data[GID_PT_SNS_DATA_SIZE]; 2456 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE]; 2457 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE]; 2458 } p; 2459 }; 2460 2461 struct fw_blob { 2462 char *name; 2463 uint32_t segs[4]; 2464 const struct firmware *fw; 2465 }; 2466 2467 /* Return data from MBC_GET_ID_LIST call. */ 2468 struct gid_list_info { 2469 uint8_t al_pa; 2470 uint8_t area; 2471 uint8_t domain; 2472 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */ 2473 uint16_t loop_id; /* ISP23XX -- 6 bytes. */ 2474 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */ 2475 }; 2476 2477 /* NPIV */ 2478 typedef struct vport_info { 2479 uint8_t port_name[WWN_SIZE]; 2480 uint8_t node_name[WWN_SIZE]; 2481 int vp_id; 2482 uint16_t loop_id; 2483 unsigned long host_no; 2484 uint8_t port_id[3]; 2485 int loop_state; 2486 } vport_info_t; 2487 2488 typedef struct vport_params { 2489 uint8_t port_name[WWN_SIZE]; 2490 uint8_t node_name[WWN_SIZE]; 2491 uint32_t options; 2492 #define VP_OPTS_RETRY_ENABLE BIT_0 2493 #define VP_OPTS_VP_DISABLE BIT_1 2494 } vport_params_t; 2495 2496 /* NPIV - return codes of VP create and modify */ 2497 #define VP_RET_CODE_OK 0 2498 #define VP_RET_CODE_FATAL 1 2499 #define VP_RET_CODE_WRONG_ID 2 2500 #define VP_RET_CODE_WWPN 3 2501 #define VP_RET_CODE_RESOURCES 4 2502 #define VP_RET_CODE_NO_MEM 5 2503 #define VP_RET_CODE_NOT_FOUND 6 2504 2505 struct qla_hw_data; 2506 struct rsp_que; 2507 /* 2508 * ISP operations 2509 */ 2510 struct isp_operations { 2511 2512 int (*pci_config) (struct scsi_qla_host *); 2513 void (*reset_chip) (struct scsi_qla_host *); 2514 int (*chip_diag) (struct scsi_qla_host *); 2515 void (*config_rings) (struct scsi_qla_host *); 2516 void (*reset_adapter) (struct scsi_qla_host *); 2517 int (*nvram_config) (struct scsi_qla_host *); 2518 void (*update_fw_options) (struct scsi_qla_host *); 2519 int (*load_risc) (struct scsi_qla_host *, uint32_t *); 2520 2521 char * (*pci_info_str) (struct scsi_qla_host *, char *); 2522 char * (*fw_version_str) (struct scsi_qla_host *, char *); 2523 2524 irq_handler_t intr_handler; 2525 void (*enable_intrs) (struct qla_hw_data *); 2526 void (*disable_intrs) (struct qla_hw_data *); 2527 2528 int (*abort_command) (srb_t *); 2529 int (*target_reset) (struct fc_port *, unsigned int, int); 2530 int (*lun_reset) (struct fc_port *, unsigned int, int); 2531 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t, 2532 uint8_t, uint8_t, uint16_t *, uint8_t); 2533 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t, 2534 uint8_t, uint8_t); 2535 2536 uint16_t (*calc_req_entries) (uint16_t); 2537 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t); 2538 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t); 2539 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t, 2540 uint32_t); 2541 2542 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *, 2543 uint32_t, uint32_t); 2544 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t, 2545 uint32_t); 2546 2547 void (*fw_dump) (struct scsi_qla_host *, int); 2548 2549 int (*beacon_on) (struct scsi_qla_host *); 2550 int (*beacon_off) (struct scsi_qla_host *); 2551 void (*beacon_blink) (struct scsi_qla_host *); 2552 2553 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *, 2554 uint32_t, uint32_t); 2555 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t, 2556 uint32_t); 2557 2558 int (*get_flash_version) (struct scsi_qla_host *, void *); 2559 int (*start_scsi) (srb_t *); 2560 int (*abort_isp) (struct scsi_qla_host *); 2561 int (*iospace_config)(struct qla_hw_data*); 2562 int (*initialize_adapter)(struct scsi_qla_host *); 2563 }; 2564 2565 /* MSI-X Support *************************************************************/ 2566 2567 #define QLA_MSIX_CHIP_REV_24XX 3 2568 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7) 2569 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1) 2570 2571 #define QLA_MSIX_DEFAULT 0x00 2572 #define QLA_MSIX_RSP_Q 0x01 2573 2574 #define QLA_MIDX_DEFAULT 0 2575 #define QLA_MIDX_RSP_Q 1 2576 #define QLA_PCI_MSIX_CONTROL 0xa2 2577 #define QLA_83XX_PCI_MSIX_CONTROL 0x92 2578 2579 struct scsi_qla_host; 2580 2581 struct qla_msix_entry { 2582 int have_irq; 2583 uint32_t vector; 2584 uint16_t entry; 2585 struct rsp_que *rsp; 2586 }; 2587 2588 #define WATCH_INTERVAL 1 /* number of seconds */ 2589 2590 /* Work events. */ 2591 enum qla_work_type { 2592 QLA_EVT_AEN, 2593 QLA_EVT_IDC_ACK, 2594 QLA_EVT_ASYNC_LOGIN, 2595 QLA_EVT_ASYNC_LOGIN_DONE, 2596 QLA_EVT_ASYNC_LOGOUT, 2597 QLA_EVT_ASYNC_LOGOUT_DONE, 2598 QLA_EVT_ASYNC_ADISC, 2599 QLA_EVT_ASYNC_ADISC_DONE, 2600 QLA_EVT_UEVENT, 2601 QLA_EVT_AENFX, 2602 }; 2603 2604 2605 struct qla_work_evt { 2606 struct list_head list; 2607 enum qla_work_type type; 2608 u32 flags; 2609 #define QLA_EVT_FLAG_FREE 0x1 2610 2611 union { 2612 struct { 2613 enum fc_host_event_code code; 2614 u32 data; 2615 } aen; 2616 struct { 2617 #define QLA_IDC_ACK_REGS 7 2618 uint16_t mb[QLA_IDC_ACK_REGS]; 2619 } idc_ack; 2620 struct { 2621 struct fc_port *fcport; 2622 #define QLA_LOGIO_LOGIN_RETRIED BIT_0 2623 u16 data[2]; 2624 } logio; 2625 struct { 2626 u32 code; 2627 #define QLA_UEVENT_CODE_FW_DUMP 0 2628 } uevent; 2629 struct { 2630 uint32_t evtcode; 2631 uint32_t mbx[8]; 2632 uint32_t count; 2633 } aenfx; 2634 struct { 2635 srb_t *sp; 2636 } iosb; 2637 } u; 2638 }; 2639 2640 struct qla_chip_state_84xx { 2641 struct list_head list; 2642 struct kref kref; 2643 2644 void *bus; 2645 spinlock_t access_lock; 2646 struct mutex fw_update_mutex; 2647 uint32_t fw_update; 2648 uint32_t op_fw_version; 2649 uint32_t op_fw_size; 2650 uint32_t op_fw_seq_size; 2651 uint32_t diag_fw_version; 2652 uint32_t gold_fw_version; 2653 }; 2654 2655 struct qla_statistics { 2656 uint32_t total_isp_aborts; 2657 uint64_t input_bytes; 2658 uint64_t output_bytes; 2659 }; 2660 2661 struct bidi_statistics { 2662 unsigned long long io_count; 2663 unsigned long long transfer_bytes; 2664 }; 2665 2666 /* Multi queue support */ 2667 #define MBC_INITIALIZE_MULTIQ 0x1f 2668 #define QLA_QUE_PAGE 0X1000 2669 #define QLA_MQ_SIZE 32 2670 #define QLA_MAX_QUEUES 256 2671 #define ISP_QUE_REG(ha, id) \ 2672 ((ha->mqenable || IS_QLA83XX(ha)) ? \ 2673 ((device_reg_t __iomem *)(ha->mqiobase) +\ 2674 (QLA_QUE_PAGE * id)) :\ 2675 ((device_reg_t __iomem *)(ha->iobase))) 2676 #define QLA_REQ_QUE_ID(tag) \ 2677 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0) 2678 #define QLA_DEFAULT_QUE_QOS 5 2679 #define QLA_PRECONFIG_VPORTS 32 2680 #define QLA_MAX_VPORTS_QLA24XX 128 2681 #define QLA_MAX_VPORTS_QLA25XX 256 2682 /* Response queue data structure */ 2683 struct rsp_que { 2684 dma_addr_t dma; 2685 response_t *ring; 2686 response_t *ring_ptr; 2687 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */ 2688 uint32_t __iomem *rsp_q_out; 2689 uint16_t ring_index; 2690 uint16_t out_ptr; 2691 uint16_t length; 2692 uint16_t options; 2693 uint16_t rid; 2694 uint16_t id; 2695 uint16_t vp_idx; 2696 struct qla_hw_data *hw; 2697 struct qla_msix_entry *msix; 2698 struct req_que *req; 2699 srb_t *status_srb; /* status continuation entry */ 2700 struct work_struct q_work; 2701 2702 dma_addr_t dma_fx00; 2703 response_t *ring_fx00; 2704 uint16_t length_fx00; 2705 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE]; 2706 }; 2707 2708 /* Request queue data structure */ 2709 struct req_que { 2710 dma_addr_t dma; 2711 request_t *ring; 2712 request_t *ring_ptr; 2713 uint32_t __iomem *req_q_in; /* FWI2-capable only. */ 2714 uint32_t __iomem *req_q_out; 2715 uint16_t ring_index; 2716 uint16_t in_ptr; 2717 uint16_t cnt; 2718 uint16_t length; 2719 uint16_t options; 2720 uint16_t rid; 2721 uint16_t id; 2722 uint16_t qos; 2723 uint16_t vp_idx; 2724 struct rsp_que *rsp; 2725 srb_t **outstanding_cmds; 2726 uint32_t current_outstanding_cmd; 2727 uint16_t num_outstanding_cmds; 2728 #define MAX_Q_DEPTH 32 2729 int max_q_depth; 2730 2731 dma_addr_t dma_fx00; 2732 request_t *ring_fx00; 2733 uint16_t length_fx00; 2734 uint8_t req_pkt[REQUEST_ENTRY_SIZE]; 2735 }; 2736 2737 /* Place holder for FW buffer parameters */ 2738 struct qlfc_fw { 2739 void *fw_buf; 2740 dma_addr_t fw_dma; 2741 uint32_t len; 2742 }; 2743 2744 struct qlt_hw_data { 2745 /* Protected by hw lock */ 2746 uint32_t enable_class_2:1; 2747 uint32_t enable_explicit_conf:1; 2748 uint32_t ini_mode_force_reverse:1; 2749 uint32_t node_name_set:1; 2750 2751 dma_addr_t atio_dma; /* Physical address. */ 2752 struct atio *atio_ring; /* Base virtual address */ 2753 struct atio *atio_ring_ptr; /* Current address. */ 2754 uint16_t atio_ring_index; /* Current index. */ 2755 uint16_t atio_q_length; 2756 uint32_t __iomem *atio_q_in; 2757 uint32_t __iomem *atio_q_out; 2758 2759 void *target_lport_ptr; 2760 struct qla_tgt_func_tmpl *tgt_ops; 2761 struct qla_tgt *qla_tgt; 2762 struct qla_tgt_cmd *cmds[DEFAULT_OUTSTANDING_COMMANDS]; 2763 uint16_t current_handle; 2764 2765 struct qla_tgt_vp_map *tgt_vp_map; 2766 struct mutex tgt_mutex; 2767 struct mutex tgt_host_action_mutex; 2768 2769 int saved_set; 2770 uint16_t saved_exchange_count; 2771 uint32_t saved_firmware_options_1; 2772 uint32_t saved_firmware_options_2; 2773 uint32_t saved_firmware_options_3; 2774 uint8_t saved_firmware_options[2]; 2775 uint8_t saved_add_firmware_options[2]; 2776 2777 uint8_t tgt_node_name[WWN_SIZE]; 2778 }; 2779 2780 /* 2781 * Qlogic host adapter specific data structure. 2782 */ 2783 struct qla_hw_data { 2784 struct pci_dev *pdev; 2785 /* SRB cache. */ 2786 #define SRB_MIN_REQ 128 2787 mempool_t *srb_mempool; 2788 2789 volatile struct { 2790 uint32_t mbox_int :1; 2791 uint32_t mbox_busy :1; 2792 uint32_t disable_risc_code_load :1; 2793 uint32_t enable_64bit_addressing :1; 2794 uint32_t enable_lip_reset :1; 2795 uint32_t enable_target_reset :1; 2796 uint32_t enable_lip_full_login :1; 2797 uint32_t enable_led_scheme :1; 2798 2799 uint32_t msi_enabled :1; 2800 uint32_t msix_enabled :1; 2801 uint32_t disable_serdes :1; 2802 uint32_t gpsc_supported :1; 2803 uint32_t npiv_supported :1; 2804 uint32_t pci_channel_io_perm_failure :1; 2805 uint32_t fce_enabled :1; 2806 uint32_t fac_supported :1; 2807 2808 uint32_t chip_reset_done :1; 2809 uint32_t port0 :1; 2810 uint32_t running_gold_fw :1; 2811 uint32_t eeh_busy :1; 2812 uint32_t cpu_affinity_enabled :1; 2813 uint32_t disable_msix_handshake :1; 2814 uint32_t fcp_prio_enabled :1; 2815 uint32_t isp82xx_fw_hung:1; 2816 uint32_t nic_core_hung:1; 2817 2818 uint32_t quiesce_owner:1; 2819 uint32_t nic_core_reset_hdlr_active:1; 2820 uint32_t nic_core_reset_owner:1; 2821 uint32_t isp82xx_no_md_cap:1; 2822 uint32_t host_shutting_down:1; 2823 uint32_t idc_compl_status:1; 2824 2825 uint32_t mr_reset_hdlr_active:1; 2826 uint32_t mr_intr_valid:1; 2827 /* 34 bits */ 2828 } flags; 2829 2830 /* This spinlock is used to protect "io transactions", you must 2831 * acquire it before doing any IO to the card, eg with RD_REG*() and 2832 * WRT_REG*() for the duration of your entire commandtransaction. 2833 * 2834 * This spinlock is of lower priority than the io request lock. 2835 */ 2836 2837 spinlock_t hardware_lock ____cacheline_aligned; 2838 int bars; 2839 int mem_only; 2840 device_reg_t __iomem *iobase; /* Base I/O address */ 2841 resource_size_t pio_address; 2842 2843 #define MIN_IOBASE_LEN 0x100 2844 dma_addr_t bar0_hdl; 2845 2846 void __iomem *cregbase; 2847 dma_addr_t bar2_hdl; 2848 #define BAR0_LEN_FX00 (1024 * 1024) 2849 #define BAR2_LEN_FX00 (128 * 1024) 2850 2851 uint32_t rqstq_intr_code; 2852 uint32_t mbx_intr_code; 2853 uint32_t req_que_len; 2854 uint32_t rsp_que_len; 2855 uint32_t req_que_off; 2856 uint32_t rsp_que_off; 2857 2858 /* Multi queue data structs */ 2859 device_reg_t __iomem *mqiobase; 2860 device_reg_t __iomem *msixbase; 2861 uint16_t msix_count; 2862 uint8_t mqenable; 2863 struct req_que **req_q_map; 2864 struct rsp_que **rsp_q_map; 2865 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 2866 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 2867 uint8_t max_req_queues; 2868 uint8_t max_rsp_queues; 2869 struct qla_npiv_entry *npiv_info; 2870 uint16_t nvram_npiv_size; 2871 2872 uint16_t switch_cap; 2873 #define FLOGI_SEQ_DEL BIT_8 2874 #define FLOGI_MID_SUPPORT BIT_10 2875 #define FLOGI_VSAN_SUPPORT BIT_12 2876 #define FLOGI_SP_SUPPORT BIT_13 2877 2878 uint8_t port_no; /* Physical port of adapter */ 2879 2880 /* Timeout timers. */ 2881 uint8_t loop_down_abort_time; /* port down timer */ 2882 atomic_t loop_down_timer; /* loop down timer */ 2883 uint8_t link_down_timeout; /* link down timeout */ 2884 uint16_t max_loop_id; 2885 uint16_t max_fibre_devices; /* Maximum number of targets */ 2886 2887 uint16_t fb_rev; 2888 uint16_t min_external_loopid; /* First external loop Id */ 2889 2890 #define PORT_SPEED_UNKNOWN 0xFFFF 2891 #define PORT_SPEED_1GB 0x00 2892 #define PORT_SPEED_2GB 0x01 2893 #define PORT_SPEED_4GB 0x03 2894 #define PORT_SPEED_8GB 0x04 2895 #define PORT_SPEED_16GB 0x05 2896 #define PORT_SPEED_10GB 0x13 2897 uint16_t link_data_rate; /* F/W operating speed */ 2898 2899 uint8_t current_topology; 2900 uint8_t prev_topology; 2901 #define ISP_CFG_NL 1 2902 #define ISP_CFG_N 2 2903 #define ISP_CFG_FL 4 2904 #define ISP_CFG_F 8 2905 2906 uint8_t operating_mode; /* F/W operating mode */ 2907 #define LOOP 0 2908 #define P2P 1 2909 #define LOOP_P2P 2 2910 #define P2P_LOOP 3 2911 uint8_t interrupts_on; 2912 uint32_t isp_abort_cnt; 2913 2914 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 2915 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432 2916 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001 2917 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031 2918 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031 2919 uint32_t device_type; 2920 #define DT_ISP2100 BIT_0 2921 #define DT_ISP2200 BIT_1 2922 #define DT_ISP2300 BIT_2 2923 #define DT_ISP2312 BIT_3 2924 #define DT_ISP2322 BIT_4 2925 #define DT_ISP6312 BIT_5 2926 #define DT_ISP6322 BIT_6 2927 #define DT_ISP2422 BIT_7 2928 #define DT_ISP2432 BIT_8 2929 #define DT_ISP5422 BIT_9 2930 #define DT_ISP5432 BIT_10 2931 #define DT_ISP2532 BIT_11 2932 #define DT_ISP8432 BIT_12 2933 #define DT_ISP8001 BIT_13 2934 #define DT_ISP8021 BIT_14 2935 #define DT_ISP2031 BIT_15 2936 #define DT_ISP8031 BIT_16 2937 #define DT_ISPFX00 BIT_17 2938 #define DT_ISP_LAST (DT_ISPFX00 << 1) 2939 2940 #define DT_T10_PI BIT_25 2941 #define DT_IIDMA BIT_26 2942 #define DT_FWI2 BIT_27 2943 #define DT_ZIO_SUPPORTED BIT_28 2944 #define DT_OEM_001 BIT_29 2945 #define DT_ISP2200A BIT_30 2946 #define DT_EXTENDED_IDS BIT_31 2947 #define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1)) 2948 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100) 2949 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200) 2950 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300) 2951 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312) 2952 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322) 2953 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312) 2954 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322) 2955 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422) 2956 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432) 2957 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422) 2958 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) 2959 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) 2960 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) 2961 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001) 2962 #define IS_QLA81XX(ha) (IS_QLA8001(ha)) 2963 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021) 2964 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031) 2965 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031) 2966 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00) 2967 2968 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ 2969 IS_QLA6312(ha) || IS_QLA6322(ha)) 2970 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) 2971 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) 2972 #define IS_QLA25XX(ha) (IS_QLA2532(ha)) 2973 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha)) 2974 #define IS_QLA84XX(ha) (IS_QLA8432(ha)) 2975 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \ 2976 IS_QLA84XX(ha)) 2977 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \ 2978 IS_QLA8031(ha)) 2979 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \ 2980 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \ 2981 IS_QLA82XX(ha) || IS_QLA83XX(ha)) 2982 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha)) 2983 #define IS_NOPOLLING_TYPE(ha) ((IS_QLA25XX(ha) || IS_QLA81XX(ha) || \ 2984 IS_QLA83XX(ha)) && (ha)->flags.msix_enabled) 2985 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha)) 2986 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha)) 2987 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha)) 2988 2989 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI) 2990 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) 2991 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2) 2992 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED) 2993 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001) 2994 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS) 2995 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED) 2996 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha)) 2997 #define IS_BIDI_CAPABLE(ha) ((IS_QLA25XX(ha) || IS_QLA2031(ha))) 2998 /* Bit 21 of fw_attributes decides the MCTP capabilities */ 2999 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \ 3000 ((ha)->fw_attributes_ext[0] & BIT_0)) 3001 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha)) 3002 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha)) 3003 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0) 3004 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha)) 3005 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \ 3006 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22)) 3007 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha)) 3008 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length) 3009 3010 /* HBA serial number */ 3011 uint8_t serial0; 3012 uint8_t serial1; 3013 uint8_t serial2; 3014 3015 /* NVRAM configuration data */ 3016 #define MAX_NVRAM_SIZE 4096 3017 #define VPD_OFFSET MAX_NVRAM_SIZE / 2 3018 uint16_t nvram_size; 3019 uint16_t nvram_base; 3020 void *nvram; 3021 uint16_t vpd_size; 3022 uint16_t vpd_base; 3023 void *vpd; 3024 3025 uint16_t loop_reset_delay; 3026 uint8_t retry_count; 3027 uint8_t login_timeout; 3028 uint16_t r_a_tov; 3029 int port_down_retry_count; 3030 uint8_t mbx_count; 3031 uint8_t aen_mbx_count; 3032 3033 uint32_t login_retry_count; 3034 /* SNS command interfaces. */ 3035 ms_iocb_entry_t *ms_iocb; 3036 dma_addr_t ms_iocb_dma; 3037 struct ct_sns_pkt *ct_sns; 3038 dma_addr_t ct_sns_dma; 3039 /* SNS command interfaces for 2200. */ 3040 struct sns_cmd_pkt *sns_cmd; 3041 dma_addr_t sns_cmd_dma; 3042 3043 #define SFP_DEV_SIZE 256 3044 #define SFP_BLOCK_SIZE 64 3045 void *sfp_data; 3046 dma_addr_t sfp_data_dma; 3047 3048 #define XGMAC_DATA_SIZE 4096 3049 void *xgmac_data; 3050 dma_addr_t xgmac_data_dma; 3051 3052 #define DCBX_TLV_DATA_SIZE 4096 3053 void *dcbx_tlv; 3054 dma_addr_t dcbx_tlv_dma; 3055 3056 struct task_struct *dpc_thread; 3057 uint8_t dpc_active; /* DPC routine is active */ 3058 3059 dma_addr_t gid_list_dma; 3060 struct gid_list_info *gid_list; 3061 int gid_list_info_size; 3062 3063 /* Small DMA pool allocations -- maximum 256 bytes in length. */ 3064 #define DMA_POOL_SIZE 256 3065 struct dma_pool *s_dma_pool; 3066 3067 dma_addr_t init_cb_dma; 3068 init_cb_t *init_cb; 3069 int init_cb_size; 3070 dma_addr_t ex_init_cb_dma; 3071 struct ex_init_cb_81xx *ex_init_cb; 3072 3073 void *async_pd; 3074 dma_addr_t async_pd_dma; 3075 3076 void *swl; 3077 3078 /* These are used by mailbox operations. */ 3079 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; 3080 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT]; 3081 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00]; 3082 3083 mbx_cmd_t *mcp; 3084 struct mbx_cmd_32 *mcp32; 3085 3086 unsigned long mbx_cmd_flags; 3087 #define MBX_INTERRUPT 1 3088 #define MBX_INTR_WAIT 2 3089 #define MBX_UPDATE_FLASH_ACTIVE 3 3090 3091 struct mutex vport_lock; /* Virtual port synchronization */ 3092 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */ 3093 struct completion mbx_cmd_comp; /* Serialize mbx access */ 3094 struct completion mbx_intr_comp; /* Used for completion notification */ 3095 struct completion dcbx_comp; /* For set port config notification */ 3096 struct completion lb_portup_comp; /* Used to wait for link up during 3097 * loopback */ 3098 #define DCBX_COMP_TIMEOUT 20 3099 #define LB_PORTUP_COMP_TIMEOUT 10 3100 3101 int notify_dcbx_comp; 3102 int notify_lb_portup_comp; 3103 struct mutex selflogin_lock; 3104 3105 /* Basic firmware related information. */ 3106 uint16_t fw_major_version; 3107 uint16_t fw_minor_version; 3108 uint16_t fw_subminor_version; 3109 uint16_t fw_attributes; 3110 uint16_t fw_attributes_h; 3111 uint16_t fw_attributes_ext[2]; 3112 uint32_t fw_memory_size; 3113 uint32_t fw_transfer_size; 3114 uint32_t fw_srisc_address; 3115 #define RISC_START_ADDRESS_2100 0x1000 3116 #define RISC_START_ADDRESS_2300 0x800 3117 #define RISC_START_ADDRESS_2400 0x100000 3118 uint16_t fw_xcb_count; 3119 uint16_t fw_iocb_count; 3120 3121 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */ 3122 uint8_t fw_seriallink_options[4]; 3123 uint16_t fw_seriallink_options24[4]; 3124 3125 uint8_t mpi_version[3]; 3126 uint32_t mpi_capabilities; 3127 uint8_t phy_version[3]; 3128 3129 /* Firmware dump information. */ 3130 struct qla2xxx_fw_dump *fw_dump; 3131 uint32_t fw_dump_len; 3132 int fw_dumped; 3133 int fw_dump_reading; 3134 dma_addr_t eft_dma; 3135 void *eft; 3136 /* Current size of mctp dump is 0x086064 bytes */ 3137 #define MCTP_DUMP_SIZE 0x086064 3138 dma_addr_t mctp_dump_dma; 3139 void *mctp_dump; 3140 int mctp_dumped; 3141 int mctp_dump_reading; 3142 uint32_t chain_offset; 3143 struct dentry *dfs_dir; 3144 struct dentry *dfs_fce; 3145 dma_addr_t fce_dma; 3146 void *fce; 3147 uint32_t fce_bufs; 3148 uint16_t fce_mb[8]; 3149 uint64_t fce_wr, fce_rd; 3150 struct mutex fce_mutex; 3151 3152 uint32_t pci_attr; 3153 uint16_t chip_revision; 3154 3155 uint16_t product_id[4]; 3156 3157 uint8_t model_number[16+1]; 3158 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" 3159 char model_desc[80]; 3160 uint8_t adapter_id[16+1]; 3161 3162 /* Option ROM information. */ 3163 char *optrom_buffer; 3164 uint32_t optrom_size; 3165 int optrom_state; 3166 #define QLA_SWAITING 0 3167 #define QLA_SREADING 1 3168 #define QLA_SWRITING 2 3169 uint32_t optrom_region_start; 3170 uint32_t optrom_region_size; 3171 3172 /* PCI expansion ROM image information. */ 3173 #define ROM_CODE_TYPE_BIOS 0 3174 #define ROM_CODE_TYPE_FCODE 1 3175 #define ROM_CODE_TYPE_EFI 3 3176 uint8_t bios_revision[2]; 3177 uint8_t efi_revision[2]; 3178 uint8_t fcode_revision[16]; 3179 uint32_t fw_revision[4]; 3180 3181 uint32_t gold_fw_version[4]; 3182 3183 /* Offsets for flash/nvram access (set to ~0 if not used). */ 3184 uint32_t flash_conf_off; 3185 uint32_t flash_data_off; 3186 uint32_t nvram_conf_off; 3187 uint32_t nvram_data_off; 3188 3189 uint32_t fdt_wrt_disable; 3190 uint32_t fdt_erase_cmd; 3191 uint32_t fdt_block_size; 3192 uint32_t fdt_unprotect_sec_cmd; 3193 uint32_t fdt_protect_sec_cmd; 3194 3195 uint32_t flt_region_flt; 3196 uint32_t flt_region_fdt; 3197 uint32_t flt_region_boot; 3198 uint32_t flt_region_fw; 3199 uint32_t flt_region_vpd_nvram; 3200 uint32_t flt_region_vpd; 3201 uint32_t flt_region_nvram; 3202 uint32_t flt_region_npiv_conf; 3203 uint32_t flt_region_gold_fw; 3204 uint32_t flt_region_fcp_prio; 3205 uint32_t flt_region_bootload; 3206 3207 /* Needed for BEACON */ 3208 uint16_t beacon_blink_led; 3209 uint8_t beacon_color_state; 3210 #define QLA_LED_GRN_ON 0x01 3211 #define QLA_LED_YLW_ON 0x02 3212 #define QLA_LED_ABR_ON 0x04 3213 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */ 3214 /* ISP2322: red, green, amber. */ 3215 uint16_t zio_mode; 3216 uint16_t zio_timer; 3217 3218 struct qla_msix_entry *msix_entries; 3219 3220 struct list_head vp_list; /* list of VP */ 3221 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) / 3222 sizeof(unsigned long)]; 3223 uint16_t num_vhosts; /* number of vports created */ 3224 uint16_t num_vsans; /* number of vsan created */ 3225 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */ 3226 int cur_vport_count; 3227 3228 struct qla_chip_state_84xx *cs84xx; 3229 struct qla_statistics qla_stats; 3230 struct isp_operations *isp_ops; 3231 struct workqueue_struct *wq; 3232 struct qlfc_fw fw_buf; 3233 3234 /* FCP_CMND priority support */ 3235 struct qla_fcp_prio_cfg *fcp_prio_cfg; 3236 3237 struct dma_pool *dl_dma_pool; 3238 #define DSD_LIST_DMA_POOL_SIZE 512 3239 3240 struct dma_pool *fcp_cmnd_dma_pool; 3241 mempool_t *ctx_mempool; 3242 #define FCP_CMND_DMA_POOL_SIZE 512 3243 3244 unsigned long nx_pcibase; /* Base I/O address */ 3245 uint8_t *nxdb_rd_ptr; /* Doorbell read pointer */ 3246 unsigned long nxdb_wr_ptr; /* Door bell write pointer */ 3247 3248 uint32_t crb_win; 3249 uint32_t curr_window; 3250 uint32_t ddr_mn_window; 3251 unsigned long mn_win_crb; 3252 unsigned long ms_win_crb; 3253 int qdr_sn_window; 3254 uint32_t fcoe_dev_init_timeout; 3255 uint32_t fcoe_reset_timeout; 3256 rwlock_t hw_lock; 3257 uint16_t portnum; /* port number */ 3258 int link_width; 3259 struct fw_blob *hablob; 3260 struct qla82xx_legacy_intr_set nx_legacy_intr; 3261 3262 uint16_t gbl_dsd_inuse; 3263 uint16_t gbl_dsd_avail; 3264 struct list_head gbl_dsd_list; 3265 #define NUM_DSD_CHAIN 4096 3266 3267 uint8_t fw_type; 3268 __le32 file_prd_off; /* File firmware product offset */ 3269 3270 uint32_t md_template_size; 3271 void *md_tmplt_hdr; 3272 dma_addr_t md_tmplt_hdr_dma; 3273 void *md_dump; 3274 uint32_t md_dump_size; 3275 3276 void *loop_id_map; 3277 3278 /* QLA83XX IDC specific fields */ 3279 uint32_t idc_audit_ts; 3280 3281 /* DPC low-priority workqueue */ 3282 struct workqueue_struct *dpc_lp_wq; 3283 struct work_struct idc_aen; 3284 /* DPC high-priority workqueue */ 3285 struct workqueue_struct *dpc_hp_wq; 3286 struct work_struct nic_core_reset; 3287 struct work_struct idc_state_handler; 3288 struct work_struct nic_core_unrecoverable; 3289 3290 #define HOST_QUEUE_RAMPDOWN_INTERVAL (60 * HZ) 3291 #define HOST_QUEUE_RAMPUP_INTERVAL (30 * HZ) 3292 unsigned long host_last_rampdown_time; 3293 unsigned long host_last_rampup_time; 3294 int cfg_lun_q_depth; 3295 3296 struct mr_data_fx00 mr; 3297 3298 struct qlt_hw_data tgt; 3299 uint16_t thermal_support; 3300 #define THERMAL_SUPPORT_I2C BIT_0 3301 #define THERMAL_SUPPORT_ISP BIT_1 3302 }; 3303 3304 /* 3305 * Qlogic scsi host structure 3306 */ 3307 typedef struct scsi_qla_host { 3308 struct list_head list; 3309 struct list_head vp_fcports; /* list of fcports */ 3310 struct list_head work_list; 3311 spinlock_t work_lock; 3312 3313 /* Commonly used flags and state information. */ 3314 struct Scsi_Host *host; 3315 unsigned long host_no; 3316 uint8_t host_str[16]; 3317 3318 volatile struct { 3319 uint32_t init_done :1; 3320 uint32_t online :1; 3321 uint32_t reset_active :1; 3322 3323 uint32_t management_server_logged_in :1; 3324 uint32_t process_response_queue :1; 3325 uint32_t difdix_supported:1; 3326 uint32_t delete_progress:1; 3327 3328 uint32_t fw_tgt_reported:1; 3329 } flags; 3330 3331 atomic_t loop_state; 3332 #define LOOP_TIMEOUT 1 3333 #define LOOP_DOWN 2 3334 #define LOOP_UP 3 3335 #define LOOP_UPDATE 4 3336 #define LOOP_READY 5 3337 #define LOOP_DEAD 6 3338 3339 unsigned long dpc_flags; 3340 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */ 3341 #define RESET_ACTIVE 1 3342 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */ 3343 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */ 3344 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */ 3345 #define LOOP_RESYNC_ACTIVE 5 3346 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */ 3347 #define RSCN_UPDATE 7 /* Perform an RSCN update. */ 3348 #define RELOGIN_NEEDED 8 3349 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */ 3350 #define ISP_ABORT_RETRY 10 /* ISP aborted. */ 3351 #define BEACON_BLINK_NEEDED 11 3352 #define REGISTER_FDMI_NEEDED 12 3353 #define FCPORT_UPDATE_NEEDED 13 3354 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */ 3355 #define UNLOADING 15 3356 #define NPIV_CONFIG_NEEDED 16 3357 #define ISP_UNRECOVERABLE 17 3358 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */ 3359 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */ 3360 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */ 3361 #define SCR_PENDING 21 /* SCR in target mode */ 3362 #define HOST_RAMP_DOWN_QUEUE_DEPTH 22 3363 #define HOST_RAMP_UP_QUEUE_DEPTH 23 3364 #define PORT_UPDATE_NEEDED 24 3365 #define FX00_RESET_RECOVERY 25 3366 #define FX00_TARGET_SCAN 26 3367 3368 uint32_t device_flags; 3369 #define SWITCH_FOUND BIT_0 3370 #define DFLG_NO_CABLE BIT_1 3371 #define DFLG_DEV_FAILED BIT_5 3372 3373 /* ISP configuration data. */ 3374 uint16_t loop_id; /* Host adapter loop id */ 3375 uint16_t self_login_loop_id; /* host adapter loop id 3376 * get it on self login 3377 */ 3378 fc_port_t bidir_fcport; /* fcport used for bidir cmnds 3379 * no need of allocating it for 3380 * each command 3381 */ 3382 3383 port_id_t d_id; /* Host adapter port id */ 3384 uint8_t marker_needed; 3385 uint16_t mgmt_svr_loop_id; 3386 3387 3388 3389 /* Timeout timers. */ 3390 uint8_t loop_down_abort_time; /* port down timer */ 3391 atomic_t loop_down_timer; /* loop down timer */ 3392 uint8_t link_down_timeout; /* link down timeout */ 3393 3394 uint32_t timer_active; 3395 struct timer_list timer; 3396 3397 uint8_t node_name[WWN_SIZE]; 3398 uint8_t port_name[WWN_SIZE]; 3399 uint8_t fabric_node_name[WWN_SIZE]; 3400 3401 uint16_t fcoe_vlan_id; 3402 uint16_t fcoe_fcf_idx; 3403 uint8_t fcoe_vn_port_mac[6]; 3404 3405 uint32_t vp_abort_cnt; 3406 3407 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */ 3408 uint16_t vp_idx; /* vport ID */ 3409 3410 unsigned long vp_flags; 3411 #define VP_IDX_ACQUIRED 0 /* bit no 0 */ 3412 #define VP_CREATE_NEEDED 1 3413 #define VP_BIND_NEEDED 2 3414 #define VP_DELETE_NEEDED 3 3415 #define VP_SCR_NEEDED 4 /* State Change Request registration */ 3416 atomic_t vp_state; 3417 #define VP_OFFLINE 0 3418 #define VP_ACTIVE 1 3419 #define VP_FAILED 2 3420 // #define VP_DISABLE 3 3421 uint16_t vp_err_state; 3422 uint16_t vp_prev_err_state; 3423 #define VP_ERR_UNKWN 0 3424 #define VP_ERR_PORTDWN 1 3425 #define VP_ERR_FAB_UNSUPPORTED 2 3426 #define VP_ERR_FAB_NORESOURCES 3 3427 #define VP_ERR_FAB_LOGOUT 4 3428 #define VP_ERR_ADAP_NORESOURCES 5 3429 struct qla_hw_data *hw; 3430 struct req_que *req; 3431 int fw_heartbeat_counter; 3432 int seconds_since_last_heartbeat; 3433 struct fc_host_statistics fc_host_stat; 3434 struct qla_statistics qla_stats; 3435 struct bidi_statistics bidi_stats; 3436 3437 atomic_t vref_count; 3438 } scsi_qla_host_t; 3439 3440 #define SET_VP_IDX 1 3441 #define SET_AL_PA 2 3442 #define RESET_VP_IDX 3 3443 #define RESET_AL_PA 4 3444 struct qla_tgt_vp_map { 3445 uint8_t idx; 3446 scsi_qla_host_t *vha; 3447 }; 3448 3449 /* 3450 * Macros to help code, maintain, etc. 3451 */ 3452 #define LOOP_TRANSITION(ha) \ 3453 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 3454 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \ 3455 atomic_read(&ha->loop_state) == LOOP_DOWN) 3456 3457 #define STATE_TRANSITION(ha) \ 3458 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 3459 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags)) 3460 3461 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \ 3462 atomic_inc(&__vha->vref_count); \ 3463 mb(); \ 3464 if (__vha->flags.delete_progress) { \ 3465 atomic_dec(&__vha->vref_count); \ 3466 __bail = 1; \ 3467 } else { \ 3468 __bail = 0; \ 3469 } \ 3470 } while (0) 3471 3472 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \ 3473 atomic_dec(&__vha->vref_count); \ 3474 } while (0) 3475 3476 /* 3477 * qla2x00 local function return status codes 3478 */ 3479 #define MBS_MASK 0x3fff 3480 3481 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK) 3482 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK) 3483 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK) 3484 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK) 3485 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK) 3486 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK) 3487 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK) 3488 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK) 3489 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK) 3490 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK) 3491 3492 #define QLA_FUNCTION_TIMEOUT 0x100 3493 #define QLA_FUNCTION_PARAMETER_ERROR 0x101 3494 #define QLA_FUNCTION_FAILED 0x102 3495 #define QLA_MEMORY_ALLOC_FAILED 0x103 3496 #define QLA_LOCK_TIMEOUT 0x104 3497 #define QLA_ABORTED 0x105 3498 #define QLA_SUSPENDED 0x106 3499 #define QLA_BUSY 0x107 3500 #define QLA_ALREADY_REGISTERED 0x109 3501 3502 #define NVRAM_DELAY() udelay(10) 3503 3504 /* 3505 * Flash support definitions 3506 */ 3507 #define OPTROM_SIZE_2300 0x20000 3508 #define OPTROM_SIZE_2322 0x100000 3509 #define OPTROM_SIZE_24XX 0x100000 3510 #define OPTROM_SIZE_25XX 0x200000 3511 #define OPTROM_SIZE_81XX 0x400000 3512 #define OPTROM_SIZE_82XX 0x800000 3513 #define OPTROM_SIZE_83XX 0x1000000 3514 3515 #define OPTROM_BURST_SIZE 0x1000 3516 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 3517 3518 #define QLA_DSDS_PER_IOCB 37 3519 3520 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr) 3521 3522 #define QLA_SG_ALL 1024 3523 3524 enum nexus_wait_type { 3525 WAIT_HOST = 0, 3526 WAIT_TARGET, 3527 WAIT_LUN, 3528 }; 3529 3530 #include "qla_gbl.h" 3531 #include "qla_dbg.h" 3532 #include "qla_inline.h" 3533 #endif 3534