1 /* arch/arm/mach-s3c2410/include/mach/map.h 2 * 3 * Copyright (c) 2003 Simtec Electronics 4 * Ben Dooks <ben@simtec.co.uk> 5 * 6 * S3C2410 - Memory map definitions 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #ifndef __ASM_ARCH_MAP_H 14 #define __ASM_ARCH_MAP_H 15 16 #include <plat/map-base.h> 17 18 /* 19 * S3C2410 UART offset is 0x4000 but the other SoCs are 0x400. 20 * So need to define it, and here is to avoid redefinition warning. 21 */ 22 #define S3C_UART_OFFSET (0x4000) 23 24 #include <plat/map-s3c.h> 25 26 /* 27 * interrupt controller is the first thing we put in, to make 28 * the assembly code for the irq detection easier 29 */ 30 #define S3C2410_PA_IRQ (0x4A000000) 31 #define S3C24XX_SZ_IRQ SZ_1M 32 33 /* memory controller registers */ 34 #define S3C2410_PA_MEMCTRL (0x48000000) 35 #define S3C24XX_SZ_MEMCTRL SZ_1M 36 37 /* UARTs */ 38 #define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET))) 39 40 /* Timers */ 41 #define S3C2410_PA_TIMER (0x51000000) 42 #define S3C24XX_SZ_TIMER SZ_1M 43 44 /* Clock and Power management */ 45 #define S3C24XX_SZ_CLKPWR SZ_1M 46 47 /* USB Device port */ 48 #define S3C2410_PA_USBDEV (0x52000000) 49 #define S3C24XX_SZ_USBDEV SZ_1M 50 51 /* Watchdog */ 52 #define S3C2410_PA_WATCHDOG (0x53000000) 53 #define S3C24XX_SZ_WATCHDOG SZ_1M 54 55 /* Standard size definitions for peripheral blocks. */ 56 57 #define S3C24XX_SZ_UART SZ_1M 58 #define S3C24XX_SZ_IIS SZ_1M 59 #define S3C24XX_SZ_ADC SZ_1M 60 #define S3C24XX_SZ_SPI SZ_1M 61 #define S3C24XX_SZ_SDI SZ_1M 62 #define S3C24XX_SZ_NAND SZ_1M 63 #define S3C24XX_SZ_GPIO SZ_1M 64 65 /* USB host controller */ 66 #define S3C2410_PA_USBHOST (0x49000000) 67 68 /* S3C2416/S3C2443/S3C2450 High-Speed USB Gadget */ 69 #define S3C2416_PA_HSUDC (0x49800000) 70 #define S3C2416_SZ_HSUDC (SZ_4K) 71 72 /* DMA controller */ 73 #define S3C2410_PA_DMA (0x4B000000) 74 #define S3C24XX_SZ_DMA SZ_1M 75 76 /* Clock and Power management */ 77 #define S3C2410_PA_CLKPWR (0x4C000000) 78 79 /* LCD controller */ 80 #define S3C2410_PA_LCD (0x4D000000) 81 #define S3C24XX_SZ_LCD SZ_1M 82 83 /* NAND flash controller */ 84 #define S3C2410_PA_NAND (0x4E000000) 85 86 /* IIC hardware controller */ 87 #define S3C2410_PA_IIC (0x54000000) 88 89 /* IIS controller */ 90 #define S3C2410_PA_IIS (0x55000000) 91 92 /* RTC */ 93 #define S3C2410_PA_RTC (0x57000000) 94 #define S3C24XX_SZ_RTC SZ_1M 95 96 /* ADC */ 97 #define S3C2410_PA_ADC (0x58000000) 98 99 /* SPI */ 100 #define S3C2410_PA_SPI (0x59000000) 101 #define S3C2443_PA_SPI0 (0x52000000) 102 #define S3C2443_PA_SPI1 S3C2410_PA_SPI 103 104 /* SDI */ 105 #define S3C2410_PA_SDI (0x5A000000) 106 107 /* CAMIF */ 108 #define S3C2440_PA_CAMIF (0x4F000000) 109 #define S3C2440_SZ_CAMIF SZ_1M 110 111 /* AC97 */ 112 113 #define S3C2440_PA_AC97 (0x5B000000) 114 #define S3C2440_SZ_AC97 SZ_1M 115 116 /* S3C2443/S3C2416 High-speed SD/MMC */ 117 #define S3C2443_PA_HSMMC (0x4A800000) 118 #define S3C2416_PA_HSMMC0 (0x4AC00000) 119 120 #define S3C2443_PA_FB (0x4C800000) 121 122 /* S3C2412 memory and IO controls */ 123 #define S3C2412_PA_SSMC (0x4F000000) 124 125 #define S3C2412_PA_EBI (0x48800000) 126 127 /* physical addresses of all the chip-select areas */ 128 129 #define S3C2410_CS0 (0x00000000) 130 #define S3C2410_CS1 (0x08000000) 131 #define S3C2410_CS2 (0x10000000) 132 #define S3C2410_CS3 (0x18000000) 133 #define S3C2410_CS4 (0x20000000) 134 #define S3C2410_CS5 (0x28000000) 135 #define S3C2410_CS6 (0x30000000) 136 #define S3C2410_CS7 (0x38000000) 137 138 #define S3C2410_SDRAM_PA (S3C2410_CS6) 139 140 /* Use a single interface for common resources between S3C24XX cpus */ 141 142 #define S3C24XX_PA_IRQ S3C2410_PA_IRQ 143 #define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL 144 #define S3C24XX_PA_DMA S3C2410_PA_DMA 145 #define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR 146 #define S3C24XX_PA_LCD S3C2410_PA_LCD 147 #define S3C24XX_PA_TIMER S3C2410_PA_TIMER 148 #define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV 149 #define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG 150 #define S3C24XX_PA_IIS S3C2410_PA_IIS 151 #define S3C24XX_PA_RTC S3C2410_PA_RTC 152 #define S3C24XX_PA_ADC S3C2410_PA_ADC 153 #define S3C24XX_PA_SPI S3C2410_PA_SPI 154 #define S3C24XX_PA_SPI1 (S3C2410_PA_SPI + S3C2410_SPI1) 155 #define S3C24XX_PA_SDI S3C2410_PA_SDI 156 #define S3C24XX_PA_NAND S3C2410_PA_NAND 157 158 #define S3C_PA_FB S3C2443_PA_FB 159 #define S3C_PA_IIC S3C2410_PA_IIC 160 #define S3C_PA_UART S3C24XX_PA_UART 161 #define S3C_PA_USBHOST S3C2410_PA_USBHOST 162 #define S3C_PA_HSMMC0 S3C2416_PA_HSMMC0 163 #define S3C_PA_HSMMC1 S3C2443_PA_HSMMC 164 #define S3C_PA_WDT S3C2410_PA_WATCHDOG 165 #define S3C_PA_NAND S3C24XX_PA_NAND 166 167 #define S3C_PA_SPI0 S3C2443_PA_SPI0 168 #define S3C_PA_SPI1 S3C2443_PA_SPI1 169 170 #endif /* __ASM_ARCH_MAP_H */ 171