1 /* 2 * include/asm-parisc/cache.h 3 */ 4 5 #ifndef __ARCH_PARISC_CACHE_H 6 #define __ARCH_PARISC_CACHE_H 7 8 9 /* 10 * PA 2.0 processors have 64-byte cachelines; PA 1.1 processors have 11 * 32-byte cachelines. The default configuration is not for SMP anyway, 12 * so if you're building for SMP, you should select the appropriate 13 * processor type. There is a potential livelock danger when running 14 * a machine with this value set too small, but it's more probable you'll 15 * just ruin performance. 16 */ 17 #ifdef CONFIG_PA20 18 #define L1_CACHE_BYTES 64 19 #define L1_CACHE_SHIFT 6 20 #else 21 #define L1_CACHE_BYTES 32 22 #define L1_CACHE_SHIFT 5 23 #endif 24 25 #ifndef __ASSEMBLY__ 26 27 #define SMP_CACHE_BYTES L1_CACHE_BYTES 28 29 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES 30 31 #define __read_mostly __attribute__((__section__(".data..read_mostly"))) 32 33 void parisc_cache_init(void); /* initializes cache-flushing */ 34 void disable_sr_hashing_asm(int); /* low level support for above */ 35 void disable_sr_hashing(void); /* turns off space register hashing */ 36 void free_sid(unsigned long); 37 unsigned long alloc_sid(void); 38 39 struct seq_file; 40 extern void show_cache_info(struct seq_file *m); 41 42 extern int split_tlb; 43 extern int dcache_stride; 44 extern int icache_stride; 45 extern struct pdc_cache_info cache_info; 46 void parisc_setup_cache_timing(void); 47 48 #define pdtlb(addr) asm volatile("pdtlb 0(%%sr1,%0)" : : "r" (addr)); 49 #define pitlb(addr) asm volatile("pitlb 0(%%sr1,%0)" : : "r" (addr)); 50 #define pdtlb_kernel(addr) asm volatile("pdtlb 0(%0)" : : "r" (addr)); 51 52 #endif /* ! __ASSEMBLY__ */ 53 54 /* Classes of processor wrt: disabling space register hashing */ 55 56 #define SRHASH_PCXST 0 /* pcxs, pcxt, pcxt_ */ 57 #define SRHASH_PCXL 1 /* pcxl */ 58 #define SRHASH_PA20 2 /* pcxu, pcxu_, pcxw, pcxw_ */ 59 60 #endif 61