1 /*
2 * OMAP3-specific clock framework functions
3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation
6 *
7 * Paul Walmsley
8 * Jouni Högander
9 *
10 * Parts of this code are based on code written by
11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17 #undef DEBUG
18
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/clk.h>
22 #include <linux/io.h>
23
24 #include "soc.h"
25 #include "clock.h"
26 #include "clock3xxx.h"
27 #include "prm2xxx_3xxx.h"
28 #include "prm-regbits-34xx.h"
29 #include "cm2xxx_3xxx.h"
30 #include "cm-regbits-34xx.h"
31
32 /*
33 * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
34 * that are sourced by DPLL5, and both of these require this clock
35 * to be at 120 MHz for proper operation.
36 */
37 #define DPLL5_FREQ_FOR_USBHOST 120000000
38
39 /* needed by omap3_core_dpll_m2_set_rate() */
40 struct clk *sdrc_ick_p, *arm_fck_p;
omap3_dpll4_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)41 int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate,
42 unsigned long parent_rate)
43 {
44 /*
45 * According to the 12-5 CDP code from TI, "Limitation 2.5"
46 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
47 * on DPLL4.
48 */
49 if (omap_rev() == OMAP3430_REV_ES1_0) {
50 pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
51 return -EINVAL;
52 }
53
54 return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
55 }
56
omap3_clk_lock_dpll5(void)57 void __init omap3_clk_lock_dpll5(void)
58 {
59 struct clk *dpll5_clk;
60 struct clk *dpll5_m2_clk;
61
62 dpll5_clk = clk_get(NULL, "dpll5_ck");
63 clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
64 clk_prepare_enable(dpll5_clk);
65
66 /* Program dpll5_m2_clk divider for no division */
67 dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
68 clk_prepare_enable(dpll5_m2_clk);
69 clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
70
71 clk_disable_unprepare(dpll5_m2_clk);
72 clk_disable_unprepare(dpll5_clk);
73 return;
74 }
75
76 /* Common clock code */
77
78 /*
79 * Switch the MPU rate if specified on cmdline. We cannot do this
80 * early until cmdline is parsed. XXX This should be removed from the
81 * clock code and handled by the OPP layer code in the near future.
82 */
omap3xxx_clk_arch_init(void)83 static int __init omap3xxx_clk_arch_init(void)
84 {
85 int ret;
86
87 if (!cpu_is_omap34xx())
88 return 0;
89
90 ret = omap2_clk_switch_mpurate_at_boot("dpll1_ck");
91 if (!ret)
92 omap2_clk_print_new_rates("osc_sys_ck", "core_ck", "arm_fck");
93
94 return ret;
95 }
96
97 omap_arch_initcall(omap3xxx_clk_arch_init);
98
99
100