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1 /*
2  * Copyright (c) 2008-2011 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #include <linux/dma-mapping.h>
18 #include "ath9k.h"
19 #include "ar9003_mac.h"
20 
21 #define BITS_PER_BYTE           8
22 #define OFDM_PLCP_BITS          22
23 #define HT_RC_2_STREAMS(_rc)    ((((_rc) & 0x78) >> 3) + 1)
24 #define L_STF                   8
25 #define L_LTF                   8
26 #define L_SIG                   4
27 #define HT_SIG                  8
28 #define HT_STF                  4
29 #define HT_LTF(_ns)             (4 * (_ns))
30 #define SYMBOL_TIME(_ns)        ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5)  /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t)         ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t)  (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
36 
37 
38 static u16 bits_per_symbol[][2] = {
39 	/* 20MHz 40MHz */
40 	{    26,   54 },     /*  0: BPSK */
41 	{    52,  108 },     /*  1: QPSK 1/2 */
42 	{    78,  162 },     /*  2: QPSK 3/4 */
43 	{   104,  216 },     /*  3: 16-QAM 1/2 */
44 	{   156,  324 },     /*  4: 16-QAM 3/4 */
45 	{   208,  432 },     /*  5: 64-QAM 2/3 */
46 	{   234,  486 },     /*  6: 64-QAM 3/4 */
47 	{   260,  540 },     /*  7: 64-QAM 5/6 */
48 };
49 
50 #define IS_HT_RATE(_rate)     ((_rate) & 0x80)
51 
52 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
53 			       struct ath_atx_tid *tid, struct sk_buff *skb);
54 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
55 			    int tx_flags, struct ath_txq *txq);
56 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
57 				struct ath_txq *txq, struct list_head *bf_q,
58 				struct ath_tx_status *ts, int txok);
59 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
60 			     struct list_head *head, bool internal);
61 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
62 			     struct ath_tx_status *ts, int nframes, int nbad,
63 			     int txok);
64 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
65 			      int seqno);
66 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
67 					   struct ath_txq *txq,
68 					   struct ath_atx_tid *tid,
69 					   struct sk_buff *skb);
70 
71 enum {
72 	MCS_HT20,
73 	MCS_HT20_SGI,
74 	MCS_HT40,
75 	MCS_HT40_SGI,
76 };
77 
78 /*********************/
79 /* Aggregation logic */
80 /*********************/
81 
ath_txq_lock(struct ath_softc * sc,struct ath_txq * txq)82 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
83 	__acquires(&txq->axq_lock)
84 {
85 	spin_lock_bh(&txq->axq_lock);
86 }
87 
ath_txq_unlock(struct ath_softc * sc,struct ath_txq * txq)88 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
89 	__releases(&txq->axq_lock)
90 {
91 	spin_unlock_bh(&txq->axq_lock);
92 }
93 
ath_txq_unlock_complete(struct ath_softc * sc,struct ath_txq * txq)94 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
95 	__releases(&txq->axq_lock)
96 {
97 	struct sk_buff_head q;
98 	struct sk_buff *skb;
99 
100 	__skb_queue_head_init(&q);
101 	skb_queue_splice_init(&txq->complete_q, &q);
102 	spin_unlock_bh(&txq->axq_lock);
103 
104 	while ((skb = __skb_dequeue(&q)))
105 		ieee80211_tx_status(sc->hw, skb);
106 }
107 
ath_tx_queue_tid(struct ath_txq * txq,struct ath_atx_tid * tid)108 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
109 {
110 	struct ath_atx_ac *ac = tid->ac;
111 
112 	if (tid->paused)
113 		return;
114 
115 	if (tid->sched)
116 		return;
117 
118 	tid->sched = true;
119 	list_add_tail(&tid->list, &ac->tid_q);
120 
121 	if (ac->sched)
122 		return;
123 
124 	ac->sched = true;
125 	list_add_tail(&ac->list, &txq->axq_acq);
126 }
127 
get_frame_info(struct sk_buff * skb)128 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
129 {
130 	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
131 	BUILD_BUG_ON(sizeof(struct ath_frame_info) >
132 		     sizeof(tx_info->rate_driver_data));
133 	return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
134 }
135 
ath_send_bar(struct ath_atx_tid * tid,u16 seqno)136 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
137 {
138 	ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
139 			   seqno << IEEE80211_SEQ_SEQ_SHIFT);
140 }
141 
ath_set_rates(struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct ath_buf * bf)142 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
143 			  struct ath_buf *bf)
144 {
145 	ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
146 			       ARRAY_SIZE(bf->rates));
147 }
148 
ath_tx_flush_tid(struct ath_softc * sc,struct ath_atx_tid * tid)149 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
150 {
151 	struct ath_txq *txq = tid->ac->txq;
152 	struct sk_buff *skb;
153 	struct ath_buf *bf;
154 	struct list_head bf_head;
155 	struct ath_tx_status ts;
156 	struct ath_frame_info *fi;
157 	bool sendbar = false;
158 
159 	INIT_LIST_HEAD(&bf_head);
160 
161 	memset(&ts, 0, sizeof(ts));
162 
163 	while ((skb = __skb_dequeue(&tid->buf_q))) {
164 		fi = get_frame_info(skb);
165 		bf = fi->bf;
166 
167 		if (!bf) {
168 			bf = ath_tx_setup_buffer(sc, txq, tid, skb);
169 			if (!bf) {
170 				ieee80211_free_txskb(sc->hw, skb);
171 				continue;
172 			}
173 		}
174 
175 		if (fi->retries) {
176 			list_add_tail(&bf->list, &bf_head);
177 			ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
178 			ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
179 			sendbar = true;
180 		} else {
181 			ath_set_rates(tid->an->vif, tid->an->sta, bf);
182 			ath_tx_send_normal(sc, txq, NULL, skb);
183 		}
184 	}
185 
186 	if (sendbar) {
187 		ath_txq_unlock(sc, txq);
188 		ath_send_bar(tid, tid->seq_start);
189 		ath_txq_lock(sc, txq);
190 	}
191 }
192 
ath_tx_update_baw(struct ath_softc * sc,struct ath_atx_tid * tid,int seqno)193 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
194 			      int seqno)
195 {
196 	int index, cindex;
197 
198 	index  = ATH_BA_INDEX(tid->seq_start, seqno);
199 	cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
200 
201 	__clear_bit(cindex, tid->tx_buf);
202 
203 	while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
204 		INCR(tid->seq_start, IEEE80211_SEQ_MAX);
205 		INCR(tid->baw_head, ATH_TID_MAX_BUFS);
206 		if (tid->bar_index >= 0)
207 			tid->bar_index--;
208 	}
209 }
210 
ath_tx_addto_baw(struct ath_softc * sc,struct ath_atx_tid * tid,u16 seqno)211 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
212 			     u16 seqno)
213 {
214 	int index, cindex;
215 
216 	index  = ATH_BA_INDEX(tid->seq_start, seqno);
217 	cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
218 	__set_bit(cindex, tid->tx_buf);
219 
220 	if (index >= ((tid->baw_tail - tid->baw_head) &
221 		(ATH_TID_MAX_BUFS - 1))) {
222 		tid->baw_tail = cindex;
223 		INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
224 	}
225 }
226 
227 /*
228  * TODO: For frame(s) that are in the retry state, we will reuse the
229  * sequence number(s) without setting the retry bit. The
230  * alternative is to give up on these and BAR the receiver's window
231  * forward.
232  */
ath_tid_drain(struct ath_softc * sc,struct ath_txq * txq,struct ath_atx_tid * tid)233 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
234 			  struct ath_atx_tid *tid)
235 
236 {
237 	struct sk_buff *skb;
238 	struct ath_buf *bf;
239 	struct list_head bf_head;
240 	struct ath_tx_status ts;
241 	struct ath_frame_info *fi;
242 
243 	memset(&ts, 0, sizeof(ts));
244 	INIT_LIST_HEAD(&bf_head);
245 
246 	while ((skb = __skb_dequeue(&tid->buf_q))) {
247 		fi = get_frame_info(skb);
248 		bf = fi->bf;
249 
250 		if (!bf) {
251 			ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
252 			continue;
253 		}
254 
255 		list_add_tail(&bf->list, &bf_head);
256 
257 		ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
258 		ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
259 	}
260 
261 	tid->seq_next = tid->seq_start;
262 	tid->baw_tail = tid->baw_head;
263 	tid->bar_index = -1;
264 }
265 
ath_tx_set_retry(struct ath_softc * sc,struct ath_txq * txq,struct sk_buff * skb,int count)266 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
267 			     struct sk_buff *skb, int count)
268 {
269 	struct ath_frame_info *fi = get_frame_info(skb);
270 	struct ath_buf *bf = fi->bf;
271 	struct ieee80211_hdr *hdr;
272 	int prev = fi->retries;
273 
274 	TX_STAT_INC(txq->axq_qnum, a_retries);
275 	fi->retries += count;
276 
277 	if (prev > 0)
278 		return;
279 
280 	hdr = (struct ieee80211_hdr *)skb->data;
281 	hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
282 	dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
283 		sizeof(*hdr), DMA_TO_DEVICE);
284 }
285 
ath_tx_get_buffer(struct ath_softc * sc)286 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
287 {
288 	struct ath_buf *bf = NULL;
289 
290 	spin_lock_bh(&sc->tx.txbuflock);
291 
292 	if (unlikely(list_empty(&sc->tx.txbuf))) {
293 		spin_unlock_bh(&sc->tx.txbuflock);
294 		return NULL;
295 	}
296 
297 	bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
298 	list_del(&bf->list);
299 
300 	spin_unlock_bh(&sc->tx.txbuflock);
301 
302 	return bf;
303 }
304 
ath_tx_return_buffer(struct ath_softc * sc,struct ath_buf * bf)305 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
306 {
307 	spin_lock_bh(&sc->tx.txbuflock);
308 	list_add_tail(&bf->list, &sc->tx.txbuf);
309 	spin_unlock_bh(&sc->tx.txbuflock);
310 }
311 
ath_clone_txbuf(struct ath_softc * sc,struct ath_buf * bf)312 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
313 {
314 	struct ath_buf *tbf;
315 
316 	tbf = ath_tx_get_buffer(sc);
317 	if (WARN_ON(!tbf))
318 		return NULL;
319 
320 	ATH_TXBUF_RESET(tbf);
321 
322 	tbf->bf_mpdu = bf->bf_mpdu;
323 	tbf->bf_buf_addr = bf->bf_buf_addr;
324 	memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
325 	tbf->bf_state = bf->bf_state;
326 
327 	return tbf;
328 }
329 
ath_tx_count_frames(struct ath_softc * sc,struct ath_buf * bf,struct ath_tx_status * ts,int txok,int * nframes,int * nbad)330 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
331 			        struct ath_tx_status *ts, int txok,
332 			        int *nframes, int *nbad)
333 {
334 	struct ath_frame_info *fi;
335 	u16 seq_st = 0;
336 	u32 ba[WME_BA_BMP_SIZE >> 5];
337 	int ba_index;
338 	int isaggr = 0;
339 
340 	*nbad = 0;
341 	*nframes = 0;
342 
343 	isaggr = bf_isaggr(bf);
344 	if (isaggr) {
345 		seq_st = ts->ts_seqnum;
346 		memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
347 	}
348 
349 	while (bf) {
350 		fi = get_frame_info(bf->bf_mpdu);
351 		ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
352 
353 		(*nframes)++;
354 		if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
355 			(*nbad)++;
356 
357 		bf = bf->bf_next;
358 	}
359 }
360 
361 
ath_tx_complete_aggr(struct ath_softc * sc,struct ath_txq * txq,struct ath_buf * bf,struct list_head * bf_q,struct ath_tx_status * ts,int txok)362 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
363 				 struct ath_buf *bf, struct list_head *bf_q,
364 				 struct ath_tx_status *ts, int txok)
365 {
366 	struct ath_node *an = NULL;
367 	struct sk_buff *skb;
368 	struct ieee80211_sta *sta;
369 	struct ieee80211_hw *hw = sc->hw;
370 	struct ieee80211_hdr *hdr;
371 	struct ieee80211_tx_info *tx_info;
372 	struct ath_atx_tid *tid = NULL;
373 	struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
374 	struct list_head bf_head;
375 	struct sk_buff_head bf_pending;
376 	u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
377 	u32 ba[WME_BA_BMP_SIZE >> 5];
378 	int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
379 	bool rc_update = true, isba;
380 	struct ieee80211_tx_rate rates[4];
381 	struct ath_frame_info *fi;
382 	int nframes;
383 	u8 tidno;
384 	bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
385 	int i, retries;
386 	int bar_index = -1;
387 
388 	skb = bf->bf_mpdu;
389 	hdr = (struct ieee80211_hdr *)skb->data;
390 
391 	tx_info = IEEE80211_SKB_CB(skb);
392 
393 	memcpy(rates, bf->rates, sizeof(rates));
394 
395 	retries = ts->ts_longretry + 1;
396 	for (i = 0; i < ts->ts_rateindex; i++)
397 		retries += rates[i].count;
398 
399 	rcu_read_lock();
400 
401 	sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
402 	if (!sta) {
403 		rcu_read_unlock();
404 
405 		INIT_LIST_HEAD(&bf_head);
406 		while (bf) {
407 			bf_next = bf->bf_next;
408 
409 			if (!bf->bf_stale || bf_next != NULL)
410 				list_move_tail(&bf->list, &bf_head);
411 
412 			ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
413 
414 			bf = bf_next;
415 		}
416 		return;
417 	}
418 
419 	an = (struct ath_node *)sta->drv_priv;
420 	tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
421 	tid = ATH_AN_2_TID(an, tidno);
422 	seq_first = tid->seq_start;
423 	isba = ts->ts_flags & ATH9K_TX_BA;
424 
425 	/*
426 	 * The hardware occasionally sends a tx status for the wrong TID.
427 	 * In this case, the BA status cannot be considered valid and all
428 	 * subframes need to be retransmitted
429 	 *
430 	 * Only BlockAcks have a TID and therefore normal Acks cannot be
431 	 * checked
432 	 */
433 	if (isba && tidno != ts->tid)
434 		txok = false;
435 
436 	isaggr = bf_isaggr(bf);
437 	memset(ba, 0, WME_BA_BMP_SIZE >> 3);
438 
439 	if (isaggr && txok) {
440 		if (ts->ts_flags & ATH9K_TX_BA) {
441 			seq_st = ts->ts_seqnum;
442 			memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
443 		} else {
444 			/*
445 			 * AR5416 can become deaf/mute when BA
446 			 * issue happens. Chip needs to be reset.
447 			 * But AP code may have sychronization issues
448 			 * when perform internal reset in this routine.
449 			 * Only enable reset in STA mode for now.
450 			 */
451 			if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
452 				needreset = 1;
453 		}
454 	}
455 
456 	__skb_queue_head_init(&bf_pending);
457 
458 	ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
459 	while (bf) {
460 		u16 seqno = bf->bf_state.seqno;
461 
462 		txfail = txpending = sendbar = 0;
463 		bf_next = bf->bf_next;
464 
465 		skb = bf->bf_mpdu;
466 		tx_info = IEEE80211_SKB_CB(skb);
467 		fi = get_frame_info(skb);
468 
469 		if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
470 			/*
471 			 * Outside of the current BlockAck window,
472 			 * maybe part of a previous session
473 			 */
474 			txfail = 1;
475 		} else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
476 			/* transmit completion, subframe is
477 			 * acked by block ack */
478 			acked_cnt++;
479 		} else if (!isaggr && txok) {
480 			/* transmit completion */
481 			acked_cnt++;
482 		} else if (flush) {
483 			txpending = 1;
484 		} else if (fi->retries < ATH_MAX_SW_RETRIES) {
485 			if (txok || !an->sleeping)
486 				ath_tx_set_retry(sc, txq, bf->bf_mpdu,
487 						 retries);
488 
489 			txpending = 1;
490 		} else {
491 			txfail = 1;
492 			txfail_cnt++;
493 			bar_index = max_t(int, bar_index,
494 				ATH_BA_INDEX(seq_first, seqno));
495 		}
496 
497 		/*
498 		 * Make sure the last desc is reclaimed if it
499 		 * not a holding desc.
500 		 */
501 		INIT_LIST_HEAD(&bf_head);
502 		if (bf_next != NULL || !bf_last->bf_stale)
503 			list_move_tail(&bf->list, &bf_head);
504 
505 		if (!txpending) {
506 			/*
507 			 * complete the acked-ones/xretried ones; update
508 			 * block-ack window
509 			 */
510 			ath_tx_update_baw(sc, tid, seqno);
511 
512 			if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
513 				memcpy(tx_info->control.rates, rates, sizeof(rates));
514 				ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
515 				rc_update = false;
516 			}
517 
518 			ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
519 				!txfail);
520 		} else {
521 			/* retry the un-acked ones */
522 			if (bf->bf_next == NULL && bf_last->bf_stale) {
523 				struct ath_buf *tbf;
524 
525 				tbf = ath_clone_txbuf(sc, bf_last);
526 				/*
527 				 * Update tx baw and complete the
528 				 * frame with failed status if we
529 				 * run out of tx buf.
530 				 */
531 				if (!tbf) {
532 					ath_tx_update_baw(sc, tid, seqno);
533 
534 					ath_tx_complete_buf(sc, bf, txq,
535 							    &bf_head, ts, 0);
536 					bar_index = max_t(int, bar_index,
537 						ATH_BA_INDEX(seq_first, seqno));
538 					break;
539 				}
540 
541 				fi->bf = tbf;
542 			}
543 
544 			/*
545 			 * Put this buffer to the temporary pending
546 			 * queue to retain ordering
547 			 */
548 			__skb_queue_tail(&bf_pending, skb);
549 		}
550 
551 		bf = bf_next;
552 	}
553 
554 	/* prepend un-acked frames to the beginning of the pending frame queue */
555 	if (!skb_queue_empty(&bf_pending)) {
556 		if (an->sleeping)
557 			ieee80211_sta_set_buffered(sta, tid->tidno, true);
558 
559 		skb_queue_splice(&bf_pending, &tid->buf_q);
560 		if (!an->sleeping) {
561 			ath_tx_queue_tid(txq, tid);
562 
563 			if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
564 				tid->ac->clear_ps_filter = true;
565 		}
566 	}
567 
568 	if (bar_index >= 0) {
569 		u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
570 
571 		if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
572 			tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
573 
574 		ath_txq_unlock(sc, txq);
575 		ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
576 		ath_txq_lock(sc, txq);
577 	}
578 
579 	rcu_read_unlock();
580 
581 	if (needreset)
582 		ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
583 }
584 
bf_is_ampdu_not_probing(struct ath_buf * bf)585 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
586 {
587     struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
588     return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
589 }
590 
ath_tx_process_buffer(struct ath_softc * sc,struct ath_txq * txq,struct ath_tx_status * ts,struct ath_buf * bf,struct list_head * bf_head)591 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
592 				  struct ath_tx_status *ts, struct ath_buf *bf,
593 				  struct list_head *bf_head)
594 {
595 	struct ieee80211_tx_info *info;
596 	bool txok, flush;
597 
598 	txok = !(ts->ts_status & ATH9K_TXERR_MASK);
599 	flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
600 	txq->axq_tx_inprogress = false;
601 
602 	txq->axq_depth--;
603 	if (bf_is_ampdu_not_probing(bf))
604 		txq->axq_ampdu_depth--;
605 
606 	if (!bf_isampdu(bf)) {
607 		if (!flush) {
608 			info = IEEE80211_SKB_CB(bf->bf_mpdu);
609 			memcpy(info->control.rates, bf->rates,
610 			       sizeof(info->control.rates));
611 			ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
612 		}
613 		ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
614 	} else
615 		ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok);
616 
617 	if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) && !flush)
618 		ath_txq_schedule(sc, txq);
619 }
620 
ath_lookup_legacy(struct ath_buf * bf)621 static bool ath_lookup_legacy(struct ath_buf *bf)
622 {
623 	struct sk_buff *skb;
624 	struct ieee80211_tx_info *tx_info;
625 	struct ieee80211_tx_rate *rates;
626 	int i;
627 
628 	skb = bf->bf_mpdu;
629 	tx_info = IEEE80211_SKB_CB(skb);
630 	rates = tx_info->control.rates;
631 
632 	for (i = 0; i < 4; i++) {
633 		if (!rates[i].count || rates[i].idx < 0)
634 			break;
635 
636 		if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
637 			return true;
638 	}
639 
640 	return false;
641 }
642 
ath_lookup_rate(struct ath_softc * sc,struct ath_buf * bf,struct ath_atx_tid * tid)643 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
644 			   struct ath_atx_tid *tid)
645 {
646 	struct sk_buff *skb;
647 	struct ieee80211_tx_info *tx_info;
648 	struct ieee80211_tx_rate *rates;
649 	u32 max_4ms_framelen, frmlen;
650 	u16 aggr_limit, bt_aggr_limit, legacy = 0;
651 	int q = tid->ac->txq->mac80211_qnum;
652 	int i;
653 
654 	skb = bf->bf_mpdu;
655 	tx_info = IEEE80211_SKB_CB(skb);
656 	rates = bf->rates;
657 
658 	/*
659 	 * Find the lowest frame length among the rate series that will have a
660 	 * 4ms (or TXOP limited) transmit duration.
661 	 */
662 	max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
663 
664 	for (i = 0; i < 4; i++) {
665 		int modeidx;
666 
667 		if (!rates[i].count)
668 			continue;
669 
670 		if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
671 			legacy = 1;
672 			break;
673 		}
674 
675 		if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
676 			modeidx = MCS_HT40;
677 		else
678 			modeidx = MCS_HT20;
679 
680 		if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
681 			modeidx++;
682 
683 		frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
684 		max_4ms_framelen = min(max_4ms_framelen, frmlen);
685 	}
686 
687 	/*
688 	 * limit aggregate size by the minimum rate if rate selected is
689 	 * not a probe rate, if rate selected is a probe rate then
690 	 * avoid aggregation of this packet.
691 	 */
692 	if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
693 		return 0;
694 
695 	aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
696 
697 	/*
698 	 * Override the default aggregation limit for BTCOEX.
699 	 */
700 	bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
701 	if (bt_aggr_limit)
702 		aggr_limit = bt_aggr_limit;
703 
704 	/*
705 	 * h/w can accept aggregates up to 16 bit lengths (65535).
706 	 * The IE, however can hold up to 65536, which shows up here
707 	 * as zero. Ignore 65536 since we  are constrained by hw.
708 	 */
709 	if (tid->an->maxampdu)
710 		aggr_limit = min(aggr_limit, tid->an->maxampdu);
711 
712 	return aggr_limit;
713 }
714 
715 /*
716  * Returns the number of delimiters to be added to
717  * meet the minimum required mpdudensity.
718  */
ath_compute_num_delims(struct ath_softc * sc,struct ath_atx_tid * tid,struct ath_buf * bf,u16 frmlen,bool first_subfrm)719 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
720 				  struct ath_buf *bf, u16 frmlen,
721 				  bool first_subfrm)
722 {
723 #define FIRST_DESC_NDELIMS 60
724 	u32 nsymbits, nsymbols;
725 	u16 minlen;
726 	u8 flags, rix;
727 	int width, streams, half_gi, ndelim, mindelim;
728 	struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
729 
730 	/* Select standard number of delimiters based on frame length alone */
731 	ndelim = ATH_AGGR_GET_NDELIM(frmlen);
732 
733 	/*
734 	 * If encryption enabled, hardware requires some more padding between
735 	 * subframes.
736 	 * TODO - this could be improved to be dependent on the rate.
737 	 *      The hardware can keep up at lower rates, but not higher rates
738 	 */
739 	if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
740 	    !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
741 		ndelim += ATH_AGGR_ENCRYPTDELIM;
742 
743 	/*
744 	 * Add delimiter when using RTS/CTS with aggregation
745 	 * and non enterprise AR9003 card
746 	 */
747 	if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
748 	    (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
749 		ndelim = max(ndelim, FIRST_DESC_NDELIMS);
750 
751 	/*
752 	 * Convert desired mpdu density from microeconds to bytes based
753 	 * on highest rate in rate series (i.e. first rate) to determine
754 	 * required minimum length for subframe. Take into account
755 	 * whether high rate is 20 or 40Mhz and half or full GI.
756 	 *
757 	 * If there is no mpdu density restriction, no further calculation
758 	 * is needed.
759 	 */
760 
761 	if (tid->an->mpdudensity == 0)
762 		return ndelim;
763 
764 	rix = bf->rates[0].idx;
765 	flags = bf->rates[0].flags;
766 	width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
767 	half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
768 
769 	if (half_gi)
770 		nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
771 	else
772 		nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
773 
774 	if (nsymbols == 0)
775 		nsymbols = 1;
776 
777 	streams = HT_RC_2_STREAMS(rix);
778 	nsymbits = bits_per_symbol[rix % 8][width] * streams;
779 	minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
780 
781 	if (frmlen < minlen) {
782 		mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
783 		ndelim = max(mindelim, ndelim);
784 	}
785 
786 	return ndelim;
787 }
788 
ath_tx_form_aggr(struct ath_softc * sc,struct ath_txq * txq,struct ath_atx_tid * tid,struct list_head * bf_q,int * aggr_len)789 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
790 					     struct ath_txq *txq,
791 					     struct ath_atx_tid *tid,
792 					     struct list_head *bf_q,
793 					     int *aggr_len)
794 {
795 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
796 	struct ath_buf *bf, *bf_first = NULL, *bf_prev = NULL;
797 	int rl = 0, nframes = 0, ndelim, prev_al = 0;
798 	u16 aggr_limit = 0, al = 0, bpad = 0,
799 		al_delta, h_baw = tid->baw_size / 2;
800 	enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
801 	struct ieee80211_tx_info *tx_info;
802 	struct ath_frame_info *fi;
803 	struct sk_buff *skb;
804 	u16 seqno;
805 
806 	do {
807 		skb = skb_peek(&tid->buf_q);
808 		fi = get_frame_info(skb);
809 		bf = fi->bf;
810 		if (!fi->bf)
811 			bf = ath_tx_setup_buffer(sc, txq, tid, skb);
812 
813 		if (!bf) {
814 			__skb_unlink(skb, &tid->buf_q);
815 			ieee80211_free_txskb(sc->hw, skb);
816 			continue;
817 		}
818 
819 		bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
820 		seqno = bf->bf_state.seqno;
821 
822 		/* do not step over block-ack window */
823 		if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
824 			status = ATH_AGGR_BAW_CLOSED;
825 			break;
826 		}
827 
828 		if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
829 			struct ath_tx_status ts = {};
830 			struct list_head bf_head;
831 
832 			INIT_LIST_HEAD(&bf_head);
833 			list_add(&bf->list, &bf_head);
834 			__skb_unlink(skb, &tid->buf_q);
835 			ath_tx_update_baw(sc, tid, seqno);
836 			ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
837 			continue;
838 		}
839 
840 		if (!bf_first)
841 			bf_first = bf;
842 
843 		if (!rl) {
844 			ath_set_rates(tid->an->vif, tid->an->sta, bf);
845 			aggr_limit = ath_lookup_rate(sc, bf, tid);
846 			rl = 1;
847 		}
848 
849 		/* do not exceed aggregation limit */
850 		al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
851 
852 		if (nframes &&
853 		    ((aggr_limit < (al + bpad + al_delta + prev_al)) ||
854 		     ath_lookup_legacy(bf))) {
855 			status = ATH_AGGR_LIMITED;
856 			break;
857 		}
858 
859 		tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
860 		if (nframes && (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE))
861 			break;
862 
863 		/* do not exceed subframe limit */
864 		if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
865 			status = ATH_AGGR_LIMITED;
866 			break;
867 		}
868 
869 		/* add padding for previous frame to aggregation length */
870 		al += bpad + al_delta;
871 
872 		/*
873 		 * Get the delimiters needed to meet the MPDU
874 		 * density for this node.
875 		 */
876 		ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
877 						!nframes);
878 		bpad = PADBYTES(al_delta) + (ndelim << 2);
879 
880 		nframes++;
881 		bf->bf_next = NULL;
882 
883 		/* link buffers of this frame to the aggregate */
884 		if (!fi->retries)
885 			ath_tx_addto_baw(sc, tid, seqno);
886 		bf->bf_state.ndelim = ndelim;
887 
888 		__skb_unlink(skb, &tid->buf_q);
889 		list_add_tail(&bf->list, bf_q);
890 		if (bf_prev)
891 			bf_prev->bf_next = bf;
892 
893 		bf_prev = bf;
894 
895 	} while (!skb_queue_empty(&tid->buf_q));
896 
897 	*aggr_len = al;
898 
899 	return status;
900 #undef PADBYTES
901 }
902 
903 /*
904  * rix - rate index
905  * pktlen - total bytes (delims + data + fcs + pads + pad delims)
906  * width  - 0 for 20 MHz, 1 for 40 MHz
907  * half_gi - to use 4us v/s 3.6 us for symbol time
908  */
ath_pkt_duration(struct ath_softc * sc,u8 rix,int pktlen,int width,int half_gi,bool shortPreamble)909 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
910 			    int width, int half_gi, bool shortPreamble)
911 {
912 	u32 nbits, nsymbits, duration, nsymbols;
913 	int streams;
914 
915 	/* find number of symbols: PLCP + data */
916 	streams = HT_RC_2_STREAMS(rix);
917 	nbits = (pktlen << 3) + OFDM_PLCP_BITS;
918 	nsymbits = bits_per_symbol[rix % 8][width] * streams;
919 	nsymbols = (nbits + nsymbits - 1) / nsymbits;
920 
921 	if (!half_gi)
922 		duration = SYMBOL_TIME(nsymbols);
923 	else
924 		duration = SYMBOL_TIME_HALFGI(nsymbols);
925 
926 	/* addup duration for legacy/ht training and signal fields */
927 	duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
928 
929 	return duration;
930 }
931 
ath_max_framelen(int usec,int mcs,bool ht40,bool sgi)932 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
933 {
934 	int streams = HT_RC_2_STREAMS(mcs);
935 	int symbols, bits;
936 	int bytes = 0;
937 
938 	symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
939 	bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
940 	bits -= OFDM_PLCP_BITS;
941 	bytes = bits / 8;
942 	bytes -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
943 	if (bytes > 65532)
944 		bytes = 65532;
945 
946 	return bytes;
947 }
948 
ath_update_max_aggr_framelen(struct ath_softc * sc,int queue,int txop)949 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
950 {
951 	u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
952 	int mcs;
953 
954 	/* 4ms is the default (and maximum) duration */
955 	if (!txop || txop > 4096)
956 		txop = 4096;
957 
958 	cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
959 	cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
960 	cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
961 	cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
962 	for (mcs = 0; mcs < 32; mcs++) {
963 		cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
964 		cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
965 		cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
966 		cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
967 	}
968 }
969 
ath_buf_set_rate(struct ath_softc * sc,struct ath_buf * bf,struct ath_tx_info * info,int len)970 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
971 			     struct ath_tx_info *info, int len)
972 {
973 	struct ath_hw *ah = sc->sc_ah;
974 	struct sk_buff *skb;
975 	struct ieee80211_tx_info *tx_info;
976 	struct ieee80211_tx_rate *rates;
977 	const struct ieee80211_rate *rate;
978 	struct ieee80211_hdr *hdr;
979 	struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
980 	int i;
981 	u8 rix = 0;
982 
983 	skb = bf->bf_mpdu;
984 	tx_info = IEEE80211_SKB_CB(skb);
985 	rates = bf->rates;
986 	hdr = (struct ieee80211_hdr *)skb->data;
987 
988 	/* set dur_update_en for l-sig computation except for PS-Poll frames */
989 	info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
990 	info->rtscts_rate = fi->rtscts_rate;
991 
992 	for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
993 		bool is_40, is_sgi, is_sp;
994 		int phy;
995 
996 		if (!rates[i].count || (rates[i].idx < 0))
997 			continue;
998 
999 		rix = rates[i].idx;
1000 		info->rates[i].Tries = rates[i].count;
1001 
1002 		    if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1003 			info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1004 			info->flags |= ATH9K_TXDESC_RTSENA;
1005 		} else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1006 			info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1007 			info->flags |= ATH9K_TXDESC_CTSENA;
1008 		}
1009 
1010 		if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1011 			info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1012 		if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1013 			info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1014 
1015 		is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1016 		is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1017 		is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1018 
1019 		if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1020 			/* MCS rates */
1021 			info->rates[i].Rate = rix | 0x80;
1022 			info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1023 					ah->txchainmask, info->rates[i].Rate);
1024 			info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1025 				 is_40, is_sgi, is_sp);
1026 			if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1027 				info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1028 			continue;
1029 		}
1030 
1031 		/* legacy rates */
1032 		rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1033 		if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1034 		    !(rate->flags & IEEE80211_RATE_ERP_G))
1035 			phy = WLAN_RC_PHY_CCK;
1036 		else
1037 			phy = WLAN_RC_PHY_OFDM;
1038 
1039 		info->rates[i].Rate = rate->hw_value;
1040 		if (rate->hw_value_short) {
1041 			if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1042 				info->rates[i].Rate |= rate->hw_value_short;
1043 		} else {
1044 			is_sp = false;
1045 		}
1046 
1047 		if (bf->bf_state.bfs_paprd)
1048 			info->rates[i].ChSel = ah->txchainmask;
1049 		else
1050 			info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1051 					ah->txchainmask, info->rates[i].Rate);
1052 
1053 		info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1054 			phy, rate->bitrate * 100, len, rix, is_sp);
1055 	}
1056 
1057 	/* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1058 	if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1059 		info->flags &= ~ATH9K_TXDESC_RTSENA;
1060 
1061 	/* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1062 	if (info->flags & ATH9K_TXDESC_RTSENA)
1063 		info->flags &= ~ATH9K_TXDESC_CTSENA;
1064 }
1065 
get_hw_packet_type(struct sk_buff * skb)1066 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1067 {
1068 	struct ieee80211_hdr *hdr;
1069 	enum ath9k_pkt_type htype;
1070 	__le16 fc;
1071 
1072 	hdr = (struct ieee80211_hdr *)skb->data;
1073 	fc = hdr->frame_control;
1074 
1075 	if (ieee80211_is_beacon(fc))
1076 		htype = ATH9K_PKT_TYPE_BEACON;
1077 	else if (ieee80211_is_probe_resp(fc))
1078 		htype = ATH9K_PKT_TYPE_PROBE_RESP;
1079 	else if (ieee80211_is_atim(fc))
1080 		htype = ATH9K_PKT_TYPE_ATIM;
1081 	else if (ieee80211_is_pspoll(fc))
1082 		htype = ATH9K_PKT_TYPE_PSPOLL;
1083 	else
1084 		htype = ATH9K_PKT_TYPE_NORMAL;
1085 
1086 	return htype;
1087 }
1088 
ath_tx_fill_desc(struct ath_softc * sc,struct ath_buf * bf,struct ath_txq * txq,int len)1089 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1090 			     struct ath_txq *txq, int len)
1091 {
1092 	struct ath_hw *ah = sc->sc_ah;
1093 	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1094 	struct ath_buf *bf_first = bf;
1095 	struct ath_tx_info info;
1096 	bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1097 
1098 	memset(&info, 0, sizeof(info));
1099 	info.is_first = true;
1100 	info.is_last = true;
1101 	info.txpower = MAX_RATE_POWER;
1102 	info.qcu = txq->axq_qnum;
1103 
1104 	info.flags = ATH9K_TXDESC_INTREQ;
1105 	if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1106 		info.flags |= ATH9K_TXDESC_NOACK;
1107 	if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1108 		info.flags |= ATH9K_TXDESC_LDPC;
1109 
1110 	ath_buf_set_rate(sc, bf, &info, len);
1111 
1112 	if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
1113 		info.flags |= ATH9K_TXDESC_CLRDMASK;
1114 
1115 	if (bf->bf_state.bfs_paprd)
1116 		info.flags |= (u32) bf->bf_state.bfs_paprd << ATH9K_TXDESC_PAPRD_S;
1117 
1118 
1119 	while (bf) {
1120 		struct sk_buff *skb = bf->bf_mpdu;
1121 		struct ath_frame_info *fi = get_frame_info(skb);
1122 
1123 		info.type = get_hw_packet_type(skb);
1124 		if (bf->bf_next)
1125 			info.link = bf->bf_next->bf_daddr;
1126 		else
1127 			info.link = 0;
1128 
1129 		info.buf_addr[0] = bf->bf_buf_addr;
1130 		info.buf_len[0] = skb->len;
1131 		info.pkt_len = fi->framelen;
1132 		info.keyix = fi->keyix;
1133 		info.keytype = fi->keytype;
1134 
1135 		if (aggr) {
1136 			if (bf == bf_first)
1137 				info.aggr = AGGR_BUF_FIRST;
1138 			else if (!bf->bf_next)
1139 				info.aggr = AGGR_BUF_LAST;
1140 			else
1141 				info.aggr = AGGR_BUF_MIDDLE;
1142 
1143 			info.ndelim = bf->bf_state.ndelim;
1144 			info.aggr_len = len;
1145 		}
1146 
1147 		ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1148 		bf = bf->bf_next;
1149 	}
1150 }
1151 
ath_tx_sched_aggr(struct ath_softc * sc,struct ath_txq * txq,struct ath_atx_tid * tid)1152 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1153 			      struct ath_atx_tid *tid)
1154 {
1155 	struct ath_buf *bf;
1156 	enum ATH_AGGR_STATUS status;
1157 	struct ieee80211_tx_info *tx_info;
1158 	struct list_head bf_q;
1159 	int aggr_len;
1160 
1161 	do {
1162 		if (skb_queue_empty(&tid->buf_q))
1163 			return;
1164 
1165 		INIT_LIST_HEAD(&bf_q);
1166 
1167 		status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
1168 
1169 		/*
1170 		 * no frames picked up to be aggregated;
1171 		 * block-ack window is not open.
1172 		 */
1173 		if (list_empty(&bf_q))
1174 			break;
1175 
1176 		bf = list_first_entry(&bf_q, struct ath_buf, list);
1177 		bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
1178 		tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1179 
1180 		if (tid->ac->clear_ps_filter) {
1181 			tid->ac->clear_ps_filter = false;
1182 			tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1183 		} else {
1184 			tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
1185 		}
1186 
1187 		/* if only one frame, send as non-aggregate */
1188 		if (bf == bf->bf_lastbf) {
1189 			aggr_len = get_frame_info(bf->bf_mpdu)->framelen;
1190 			bf->bf_state.bf_type = BUF_AMPDU;
1191 		} else {
1192 			TX_STAT_INC(txq->axq_qnum, a_aggr);
1193 		}
1194 
1195 		ath_tx_fill_desc(sc, bf, txq, aggr_len);
1196 		ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1197 	} while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
1198 		 status != ATH_AGGR_BAW_CLOSED);
1199 }
1200 
ath_tx_aggr_start(struct ath_softc * sc,struct ieee80211_sta * sta,u16 tid,u16 * ssn)1201 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1202 		      u16 tid, u16 *ssn)
1203 {
1204 	struct ath_atx_tid *txtid;
1205 	struct ath_node *an;
1206 	u8 density;
1207 
1208 	an = (struct ath_node *)sta->drv_priv;
1209 	txtid = ATH_AN_2_TID(an, tid);
1210 
1211 	/* update ampdu factor/density, they may have changed. This may happen
1212 	 * in HT IBSS when a beacon with HT-info is received after the station
1213 	 * has already been added.
1214 	 */
1215 	if (sta->ht_cap.ht_supported) {
1216 		an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1217 				     sta->ht_cap.ampdu_factor);
1218 		density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1219 		an->mpdudensity = density;
1220 	}
1221 
1222 	txtid->active = true;
1223 	txtid->paused = true;
1224 	*ssn = txtid->seq_start = txtid->seq_next;
1225 	txtid->bar_index = -1;
1226 
1227 	memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1228 	txtid->baw_head = txtid->baw_tail = 0;
1229 
1230 	return 0;
1231 }
1232 
ath_tx_aggr_stop(struct ath_softc * sc,struct ieee80211_sta * sta,u16 tid)1233 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1234 {
1235 	struct ath_node *an = (struct ath_node *)sta->drv_priv;
1236 	struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1237 	struct ath_txq *txq = txtid->ac->txq;
1238 
1239 	ath_txq_lock(sc, txq);
1240 	txtid->active = false;
1241 	txtid->paused = true;
1242 	ath_tx_flush_tid(sc, txtid);
1243 	ath_txq_unlock_complete(sc, txq);
1244 }
1245 
ath_tx_aggr_sleep(struct ieee80211_sta * sta,struct ath_softc * sc,struct ath_node * an)1246 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1247 		       struct ath_node *an)
1248 {
1249 	struct ath_atx_tid *tid;
1250 	struct ath_atx_ac *ac;
1251 	struct ath_txq *txq;
1252 	bool buffered;
1253 	int tidno;
1254 
1255 	for (tidno = 0, tid = &an->tid[tidno];
1256 	     tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1257 
1258 		if (!tid->sched)
1259 			continue;
1260 
1261 		ac = tid->ac;
1262 		txq = ac->txq;
1263 
1264 		ath_txq_lock(sc, txq);
1265 
1266 		buffered = !skb_queue_empty(&tid->buf_q);
1267 
1268 		tid->sched = false;
1269 		list_del(&tid->list);
1270 
1271 		if (ac->sched) {
1272 			ac->sched = false;
1273 			list_del(&ac->list);
1274 		}
1275 
1276 		ath_txq_unlock(sc, txq);
1277 
1278 		ieee80211_sta_set_buffered(sta, tidno, buffered);
1279 	}
1280 }
1281 
ath_tx_aggr_wakeup(struct ath_softc * sc,struct ath_node * an)1282 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1283 {
1284 	struct ath_atx_tid *tid;
1285 	struct ath_atx_ac *ac;
1286 	struct ath_txq *txq;
1287 	int tidno;
1288 
1289 	for (tidno = 0, tid = &an->tid[tidno];
1290 	     tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1291 
1292 		ac = tid->ac;
1293 		txq = ac->txq;
1294 
1295 		ath_txq_lock(sc, txq);
1296 		ac->clear_ps_filter = true;
1297 
1298 		if (!skb_queue_empty(&tid->buf_q) && !tid->paused) {
1299 			ath_tx_queue_tid(txq, tid);
1300 			ath_txq_schedule(sc, txq);
1301 		}
1302 
1303 		ath_txq_unlock_complete(sc, txq);
1304 	}
1305 }
1306 
ath_tx_aggr_resume(struct ath_softc * sc,struct ieee80211_sta * sta,u16 tidno)1307 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta,
1308 			u16 tidno)
1309 {
1310 	struct ath_atx_tid *tid;
1311 	struct ath_node *an;
1312 	struct ath_txq *txq;
1313 
1314 	an = (struct ath_node *)sta->drv_priv;
1315 	tid = ATH_AN_2_TID(an, tidno);
1316 	txq = tid->ac->txq;
1317 
1318 	ath_txq_lock(sc, txq);
1319 
1320 	tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1321 	tid->paused = false;
1322 
1323 	if (!skb_queue_empty(&tid->buf_q)) {
1324 		ath_tx_queue_tid(txq, tid);
1325 		ath_txq_schedule(sc, txq);
1326 	}
1327 
1328 	ath_txq_unlock_complete(sc, txq);
1329 }
1330 
1331 /********************/
1332 /* Queue Management */
1333 /********************/
1334 
ath_txq_setup(struct ath_softc * sc,int qtype,int subtype)1335 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1336 {
1337 	struct ath_hw *ah = sc->sc_ah;
1338 	struct ath9k_tx_queue_info qi;
1339 	static const int subtype_txq_to_hwq[] = {
1340 		[IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1341 		[IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1342 		[IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1343 		[IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1344 	};
1345 	int axq_qnum, i;
1346 
1347 	memset(&qi, 0, sizeof(qi));
1348 	qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1349 	qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1350 	qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1351 	qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1352 	qi.tqi_physCompBuf = 0;
1353 
1354 	/*
1355 	 * Enable interrupts only for EOL and DESC conditions.
1356 	 * We mark tx descriptors to receive a DESC interrupt
1357 	 * when a tx queue gets deep; otherwise waiting for the
1358 	 * EOL to reap descriptors.  Note that this is done to
1359 	 * reduce interrupt load and this only defers reaping
1360 	 * descriptors, never transmitting frames.  Aside from
1361 	 * reducing interrupts this also permits more concurrency.
1362 	 * The only potential downside is if the tx queue backs
1363 	 * up in which case the top half of the kernel may backup
1364 	 * due to a lack of tx descriptors.
1365 	 *
1366 	 * The UAPSD queue is an exception, since we take a desc-
1367 	 * based intr on the EOSP frames.
1368 	 */
1369 	if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1370 		qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1371 	} else {
1372 		if (qtype == ATH9K_TX_QUEUE_UAPSD)
1373 			qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1374 		else
1375 			qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1376 					TXQ_FLAG_TXDESCINT_ENABLE;
1377 	}
1378 	axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1379 	if (axq_qnum == -1) {
1380 		/*
1381 		 * NB: don't print a message, this happens
1382 		 * normally on parts with too few tx queues
1383 		 */
1384 		return NULL;
1385 	}
1386 	if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1387 		struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1388 
1389 		txq->axq_qnum = axq_qnum;
1390 		txq->mac80211_qnum = -1;
1391 		txq->axq_link = NULL;
1392 		__skb_queue_head_init(&txq->complete_q);
1393 		INIT_LIST_HEAD(&txq->axq_q);
1394 		INIT_LIST_HEAD(&txq->axq_acq);
1395 		spin_lock_init(&txq->axq_lock);
1396 		txq->axq_depth = 0;
1397 		txq->axq_ampdu_depth = 0;
1398 		txq->axq_tx_inprogress = false;
1399 		sc->tx.txqsetup |= 1<<axq_qnum;
1400 
1401 		txq->txq_headidx = txq->txq_tailidx = 0;
1402 		for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1403 			INIT_LIST_HEAD(&txq->txq_fifo[i]);
1404 	}
1405 	return &sc->tx.txq[axq_qnum];
1406 }
1407 
ath_txq_update(struct ath_softc * sc,int qnum,struct ath9k_tx_queue_info * qinfo)1408 int ath_txq_update(struct ath_softc *sc, int qnum,
1409 		   struct ath9k_tx_queue_info *qinfo)
1410 {
1411 	struct ath_hw *ah = sc->sc_ah;
1412 	int error = 0;
1413 	struct ath9k_tx_queue_info qi;
1414 
1415 	BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1416 
1417 	ath9k_hw_get_txq_props(ah, qnum, &qi);
1418 	qi.tqi_aifs = qinfo->tqi_aifs;
1419 	qi.tqi_cwmin = qinfo->tqi_cwmin;
1420 	qi.tqi_cwmax = qinfo->tqi_cwmax;
1421 	qi.tqi_burstTime = qinfo->tqi_burstTime;
1422 	qi.tqi_readyTime = qinfo->tqi_readyTime;
1423 
1424 	if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1425 		ath_err(ath9k_hw_common(sc->sc_ah),
1426 			"Unable to update hardware queue %u!\n", qnum);
1427 		error = -EIO;
1428 	} else {
1429 		ath9k_hw_resettxqueue(ah, qnum);
1430 	}
1431 
1432 	return error;
1433 }
1434 
ath_cabq_update(struct ath_softc * sc)1435 int ath_cabq_update(struct ath_softc *sc)
1436 {
1437 	struct ath9k_tx_queue_info qi;
1438 	struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1439 	int qnum = sc->beacon.cabq->axq_qnum;
1440 
1441 	ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1442 	/*
1443 	 * Ensure the readytime % is within the bounds.
1444 	 */
1445 	if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1446 		sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1447 	else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1448 		sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1449 
1450 	qi.tqi_readyTime = (cur_conf->beacon_interval *
1451 			    sc->config.cabqReadytime) / 100;
1452 	ath_txq_update(sc, qnum, &qi);
1453 
1454 	return 0;
1455 }
1456 
ath_drain_txq_list(struct ath_softc * sc,struct ath_txq * txq,struct list_head * list)1457 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1458 			       struct list_head *list)
1459 {
1460 	struct ath_buf *bf, *lastbf;
1461 	struct list_head bf_head;
1462 	struct ath_tx_status ts;
1463 
1464 	memset(&ts, 0, sizeof(ts));
1465 	ts.ts_status = ATH9K_TX_FLUSH;
1466 	INIT_LIST_HEAD(&bf_head);
1467 
1468 	while (!list_empty(list)) {
1469 		bf = list_first_entry(list, struct ath_buf, list);
1470 
1471 		if (bf->bf_stale) {
1472 			list_del(&bf->list);
1473 
1474 			ath_tx_return_buffer(sc, bf);
1475 			continue;
1476 		}
1477 
1478 		lastbf = bf->bf_lastbf;
1479 		list_cut_position(&bf_head, list, &lastbf->list);
1480 		ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1481 	}
1482 }
1483 
1484 /*
1485  * Drain a given TX queue (could be Beacon or Data)
1486  *
1487  * This assumes output has been stopped and
1488  * we do not need to block ath_tx_tasklet.
1489  */
ath_draintxq(struct ath_softc * sc,struct ath_txq * txq)1490 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1491 {
1492 	ath_txq_lock(sc, txq);
1493 
1494 	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1495 		int idx = txq->txq_tailidx;
1496 
1497 		while (!list_empty(&txq->txq_fifo[idx])) {
1498 			ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1499 
1500 			INCR(idx, ATH_TXFIFO_DEPTH);
1501 		}
1502 		txq->txq_tailidx = idx;
1503 	}
1504 
1505 	txq->axq_link = NULL;
1506 	txq->axq_tx_inprogress = false;
1507 	ath_drain_txq_list(sc, txq, &txq->axq_q);
1508 
1509 	ath_txq_unlock_complete(sc, txq);
1510 }
1511 
ath_drain_all_txq(struct ath_softc * sc)1512 bool ath_drain_all_txq(struct ath_softc *sc)
1513 {
1514 	struct ath_hw *ah = sc->sc_ah;
1515 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1516 	struct ath_txq *txq;
1517 	int i;
1518 	u32 npend = 0;
1519 
1520 	if (test_bit(SC_OP_INVALID, &sc->sc_flags))
1521 		return true;
1522 
1523 	ath9k_hw_abort_tx_dma(ah);
1524 
1525 	/* Check if any queue remains active */
1526 	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1527 		if (!ATH_TXQ_SETUP(sc, i))
1528 			continue;
1529 
1530 		if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1531 			npend |= BIT(i);
1532 	}
1533 
1534 	if (npend)
1535 		ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1536 
1537 	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1538 		if (!ATH_TXQ_SETUP(sc, i))
1539 			continue;
1540 
1541 		/*
1542 		 * The caller will resume queues with ieee80211_wake_queues.
1543 		 * Mark the queue as not stopped to prevent ath_tx_complete
1544 		 * from waking the queue too early.
1545 		 */
1546 		txq = &sc->tx.txq[i];
1547 		txq->stopped = false;
1548 		ath_draintxq(sc, txq);
1549 	}
1550 
1551 	return !npend;
1552 }
1553 
ath_tx_cleanupq(struct ath_softc * sc,struct ath_txq * txq)1554 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1555 {
1556 	ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1557 	sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1558 }
1559 
1560 /* For each axq_acq entry, for each tid, try to schedule packets
1561  * for transmit until ampdu_depth has reached min Q depth.
1562  */
ath_txq_schedule(struct ath_softc * sc,struct ath_txq * txq)1563 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1564 {
1565 	struct ath_atx_ac *ac, *ac_tmp, *last_ac;
1566 	struct ath_atx_tid *tid, *last_tid;
1567 
1568 	if (test_bit(SC_OP_HW_RESET, &sc->sc_flags) ||
1569 	    list_empty(&txq->axq_acq) ||
1570 	    txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1571 		return;
1572 
1573 	rcu_read_lock();
1574 
1575 	ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1576 	last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1577 
1578 	list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1579 		last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1580 		list_del(&ac->list);
1581 		ac->sched = false;
1582 
1583 		while (!list_empty(&ac->tid_q)) {
1584 			tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1585 					       list);
1586 			list_del(&tid->list);
1587 			tid->sched = false;
1588 
1589 			if (tid->paused)
1590 				continue;
1591 
1592 			ath_tx_sched_aggr(sc, txq, tid);
1593 
1594 			/*
1595 			 * add tid to round-robin queue if more frames
1596 			 * are pending for the tid
1597 			 */
1598 			if (!skb_queue_empty(&tid->buf_q))
1599 				ath_tx_queue_tid(txq, tid);
1600 
1601 			if (tid == last_tid ||
1602 			    txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1603 				break;
1604 		}
1605 
1606 		if (!list_empty(&ac->tid_q) && !ac->sched) {
1607 			ac->sched = true;
1608 			list_add_tail(&ac->list, &txq->axq_acq);
1609 		}
1610 
1611 		if (ac == last_ac ||
1612 		    txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1613 			break;
1614 	}
1615 
1616 	rcu_read_unlock();
1617 }
1618 
1619 /***********/
1620 /* TX, DMA */
1621 /***********/
1622 
1623 /*
1624  * Insert a chain of ath_buf (descriptors) on a txq and
1625  * assume the descriptors are already chained together by caller.
1626  */
ath_tx_txqaddbuf(struct ath_softc * sc,struct ath_txq * txq,struct list_head * head,bool internal)1627 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1628 			     struct list_head *head, bool internal)
1629 {
1630 	struct ath_hw *ah = sc->sc_ah;
1631 	struct ath_common *common = ath9k_hw_common(ah);
1632 	struct ath_buf *bf, *bf_last;
1633 	bool puttxbuf = false;
1634 	bool edma;
1635 
1636 	/*
1637 	 * Insert the frame on the outbound list and
1638 	 * pass it on to the hardware.
1639 	 */
1640 
1641 	if (list_empty(head))
1642 		return;
1643 
1644 	edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1645 	bf = list_first_entry(head, struct ath_buf, list);
1646 	bf_last = list_entry(head->prev, struct ath_buf, list);
1647 
1648 	ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
1649 		txq->axq_qnum, txq->axq_depth);
1650 
1651 	if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1652 		list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1653 		INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1654 		puttxbuf = true;
1655 	} else {
1656 		list_splice_tail_init(head, &txq->axq_q);
1657 
1658 		if (txq->axq_link) {
1659 			ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1660 			ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
1661 				txq->axq_qnum, txq->axq_link,
1662 				ito64(bf->bf_daddr), bf->bf_desc);
1663 		} else if (!edma)
1664 			puttxbuf = true;
1665 
1666 		txq->axq_link = bf_last->bf_desc;
1667 	}
1668 
1669 	if (puttxbuf) {
1670 		TX_STAT_INC(txq->axq_qnum, puttxbuf);
1671 		ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1672 		ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
1673 			txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1674 	}
1675 
1676 	if (!edma) {
1677 		TX_STAT_INC(txq->axq_qnum, txstart);
1678 		ath9k_hw_txstart(ah, txq->axq_qnum);
1679 	}
1680 
1681 	if (!internal) {
1682 		txq->axq_depth++;
1683 		if (bf_is_ampdu_not_probing(bf))
1684 			txq->axq_ampdu_depth++;
1685 	}
1686 }
1687 
ath_tx_send_ampdu(struct ath_softc * sc,struct ath_atx_tid * tid,struct sk_buff * skb,struct ath_tx_control * txctl)1688 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1689 			      struct sk_buff *skb, struct ath_tx_control *txctl)
1690 {
1691 	struct ath_frame_info *fi = get_frame_info(skb);
1692 	struct list_head bf_head;
1693 	struct ath_buf *bf;
1694 
1695 	/*
1696 	 * Do not queue to h/w when any of the following conditions is true:
1697 	 * - there are pending frames in software queue
1698 	 * - the TID is currently paused for ADDBA/BAR request
1699 	 * - seqno is not within block-ack window
1700 	 * - h/w queue depth exceeds low water mark
1701 	 */
1702 	if (!skb_queue_empty(&tid->buf_q) || tid->paused ||
1703 	    !BAW_WITHIN(tid->seq_start, tid->baw_size, tid->seq_next) ||
1704 	    txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
1705 		/*
1706 		 * Add this frame to software queue for scheduling later
1707 		 * for aggregation.
1708 		 */
1709 		TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw);
1710 		__skb_queue_tail(&tid->buf_q, skb);
1711 		if (!txctl->an || !txctl->an->sleeping)
1712 			ath_tx_queue_tid(txctl->txq, tid);
1713 		return;
1714 	}
1715 
1716 	bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb);
1717 	if (!bf) {
1718 		ieee80211_free_txskb(sc->hw, skb);
1719 		return;
1720 	}
1721 
1722 	ath_set_rates(tid->an->vif, tid->an->sta, bf);
1723 	bf->bf_state.bf_type = BUF_AMPDU;
1724 	INIT_LIST_HEAD(&bf_head);
1725 	list_add(&bf->list, &bf_head);
1726 
1727 	/* Add sub-frame to BAW */
1728 	ath_tx_addto_baw(sc, tid, bf->bf_state.seqno);
1729 
1730 	/* Queue to h/w without aggregation */
1731 	TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
1732 	bf->bf_lastbf = bf;
1733 	ath_tx_fill_desc(sc, bf, txctl->txq, fi->framelen);
1734 	ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false);
1735 }
1736 
ath_tx_send_normal(struct ath_softc * sc,struct ath_txq * txq,struct ath_atx_tid * tid,struct sk_buff * skb)1737 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1738 			       struct ath_atx_tid *tid, struct sk_buff *skb)
1739 {
1740 	struct ath_frame_info *fi = get_frame_info(skb);
1741 	struct list_head bf_head;
1742 	struct ath_buf *bf;
1743 
1744 	bf = fi->bf;
1745 
1746 	INIT_LIST_HEAD(&bf_head);
1747 	list_add_tail(&bf->list, &bf_head);
1748 	bf->bf_state.bf_type = 0;
1749 
1750 	bf->bf_next = NULL;
1751 	bf->bf_lastbf = bf;
1752 	ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1753 	ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1754 	TX_STAT_INC(txq->axq_qnum, queued);
1755 }
1756 
setup_frame_info(struct ieee80211_hw * hw,struct ieee80211_sta * sta,struct sk_buff * skb,int framelen)1757 static void setup_frame_info(struct ieee80211_hw *hw,
1758 			     struct ieee80211_sta *sta,
1759 			     struct sk_buff *skb,
1760 			     int framelen)
1761 {
1762 	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1763 	struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1764 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1765 	const struct ieee80211_rate *rate;
1766 	struct ath_frame_info *fi = get_frame_info(skb);
1767 	struct ath_node *an = NULL;
1768 	enum ath9k_key_type keytype;
1769 	bool short_preamble = false;
1770 
1771 	/*
1772 	 * We check if Short Preamble is needed for the CTS rate by
1773 	 * checking the BSS's global flag.
1774 	 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1775 	 */
1776 	if (tx_info->control.vif &&
1777 	    tx_info->control.vif->bss_conf.use_short_preamble)
1778 		short_preamble = true;
1779 
1780 	rate = ieee80211_get_rts_cts_rate(hw, tx_info);
1781 	keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1782 
1783 	if (sta)
1784 		an = (struct ath_node *) sta->drv_priv;
1785 
1786 	memset(fi, 0, sizeof(*fi));
1787 	if (hw_key)
1788 		fi->keyix = hw_key->hw_key_idx;
1789 	else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
1790 		fi->keyix = an->ps_key;
1791 	else
1792 		fi->keyix = ATH9K_TXKEYIX_INVALID;
1793 	fi->keytype = keytype;
1794 	fi->framelen = framelen;
1795 	fi->rtscts_rate = rate->hw_value;
1796 	if (short_preamble)
1797 		fi->rtscts_rate |= rate->hw_value_short;
1798 }
1799 
ath_txchainmask_reduction(struct ath_softc * sc,u8 chainmask,u32 rate)1800 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1801 {
1802 	struct ath_hw *ah = sc->sc_ah;
1803 	struct ath9k_channel *curchan = ah->curchan;
1804 
1805 	if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
1806 	    (curchan->channelFlags & CHANNEL_5GHZ) &&
1807 	    (chainmask == 0x7) && (rate < 0x90))
1808 		return 0x3;
1809 	else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
1810 		 IS_CCK_RATE(rate))
1811 		return 0x2;
1812 	else
1813 		return chainmask;
1814 }
1815 
1816 /*
1817  * Assign a descriptor (and sequence number if necessary,
1818  * and map buffer for DMA. Frees skb on error
1819  */
ath_tx_setup_buffer(struct ath_softc * sc,struct ath_txq * txq,struct ath_atx_tid * tid,struct sk_buff * skb)1820 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
1821 					   struct ath_txq *txq,
1822 					   struct ath_atx_tid *tid,
1823 					   struct sk_buff *skb)
1824 {
1825 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1826 	struct ath_frame_info *fi = get_frame_info(skb);
1827 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1828 	struct ath_buf *bf;
1829 	int fragno;
1830 	u16 seqno;
1831 
1832 	bf = ath_tx_get_buffer(sc);
1833 	if (!bf) {
1834 		ath_dbg(common, XMIT, "TX buffers are full\n");
1835 		return NULL;
1836 	}
1837 
1838 	ATH_TXBUF_RESET(bf);
1839 
1840 	if (tid) {
1841 		fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
1842 		seqno = tid->seq_next;
1843 		hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
1844 
1845 		if (fragno)
1846 			hdr->seq_ctrl |= cpu_to_le16(fragno);
1847 
1848 		if (!ieee80211_has_morefrags(hdr->frame_control))
1849 			INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1850 
1851 		bf->bf_state.seqno = seqno;
1852 	}
1853 
1854 	bf->bf_mpdu = skb;
1855 
1856 	bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
1857 					 skb->len, DMA_TO_DEVICE);
1858 	if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
1859 		bf->bf_mpdu = NULL;
1860 		bf->bf_buf_addr = 0;
1861 		ath_err(ath9k_hw_common(sc->sc_ah),
1862 			"dma_mapping_error() on TX\n");
1863 		ath_tx_return_buffer(sc, bf);
1864 		return NULL;
1865 	}
1866 
1867 	fi->bf = bf;
1868 
1869 	return bf;
1870 }
1871 
1872 /* Upon failure caller should free skb */
ath_tx_start(struct ieee80211_hw * hw,struct sk_buff * skb,struct ath_tx_control * txctl)1873 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1874 		 struct ath_tx_control *txctl)
1875 {
1876 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1877 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1878 	struct ieee80211_sta *sta = txctl->sta;
1879 	struct ieee80211_vif *vif = info->control.vif;
1880 	struct ath_softc *sc = hw->priv;
1881 	struct ath_txq *txq = txctl->txq;
1882 	struct ath_atx_tid *tid = NULL;
1883 	struct ath_buf *bf;
1884 	int padpos, padsize;
1885 	int frmlen = skb->len + FCS_LEN;
1886 	u8 tidno;
1887 	int q;
1888 
1889 	/* NOTE:  sta can be NULL according to net/mac80211.h */
1890 	if (sta)
1891 		txctl->an = (struct ath_node *)sta->drv_priv;
1892 
1893 	if (info->control.hw_key)
1894 		frmlen += info->control.hw_key->icv_len;
1895 
1896 	/*
1897 	 * As a temporary workaround, assign seq# here; this will likely need
1898 	 * to be cleaned up to work better with Beacon transmission and virtual
1899 	 * BSSes.
1900 	 */
1901 	if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1902 		if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1903 			sc->tx.seq_no += 0x10;
1904 		hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1905 		hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1906 	}
1907 
1908 	/* Add the padding after the header if this is not already done */
1909 	padpos = ieee80211_hdrlen(hdr->frame_control);
1910 	padsize = padpos & 3;
1911 	if (padsize && skb->len > padpos) {
1912 		if (skb_headroom(skb) < padsize)
1913 			return -ENOMEM;
1914 
1915 		skb_push(skb, padsize);
1916 		memmove(skb->data, skb->data + padsize, padpos);
1917 		hdr = (struct ieee80211_hdr *) skb->data;
1918 	}
1919 
1920 	if ((vif && vif->type != NL80211_IFTYPE_AP &&
1921 	            vif->type != NL80211_IFTYPE_AP_VLAN) ||
1922 	    !ieee80211_is_data(hdr->frame_control))
1923 		info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1924 
1925 	setup_frame_info(hw, sta, skb, frmlen);
1926 
1927 	/*
1928 	 * At this point, the vif, hw_key and sta pointers in the tx control
1929 	 * info are no longer valid (overwritten by the ath_frame_info data.
1930 	 */
1931 
1932 	q = skb_get_queue_mapping(skb);
1933 
1934 	ath_txq_lock(sc, txq);
1935 	if (txq == sc->tx.txq_map[q] &&
1936 	    ++txq->pending_frames > sc->tx.txq_max_pending[q] &&
1937 	    !txq->stopped) {
1938 		ieee80211_stop_queue(sc->hw, q);
1939 		txq->stopped = true;
1940 	}
1941 
1942 	if (txctl->an && ieee80211_is_data_qos(hdr->frame_control)) {
1943 		tidno = ieee80211_get_qos_ctl(hdr)[0] &
1944 			IEEE80211_QOS_CTL_TID_MASK;
1945 		tid = ATH_AN_2_TID(txctl->an, tidno);
1946 
1947 		WARN_ON(tid->ac->txq != txctl->txq);
1948 	}
1949 
1950 	if ((info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
1951 		/*
1952 		 * Try aggregation if it's a unicast data frame
1953 		 * and the destination is HT capable.
1954 		 */
1955 		ath_tx_send_ampdu(sc, tid, skb, txctl);
1956 		goto out;
1957 	}
1958 
1959 	bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb);
1960 	if (!bf) {
1961 		if (txctl->paprd)
1962 			dev_kfree_skb_any(skb);
1963 		else
1964 			ieee80211_free_txskb(sc->hw, skb);
1965 		goto out;
1966 	}
1967 
1968 	bf->bf_state.bfs_paprd = txctl->paprd;
1969 
1970 	if (txctl->paprd)
1971 		bf->bf_state.bfs_paprd_timestamp = jiffies;
1972 
1973 	ath_set_rates(vif, sta, bf);
1974 	ath_tx_send_normal(sc, txctl->txq, tid, skb);
1975 
1976 out:
1977 	ath_txq_unlock(sc, txq);
1978 
1979 	return 0;
1980 }
1981 
1982 /*****************/
1983 /* TX Completion */
1984 /*****************/
1985 
ath_tx_complete(struct ath_softc * sc,struct sk_buff * skb,int tx_flags,struct ath_txq * txq)1986 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1987 			    int tx_flags, struct ath_txq *txq)
1988 {
1989 	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1990 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1991 	struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1992 	int q, padpos, padsize;
1993 	unsigned long flags;
1994 
1995 	ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
1996 
1997 	if (sc->sc_ah->caldata)
1998 		sc->sc_ah->caldata->paprd_packet_sent = true;
1999 
2000 	if (!(tx_flags & ATH_TX_ERROR))
2001 		/* Frame was ACKed */
2002 		tx_info->flags |= IEEE80211_TX_STAT_ACK;
2003 
2004 	padpos = ieee80211_hdrlen(hdr->frame_control);
2005 	padsize = padpos & 3;
2006 	if (padsize && skb->len>padpos+padsize) {
2007 		/*
2008 		 * Remove MAC header padding before giving the frame back to
2009 		 * mac80211.
2010 		 */
2011 		memmove(skb->data + padsize, skb->data, padpos);
2012 		skb_pull(skb, padsize);
2013 	}
2014 
2015 	spin_lock_irqsave(&sc->sc_pm_lock, flags);
2016 	if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2017 		sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2018 		ath_dbg(common, PS,
2019 			"Going back to sleep after having received TX status (0x%lx)\n",
2020 			sc->ps_flags & (PS_WAIT_FOR_BEACON |
2021 					PS_WAIT_FOR_CAB |
2022 					PS_WAIT_FOR_PSPOLL_DATA |
2023 					PS_WAIT_FOR_TX_ACK));
2024 	}
2025 	spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2026 
2027 	q = skb_get_queue_mapping(skb);
2028 	if (txq == sc->tx.txq_map[q]) {
2029 		if (WARN_ON(--txq->pending_frames < 0))
2030 			txq->pending_frames = 0;
2031 
2032 		if (txq->stopped &&
2033 		    txq->pending_frames < sc->tx.txq_max_pending[q]) {
2034 			ieee80211_wake_queue(sc->hw, q);
2035 			txq->stopped = false;
2036 		}
2037 	}
2038 
2039 	__skb_queue_tail(&txq->complete_q, skb);
2040 }
2041 
ath_tx_complete_buf(struct ath_softc * sc,struct ath_buf * bf,struct ath_txq * txq,struct list_head * bf_q,struct ath_tx_status * ts,int txok)2042 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2043 				struct ath_txq *txq, struct list_head *bf_q,
2044 				struct ath_tx_status *ts, int txok)
2045 {
2046 	struct sk_buff *skb = bf->bf_mpdu;
2047 	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2048 	unsigned long flags;
2049 	int tx_flags = 0;
2050 
2051 	if (!txok)
2052 		tx_flags |= ATH_TX_ERROR;
2053 
2054 	if (ts->ts_status & ATH9K_TXERR_FILT)
2055 		tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2056 
2057 	dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2058 	bf->bf_buf_addr = 0;
2059 
2060 	if (bf->bf_state.bfs_paprd) {
2061 		if (time_after(jiffies,
2062 				bf->bf_state.bfs_paprd_timestamp +
2063 				msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2064 			dev_kfree_skb_any(skb);
2065 		else
2066 			complete(&sc->paprd_complete);
2067 	} else {
2068 		ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2069 		ath_tx_complete(sc, skb, tx_flags, txq);
2070 	}
2071 	/* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2072 	 * accidentally reference it later.
2073 	 */
2074 	bf->bf_mpdu = NULL;
2075 
2076 	/*
2077 	 * Return the list of ath_buf of this mpdu to free queue
2078 	 */
2079 	spin_lock_irqsave(&sc->tx.txbuflock, flags);
2080 	list_splice_tail_init(bf_q, &sc->tx.txbuf);
2081 	spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2082 }
2083 
ath_tx_rc_status(struct ath_softc * sc,struct ath_buf * bf,struct ath_tx_status * ts,int nframes,int nbad,int txok)2084 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2085 			     struct ath_tx_status *ts, int nframes, int nbad,
2086 			     int txok)
2087 {
2088 	struct sk_buff *skb = bf->bf_mpdu;
2089 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2090 	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2091 	struct ieee80211_hw *hw = sc->hw;
2092 	struct ath_hw *ah = sc->sc_ah;
2093 	u8 i, tx_rateindex;
2094 
2095 	if (txok)
2096 		tx_info->status.ack_signal = ts->ts_rssi;
2097 
2098 	tx_rateindex = ts->ts_rateindex;
2099 	WARN_ON(tx_rateindex >= hw->max_rates);
2100 
2101 	if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2102 		tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2103 
2104 		BUG_ON(nbad > nframes);
2105 	}
2106 	tx_info->status.ampdu_len = nframes;
2107 	tx_info->status.ampdu_ack_len = nframes - nbad;
2108 
2109 	if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2110 	    (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2111 		/*
2112 		 * If an underrun error is seen assume it as an excessive
2113 		 * retry only if max frame trigger level has been reached
2114 		 * (2 KB for single stream, and 4 KB for dual stream).
2115 		 * Adjust the long retry as if the frame was tried
2116 		 * hw->max_rate_tries times to affect how rate control updates
2117 		 * PER for the failed rate.
2118 		 * In case of congestion on the bus penalizing this type of
2119 		 * underruns should help hardware actually transmit new frames
2120 		 * successfully by eventually preferring slower rates.
2121 		 * This itself should also alleviate congestion on the bus.
2122 		 */
2123 		if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2124 		                             ATH9K_TX_DELIM_UNDERRUN)) &&
2125 		    ieee80211_is_data(hdr->frame_control) &&
2126 		    ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2127 			tx_info->status.rates[tx_rateindex].count =
2128 				hw->max_rate_tries;
2129 	}
2130 
2131 	for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2132 		tx_info->status.rates[i].count = 0;
2133 		tx_info->status.rates[i].idx = -1;
2134 	}
2135 
2136 	tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2137 }
2138 
ath_tx_processq(struct ath_softc * sc,struct ath_txq * txq)2139 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2140 {
2141 	struct ath_hw *ah = sc->sc_ah;
2142 	struct ath_common *common = ath9k_hw_common(ah);
2143 	struct ath_buf *bf, *lastbf, *bf_held = NULL;
2144 	struct list_head bf_head;
2145 	struct ath_desc *ds;
2146 	struct ath_tx_status ts;
2147 	int status;
2148 
2149 	ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2150 		txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2151 		txq->axq_link);
2152 
2153 	ath_txq_lock(sc, txq);
2154 	for (;;) {
2155 		if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2156 			break;
2157 
2158 		if (list_empty(&txq->axq_q)) {
2159 			txq->axq_link = NULL;
2160 			if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2161 				ath_txq_schedule(sc, txq);
2162 			break;
2163 		}
2164 		bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2165 
2166 		/*
2167 		 * There is a race condition that a BH gets scheduled
2168 		 * after sw writes TxE and before hw re-load the last
2169 		 * descriptor to get the newly chained one.
2170 		 * Software must keep the last DONE descriptor as a
2171 		 * holding descriptor - software does so by marking
2172 		 * it with the STALE flag.
2173 		 */
2174 		bf_held = NULL;
2175 		if (bf->bf_stale) {
2176 			bf_held = bf;
2177 			if (list_is_last(&bf_held->list, &txq->axq_q))
2178 				break;
2179 
2180 			bf = list_entry(bf_held->list.next, struct ath_buf,
2181 					list);
2182 		}
2183 
2184 		lastbf = bf->bf_lastbf;
2185 		ds = lastbf->bf_desc;
2186 
2187 		memset(&ts, 0, sizeof(ts));
2188 		status = ath9k_hw_txprocdesc(ah, ds, &ts);
2189 		if (status == -EINPROGRESS)
2190 			break;
2191 
2192 		TX_STAT_INC(txq->axq_qnum, txprocdesc);
2193 
2194 		/*
2195 		 * Remove ath_buf's of the same transmit unit from txq,
2196 		 * however leave the last descriptor back as the holding
2197 		 * descriptor for hw.
2198 		 */
2199 		lastbf->bf_stale = true;
2200 		INIT_LIST_HEAD(&bf_head);
2201 		if (!list_is_singular(&lastbf->list))
2202 			list_cut_position(&bf_head,
2203 				&txq->axq_q, lastbf->list.prev);
2204 
2205 		if (bf_held) {
2206 			list_del(&bf_held->list);
2207 			ath_tx_return_buffer(sc, bf_held);
2208 		}
2209 
2210 		ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2211 	}
2212 	ath_txq_unlock_complete(sc, txq);
2213 }
2214 
ath_tx_tasklet(struct ath_softc * sc)2215 void ath_tx_tasklet(struct ath_softc *sc)
2216 {
2217 	struct ath_hw *ah = sc->sc_ah;
2218 	u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2219 	int i;
2220 
2221 	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2222 		if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2223 			ath_tx_processq(sc, &sc->tx.txq[i]);
2224 	}
2225 }
2226 
ath_tx_edma_tasklet(struct ath_softc * sc)2227 void ath_tx_edma_tasklet(struct ath_softc *sc)
2228 {
2229 	struct ath_tx_status ts;
2230 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2231 	struct ath_hw *ah = sc->sc_ah;
2232 	struct ath_txq *txq;
2233 	struct ath_buf *bf, *lastbf;
2234 	struct list_head bf_head;
2235 	struct list_head *fifo_list;
2236 	int status;
2237 
2238 	for (;;) {
2239 		if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2240 			break;
2241 
2242 		status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2243 		if (status == -EINPROGRESS)
2244 			break;
2245 		if (status == -EIO) {
2246 			ath_dbg(common, XMIT, "Error processing tx status\n");
2247 			break;
2248 		}
2249 
2250 		/* Process beacon completions separately */
2251 		if (ts.qid == sc->beacon.beaconq) {
2252 			sc->beacon.tx_processed = true;
2253 			sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2254 			continue;
2255 		}
2256 
2257 		txq = &sc->tx.txq[ts.qid];
2258 
2259 		ath_txq_lock(sc, txq);
2260 
2261 		TX_STAT_INC(txq->axq_qnum, txprocdesc);
2262 
2263 		fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2264 		if (list_empty(fifo_list)) {
2265 			ath_txq_unlock(sc, txq);
2266 			return;
2267 		}
2268 
2269 		bf = list_first_entry(fifo_list, struct ath_buf, list);
2270 		if (bf->bf_stale) {
2271 			list_del(&bf->list);
2272 			ath_tx_return_buffer(sc, bf);
2273 			bf = list_first_entry(fifo_list, struct ath_buf, list);
2274 		}
2275 
2276 		lastbf = bf->bf_lastbf;
2277 
2278 		INIT_LIST_HEAD(&bf_head);
2279 		if (list_is_last(&lastbf->list, fifo_list)) {
2280 			list_splice_tail_init(fifo_list, &bf_head);
2281 			INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2282 
2283 			if (!list_empty(&txq->axq_q)) {
2284 				struct list_head bf_q;
2285 
2286 				INIT_LIST_HEAD(&bf_q);
2287 				txq->axq_link = NULL;
2288 				list_splice_tail_init(&txq->axq_q, &bf_q);
2289 				ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2290 			}
2291 		} else {
2292 			lastbf->bf_stale = true;
2293 			if (bf != lastbf)
2294 				list_cut_position(&bf_head, fifo_list,
2295 						  lastbf->list.prev);
2296 		}
2297 
2298 		ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2299 		ath_txq_unlock_complete(sc, txq);
2300 	}
2301 }
2302 
2303 /*****************/
2304 /* Init, Cleanup */
2305 /*****************/
2306 
ath_txstatus_setup(struct ath_softc * sc,int size)2307 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2308 {
2309 	struct ath_descdma *dd = &sc->txsdma;
2310 	u8 txs_len = sc->sc_ah->caps.txs_len;
2311 
2312 	dd->dd_desc_len = size * txs_len;
2313 	dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2314 					  &dd->dd_desc_paddr, GFP_KERNEL);
2315 	if (!dd->dd_desc)
2316 		return -ENOMEM;
2317 
2318 	return 0;
2319 }
2320 
ath_tx_edma_init(struct ath_softc * sc)2321 static int ath_tx_edma_init(struct ath_softc *sc)
2322 {
2323 	int err;
2324 
2325 	err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2326 	if (!err)
2327 		ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2328 					  sc->txsdma.dd_desc_paddr,
2329 					  ATH_TXSTATUS_RING_SIZE);
2330 
2331 	return err;
2332 }
2333 
ath_tx_init(struct ath_softc * sc,int nbufs)2334 int ath_tx_init(struct ath_softc *sc, int nbufs)
2335 {
2336 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2337 	int error = 0;
2338 
2339 	spin_lock_init(&sc->tx.txbuflock);
2340 
2341 	error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2342 				  "tx", nbufs, 1, 1);
2343 	if (error != 0) {
2344 		ath_err(common,
2345 			"Failed to allocate tx descriptors: %d\n", error);
2346 		return error;
2347 	}
2348 
2349 	error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2350 				  "beacon", ATH_BCBUF, 1, 1);
2351 	if (error != 0) {
2352 		ath_err(common,
2353 			"Failed to allocate beacon descriptors: %d\n", error);
2354 		return error;
2355 	}
2356 
2357 	INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2358 
2359 	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2360 		error = ath_tx_edma_init(sc);
2361 
2362 	return error;
2363 }
2364 
ath_tx_node_init(struct ath_softc * sc,struct ath_node * an)2365 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2366 {
2367 	struct ath_atx_tid *tid;
2368 	struct ath_atx_ac *ac;
2369 	int tidno, acno;
2370 
2371 	for (tidno = 0, tid = &an->tid[tidno];
2372 	     tidno < IEEE80211_NUM_TIDS;
2373 	     tidno++, tid++) {
2374 		tid->an        = an;
2375 		tid->tidno     = tidno;
2376 		tid->seq_start = tid->seq_next = 0;
2377 		tid->baw_size  = WME_MAX_BA;
2378 		tid->baw_head  = tid->baw_tail = 0;
2379 		tid->sched     = false;
2380 		tid->paused    = false;
2381 		tid->active	   = false;
2382 		__skb_queue_head_init(&tid->buf_q);
2383 		acno = TID_TO_WME_AC(tidno);
2384 		tid->ac = &an->ac[acno];
2385 	}
2386 
2387 	for (acno = 0, ac = &an->ac[acno];
2388 	     acno < IEEE80211_NUM_ACS; acno++, ac++) {
2389 		ac->sched    = false;
2390 		ac->txq = sc->tx.txq_map[acno];
2391 		INIT_LIST_HEAD(&ac->tid_q);
2392 	}
2393 }
2394 
ath_tx_node_cleanup(struct ath_softc * sc,struct ath_node * an)2395 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2396 {
2397 	struct ath_atx_ac *ac;
2398 	struct ath_atx_tid *tid;
2399 	struct ath_txq *txq;
2400 	int tidno;
2401 
2402 	for (tidno = 0, tid = &an->tid[tidno];
2403 	     tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
2404 
2405 		ac = tid->ac;
2406 		txq = ac->txq;
2407 
2408 		ath_txq_lock(sc, txq);
2409 
2410 		if (tid->sched) {
2411 			list_del(&tid->list);
2412 			tid->sched = false;
2413 		}
2414 
2415 		if (ac->sched) {
2416 			list_del(&ac->list);
2417 			tid->ac->sched = false;
2418 		}
2419 
2420 		ath_tid_drain(sc, txq, tid);
2421 		tid->active = false;
2422 
2423 		ath_txq_unlock(sc, txq);
2424 	}
2425 }
2426