1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003, 2004 Ralf Baechle 7 * Copyright (C) 2004 Maciej W. Rozycki 8 */ 9 #ifndef __ASM_CPU_FEATURES_H 10 #define __ASM_CPU_FEATURES_H 11 12 #include <asm/cpu.h> 13 #include <asm/cpu-info.h> 14 #include <cpu-feature-overrides.h> 15 16 #ifndef current_cpu_type 17 #define current_cpu_type() current_cpu_data.cputype 18 #endif 19 20 /* 21 * SMP assumption: Options of CPU 0 are a superset of all processors. 22 * This is true for all known MIPS systems. 23 */ 24 #ifndef cpu_has_tlb 25 #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB) 26 #endif 27 #ifndef cpu_has_tlbinv 28 #define cpu_has_tlbinv (cpu_data[0].options & MIPS_CPU_TLBINV) 29 #endif 30 #ifndef cpu_has_tlbinv_full 31 #define cpu_has_tlbinv_full (cpu_data[0].options & MIPS_CPU_TLBINV_FULL) 32 #endif 33 #ifndef cpu_has_4kex 34 #define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX) 35 #endif 36 #ifndef cpu_has_3k_cache 37 #define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE) 38 #endif 39 #define cpu_has_6k_cache 0 40 #define cpu_has_8k_cache 0 41 #ifndef cpu_has_4k_cache 42 #define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE) 43 #endif 44 #ifndef cpu_has_tx39_cache 45 #define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) 46 #endif 47 #ifndef cpu_has_octeon_cache 48 #define cpu_has_octeon_cache 0 49 #endif 50 #ifndef cpu_has_fpu 51 #define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) 52 #define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) 53 #else 54 #define raw_cpu_has_fpu cpu_has_fpu 55 #endif 56 #ifndef cpu_has_32fpr 57 #define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR) 58 #endif 59 #ifndef cpu_has_counter 60 #define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER) 61 #endif 62 #ifndef cpu_has_watch 63 #define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH) 64 #endif 65 #ifndef cpu_has_divec 66 #define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC) 67 #endif 68 #ifndef cpu_has_vce 69 #define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE) 70 #endif 71 #ifndef cpu_has_cache_cdex_p 72 #define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P) 73 #endif 74 #ifndef cpu_has_cache_cdex_s 75 #define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S) 76 #endif 77 #ifndef cpu_has_prefetch 78 #ifdef CONFIG_CPU_MIPSR6 79 #define cpu_has_prefetch (0) 80 #else 81 #define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH) 82 #endif 83 #endif 84 #ifndef cpu_has_mcheck 85 #define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK) 86 #endif 87 #ifndef cpu_has_ejtag 88 #define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG) 89 #endif 90 #ifndef cpu_has_llsc 91 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) 92 #endif 93 #ifndef kernel_uses_llsc 94 #define kernel_uses_llsc cpu_has_llsc 95 #endif 96 #ifndef cpu_has_mips16 97 #define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16) 98 #endif 99 #ifndef cpu_has_mdmx 100 #define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX) 101 #endif 102 #ifndef cpu_has_mips3d 103 #define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D) 104 #endif 105 #ifndef cpu_has_smartmips 106 #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) 107 #endif 108 #ifndef cpu_has_rixi 109 #define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) 110 #endif 111 #ifndef cpu_has_himem 112 #define cpu_has_himem (cpu_data[0].options2 & MIPS_CPU_HIMEM) 113 #endif 114 #ifndef cpu_has_rixi_except 115 #define cpu_has_rixi_except (cpu_data[0].options & MIPS_CPU_RIXI_EXCEPT) 116 #endif 117 #ifndef cpu_has_mmips 118 # ifdef CONFIG_SYS_SUPPORTS_MICROMIPS 119 # define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS) 120 # else 121 # define cpu_has_mmips 0 122 # endif 123 #endif 124 #ifndef cpu_has_vtag_icache 125 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) 126 #endif 127 #ifndef cpu_has_vtag_dcache 128 #define cpu_has_vtag_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_VTAG) 129 #endif 130 #ifndef cpu_has_ic_aliases 131 #define cpu_has_ic_aliases (cpu_data[0].icache.flags & MIPS_CACHE_ALIASES) 132 #endif 133 #ifndef cpu_has_dc_aliases 134 #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES) 135 #endif 136 #ifndef cpu_has_ic_fills_f_dc 137 #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) 138 #endif 139 #ifndef cpu_has_pindexed_dcache 140 #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) 141 #endif 142 #ifndef cpu_has_local_ebase 143 #define cpu_has_local_ebase 1 144 #endif 145 #ifdef CONFIG_MIPS_CMP 146 #ifndef cpu_has_cm2 147 #define cpu_has_cm2 (cpu_data[0].options & MIPS_CPU_CM2) 148 #endif 149 #ifndef cpu_has_cm2_l2sync 150 #define cpu_has_cm2_l2sync (cpu_data[0].options & MIPS_CPU_CM2_L2SYNC) 151 #endif 152 #else 153 #define cpu_has_cm2 (0) 154 #define cpu_has_cm2_l2sync (0) 155 #endif 156 #ifndef cpu_has_maar 157 #define cpu_has_maar (cpu_data[0].options2 & MIPS_CPU_MAAR) 158 #endif 159 #ifndef cpu_has_fre 160 #ifdef CONFIG_MIPS_INCOMPATIBLE_ARCH_EMULATION 161 #define cpu_has_fre (cpu_data[0].options2 & MIPS_CPU_FRE) 162 #else 163 #define cpu_has_fre 0 164 #endif 165 #endif /* cpu_has_fre */ 166 #ifndef cpu_has_htw 167 #define cpu_has_htw (cpu_data[0].options2 & MIPS_CPU_HTW) 168 #endif 169 #ifndef cpu_has_l2c 170 #define cpu_has_l2c (cpu_data[0].options2 & MIPS_CPU_L2C) 171 #endif 172 #ifndef cpu_has_vcmt 173 #define cpu_has_vcmt (cpu_data[0].options2 & MIPS_CPU_VC) 174 #endif 175 176 /* 177 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors 178 * such as the R10000 have I-Caches that snoop local stores; the embedded ones 179 * don't. For maintaining I-cache coherency this means we need to flush the 180 * D-cache all the way back to whever the I-cache does refills from, so the 181 * I-cache has a chance to see the new data at all. Then we have to flush the 182 * I-cache also. 183 * Note we may have been rescheduled and may no longer be running on the CPU 184 * that did the store so we can't optimize this into only doing the flush on 185 * the local CPU. 186 */ 187 #ifndef cpu_icache_snoops_remote_store 188 #ifdef CONFIG_SMP 189 #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE) 190 #else 191 #define cpu_icache_snoops_remote_store 1 192 #endif 193 #endif 194 195 # define cpu_has_mips_1 (cpu_data[0].isa_level & MIPS_CPU_ISA_I) 196 #ifndef cpu_has_mips_2 197 # define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II) 198 #endif 199 #ifndef cpu_has_mips_3 200 # define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III) 201 #endif 202 #ifndef cpu_has_mips_4 203 # define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV) 204 #endif 205 #ifndef cpu_has_mips_5 206 # define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V) 207 #endif 208 # ifndef cpu_has_mips32r1 209 # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) 210 # endif 211 # ifndef cpu_has_mips32r2 212 # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) 213 # endif 214 # ifndef cpu_has_mips32r6 215 # define cpu_has_mips32r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6) 216 # endif 217 # ifndef cpu_has_mips64r1 218 # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) 219 # endif 220 # ifndef cpu_has_mips64r2 221 # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) 222 # endif 223 # ifndef cpu_has_mips64r6 224 # define cpu_has_mips64r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R6) 225 # endif 226 227 /* 228 * Shortcuts ... 229 */ 230 #define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6) 231 #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6) 232 #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) 233 #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) 234 #define cpu_has_mips_r6 (cpu_has_mips32r6 | cpu_has_mips64r6) 235 #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ 236 cpu_has_mips64r1 | cpu_has_mips64r2 | \ 237 cpu_has_mips32r6 | cpu_has_mips64r6) 238 239 #ifndef cpu_has_mips_r2_exec_hazard 240 #define cpu_has_mips_r2_exec_hazard (cpu_has_mips_r2 | cpu_has_mips_r6) 241 #endif 242 243 /* 244 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other 245 * pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and 246 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels 247 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. 248 */ 249 # ifndef cpu_has_clo_clz 250 # define cpu_has_clo_clz cpu_has_mips_r 251 # endif 252 253 #ifdef CONFIG_CPU_MIPSR6 254 255 #define cpu_has_dsp 0 256 #define cpu_has_dsp2 0 257 258 #else /* !CONFIG_CPU_MIPSR6 */ 259 260 #ifndef cpu_has_dsp 261 #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) 262 #endif 263 264 #ifndef cpu_has_dsp2 265 #define cpu_has_dsp2 (cpu_data[0].ases & MIPS_ASE_DSP2P) 266 #endif 267 268 #endif /* CONFIG_CPU_MIPSR6 */ 269 270 #ifndef cpu_has_mipsmt 271 #define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) 272 #endif 273 274 #ifndef cpu_has_userlocal 275 #define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI) 276 #endif 277 278 #ifndef cpu_has_segments 279 #define cpu_has_segments (cpu_data[0].options & MIPS_CPU_SEGMENTS) 280 #endif 281 282 #ifndef cpu_has_eva 283 #define cpu_has_eva (cpu_data[0].options & MIPS_CPU_EVA) 284 #endif 285 286 #ifdef CONFIG_32BIT 287 # ifndef cpu_has_nofpuex 288 # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) 289 # endif 290 # ifndef cpu_has_64bits 291 # define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 292 # endif 293 # ifndef cpu_has_64bit_zero_reg 294 # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 295 # endif 296 # ifndef cpu_has_64bit_gp_regs 297 # define cpu_has_64bit_gp_regs 0 298 # endif 299 # ifndef cpu_has_64bit_addresses 300 # define cpu_has_64bit_addresses 0 301 # endif 302 # ifndef cpu_vmbits 303 # define cpu_vmbits 31 304 # endif 305 #endif 306 307 #ifdef CONFIG_64BIT 308 # ifndef cpu_has_nofpuex 309 # define cpu_has_nofpuex 0 310 # endif 311 # ifndef cpu_has_64bits 312 # define cpu_has_64bits 1 313 # endif 314 # ifndef cpu_has_64bit_zero_reg 315 # define cpu_has_64bit_zero_reg 1 316 # endif 317 # ifndef cpu_has_64bit_gp_regs 318 # define cpu_has_64bit_gp_regs 1 319 # endif 320 # ifndef cpu_has_64bit_addresses 321 # define cpu_has_64bit_addresses 1 322 # endif 323 # ifndef cpu_vmbits 324 # define cpu_vmbits cpu_data[0].vmbits 325 # define __NEED_VMBITS_PROBE 326 # endif 327 #endif 328 329 #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) 330 # define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT) 331 #elif !defined(cpu_has_vint) 332 # define cpu_has_vint 0 333 #endif 334 335 #if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic) 336 # define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC) 337 #elif !defined(cpu_has_veic) 338 # define cpu_has_veic 0 339 #endif 340 341 #ifndef cpu_has_inclusive_pcaches 342 #define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES) 343 #endif 344 345 #ifndef cpu_has_cm3_inclusive_pcaches 346 #define cpu_has_cm3_inclusive_pcaches (cpu_data[0].options2 & MIPS_CPU_CM3_INCLUSIVE_CACHES) 347 #endif 348 349 #ifndef cpu_dcache_line_size 350 #define cpu_dcache_line_size() cpu_data[0].dcache.linesz 351 #endif 352 #ifndef cpu_icache_line_size 353 #define cpu_icache_line_size() cpu_data[0].icache.linesz 354 #endif 355 #ifndef cpu_scache_line_size 356 #define cpu_scache_line_size() cpu_data[0].scache.linesz 357 #endif 358 359 #ifndef cpu_hwrena_impl_bits 360 #define cpu_hwrena_impl_bits 0 361 #endif 362 363 #ifndef cpu_has_perf_cntr_intr_bit 364 #define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI) 365 #endif 366 367 #ifndef cpu_has_vz 368 #define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ) 369 #endif 370 371 #if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa) 372 # define cpu_has_msa (cpu_data[0].ases & MIPS_ASE_MSA) 373 #elif !defined(cpu_has_msa) 374 # define cpu_has_msa 0 375 #endif 376 377 #endif /* __ASM_CPU_FEATURES_H */ 378