1 /*
2 * TI DaVinci serial driver
3 *
4 * Copyright (C) 2006 Texas Instruments.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 *
20 */
21
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/serial_8250.h>
25 #include <linux/serial_reg.h>
26 #include <linux/platform_device.h>
27 #include <linux/delay.h>
28 #include <linux/clk.h>
29 #include <linux/io.h>
30
31 #include <mach/serial.h>
32 #include <mach/cputype.h>
33
serial_read_reg(struct plat_serial8250_port * up,int offset)34 static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
35 int offset)
36 {
37 offset <<= up->regshift;
38
39 WARN_ONCE(!up->membase, "unmapped read: uart[%d]\n", offset);
40
41 return (unsigned int)__raw_readl(up->membase + offset);
42 }
43
serial_write_reg(struct plat_serial8250_port * p,int offset,int value)44 static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
45 int value)
46 {
47 offset <<= p->regshift;
48
49 WARN_ONCE(!p->membase, "unmapped write: uart[%d]\n", offset);
50
51 __raw_writel(value, p->membase + offset);
52 }
53
davinci_serial_reset(struct plat_serial8250_port * p)54 static void __init davinci_serial_reset(struct plat_serial8250_port *p)
55 {
56 unsigned int pwremu = 0;
57
58 serial_write_reg(p, UART_IER, 0); /* disable all interrupts */
59
60 /* reset both transmitter and receiver: bits 14,13 = UTRST, URRST */
61 serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu);
62 mdelay(10);
63
64 pwremu |= (0x3 << 13);
65 pwremu |= 0x1;
66 serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu);
67
68 if (cpu_is_davinci_dm646x())
69 serial_write_reg(p, UART_DM646X_SCR,
70 UART_DM646X_SCR_TX_WATERMARK);
71 }
72
73 /* Enable UART clock and obtain its rate */
davinci_serial_setup_clk(unsigned instance,unsigned int * rate)74 int __init davinci_serial_setup_clk(unsigned instance, unsigned int *rate)
75 {
76 char name[16];
77 struct clk *clk;
78 struct davinci_soc_info *soc_info = &davinci_soc_info;
79 struct device *dev = &soc_info->serial_dev->dev;
80
81 sprintf(name, "uart%d", instance);
82 clk = clk_get(dev, name);
83 if (IS_ERR(clk)) {
84 pr_err("%s:%d: failed to get UART%d clock\n",
85 __func__, __LINE__, instance);
86 return PTR_ERR(clk);
87 }
88
89 clk_prepare_enable(clk);
90
91 if (rate)
92 *rate = clk_get_rate(clk);
93
94 return 0;
95 }
96
davinci_serial_init(struct davinci_uart_config * info)97 int __init davinci_serial_init(struct davinci_uart_config *info)
98 {
99 int i, ret;
100 struct davinci_soc_info *soc_info = &davinci_soc_info;
101 struct device *dev = &soc_info->serial_dev->dev;
102 struct plat_serial8250_port *p = dev->platform_data;
103
104 /*
105 * Make sure the serial ports are muxed on at this point.
106 * You have to mux them off in device drivers later on if not needed.
107 */
108 for (i = 0; p->flags; i++, p++) {
109 if (!(info->enabled_uarts & (1 << i)))
110 continue;
111
112 ret = davinci_serial_setup_clk(i, &p->uartclk);
113 if (ret)
114 continue;
115
116 if (!p->membase && p->mapbase) {
117 p->membase = ioremap(p->mapbase, SZ_4K);
118
119 if (p->membase)
120 p->flags &= ~UPF_IOREMAP;
121 else
122 pr_err("uart regs ioremap failed\n");
123 }
124
125 if (p->membase && p->type != PORT_AR7)
126 davinci_serial_reset(p);
127 }
128
129 return platform_device_register(soc_info->serial_dev);
130 }
131