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1 /*
2  * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3  * Author: Joerg Roedel <joerg.roedel@amd.com>
4  *         Leo Duran <leo.duran@amd.com>
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of the GNU General Public License version 2 as published
8  * by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
18  */
19 
20 #ifndef _ASM_X86_AMD_IOMMU_TYPES_H
21 #define _ASM_X86_AMD_IOMMU_TYPES_H
22 
23 #include <linux/types.h>
24 #include <linux/mutex.h>
25 #include <linux/list.h>
26 #include <linux/spinlock.h>
27 #include <linux/pci.h>
28 
29 /*
30  * Maximum number of IOMMUs supported
31  */
32 #define MAX_IOMMUS	32
33 
34 /*
35  * some size calculation constants
36  */
37 #define DEV_TABLE_ENTRY_SIZE		32
38 #define ALIAS_TABLE_ENTRY_SIZE		2
39 #define RLOOKUP_TABLE_ENTRY_SIZE	(sizeof(void *))
40 
41 /* Length of the MMIO region for the AMD IOMMU */
42 #define MMIO_REGION_LENGTH       0x4000
43 
44 /* Capability offsets used by the driver */
45 #define MMIO_CAP_HDR_OFFSET	0x00
46 #define MMIO_RANGE_OFFSET	0x0c
47 #define MMIO_MISC_OFFSET	0x10
48 
49 /* Masks, shifts and macros to parse the device range capability */
50 #define MMIO_RANGE_LD_MASK	0xff000000
51 #define MMIO_RANGE_FD_MASK	0x00ff0000
52 #define MMIO_RANGE_BUS_MASK	0x0000ff00
53 #define MMIO_RANGE_LD_SHIFT	24
54 #define MMIO_RANGE_FD_SHIFT	16
55 #define MMIO_RANGE_BUS_SHIFT	8
56 #define MMIO_GET_LD(x)  (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
57 #define MMIO_GET_FD(x)  (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
58 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
59 #define MMIO_MSI_NUM(x)	((x) & 0x1f)
60 
61 /* Flag masks for the AMD IOMMU exclusion range */
62 #define MMIO_EXCL_ENABLE_MASK 0x01ULL
63 #define MMIO_EXCL_ALLOW_MASK  0x02ULL
64 
65 /* Used offsets into the MMIO space */
66 #define MMIO_DEV_TABLE_OFFSET   0x0000
67 #define MMIO_CMD_BUF_OFFSET     0x0008
68 #define MMIO_EVT_BUF_OFFSET     0x0010
69 #define MMIO_CONTROL_OFFSET     0x0018
70 #define MMIO_EXCL_BASE_OFFSET   0x0020
71 #define MMIO_EXCL_LIMIT_OFFSET  0x0028
72 #define MMIO_EXT_FEATURES	0x0030
73 #define MMIO_PPR_LOG_OFFSET	0x0038
74 #define MMIO_CMD_HEAD_OFFSET	0x2000
75 #define MMIO_CMD_TAIL_OFFSET	0x2008
76 #define MMIO_EVT_HEAD_OFFSET	0x2010
77 #define MMIO_EVT_TAIL_OFFSET	0x2018
78 #define MMIO_STATUS_OFFSET	0x2020
79 #define MMIO_PPR_HEAD_OFFSET	0x2030
80 #define MMIO_PPR_TAIL_OFFSET	0x2038
81 
82 
83 /* Extended Feature Bits */
84 #define FEATURE_PREFETCH	(1ULL<<0)
85 #define FEATURE_PPR		(1ULL<<1)
86 #define FEATURE_X2APIC		(1ULL<<2)
87 #define FEATURE_NX		(1ULL<<3)
88 #define FEATURE_GT		(1ULL<<4)
89 #define FEATURE_IA		(1ULL<<6)
90 #define FEATURE_GA		(1ULL<<7)
91 #define FEATURE_HE		(1ULL<<8)
92 #define FEATURE_PC		(1ULL<<9)
93 
94 #define FEATURE_PASID_SHIFT	32
95 #define FEATURE_PASID_MASK	(0x1fULL << FEATURE_PASID_SHIFT)
96 
97 #define FEATURE_GLXVAL_SHIFT	14
98 #define FEATURE_GLXVAL_MASK	(0x03ULL << FEATURE_GLXVAL_SHIFT)
99 
100 #define PASID_MASK		0x000fffff
101 
102 /* MMIO status bits */
103 #define MMIO_STATUS_EVT_INT_MASK	(1 << 1)
104 #define MMIO_STATUS_COM_WAIT_INT_MASK	(1 << 2)
105 #define MMIO_STATUS_PPR_INT_MASK	(1 << 6)
106 
107 /* event logging constants */
108 #define EVENT_ENTRY_SIZE	0x10
109 #define EVENT_TYPE_SHIFT	28
110 #define EVENT_TYPE_MASK		0xf
111 #define EVENT_TYPE_ILL_DEV	0x1
112 #define EVENT_TYPE_IO_FAULT	0x2
113 #define EVENT_TYPE_DEV_TAB_ERR	0x3
114 #define EVENT_TYPE_PAGE_TAB_ERR	0x4
115 #define EVENT_TYPE_ILL_CMD	0x5
116 #define EVENT_TYPE_CMD_HARD_ERR	0x6
117 #define EVENT_TYPE_IOTLB_INV_TO	0x7
118 #define EVENT_TYPE_INV_DEV_REQ	0x8
119 #define EVENT_DEVID_MASK	0xffff
120 #define EVENT_DEVID_SHIFT	0
121 #define EVENT_DOMID_MASK	0xffff
122 #define EVENT_DOMID_SHIFT	0
123 #define EVENT_FLAGS_MASK	0xfff
124 #define EVENT_FLAGS_SHIFT	0x10
125 
126 /* feature control bits */
127 #define CONTROL_IOMMU_EN        0x00ULL
128 #define CONTROL_HT_TUN_EN       0x01ULL
129 #define CONTROL_EVT_LOG_EN      0x02ULL
130 #define CONTROL_EVT_INT_EN      0x03ULL
131 #define CONTROL_COMWAIT_EN      0x04ULL
132 #define CONTROL_INV_TIMEOUT	0x05ULL
133 #define CONTROL_PASSPW_EN       0x08ULL
134 #define CONTROL_RESPASSPW_EN    0x09ULL
135 #define CONTROL_COHERENT_EN     0x0aULL
136 #define CONTROL_ISOC_EN         0x0bULL
137 #define CONTROL_CMDBUF_EN       0x0cULL
138 #define CONTROL_PPFLOG_EN       0x0dULL
139 #define CONTROL_PPFINT_EN       0x0eULL
140 #define CONTROL_PPR_EN          0x0fULL
141 #define CONTROL_GT_EN           0x10ULL
142 
143 #define CTRL_INV_TO_MASK	(7 << CONTROL_INV_TIMEOUT)
144 #define CTRL_INV_TO_NONE	0
145 #define CTRL_INV_TO_1MS		1
146 #define CTRL_INV_TO_10MS	2
147 #define CTRL_INV_TO_100MS	3
148 #define CTRL_INV_TO_1S		4
149 #define CTRL_INV_TO_10S		5
150 #define CTRL_INV_TO_100S	6
151 
152 /* command specific defines */
153 #define CMD_COMPL_WAIT          0x01
154 #define CMD_INV_DEV_ENTRY       0x02
155 #define CMD_INV_IOMMU_PAGES	0x03
156 #define CMD_INV_IOTLB_PAGES	0x04
157 #define CMD_INV_IRT		0x05
158 #define CMD_COMPLETE_PPR	0x07
159 #define CMD_INV_ALL		0x08
160 
161 #define CMD_COMPL_WAIT_STORE_MASK	0x01
162 #define CMD_COMPL_WAIT_INT_MASK		0x02
163 #define CMD_INV_IOMMU_PAGES_SIZE_MASK	0x01
164 #define CMD_INV_IOMMU_PAGES_PDE_MASK	0x02
165 #define CMD_INV_IOMMU_PAGES_GN_MASK	0x04
166 
167 #define PPR_STATUS_MASK			0xf
168 #define PPR_STATUS_SHIFT		12
169 
170 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS	0x7fffffffffffffffULL
171 
172 /* macros and definitions for device table entries */
173 #define DEV_ENTRY_VALID         0x00
174 #define DEV_ENTRY_TRANSLATION   0x01
175 #define DEV_ENTRY_IR            0x3d
176 #define DEV_ENTRY_IW            0x3e
177 #define DEV_ENTRY_NO_PAGE_FAULT	0x62
178 #define DEV_ENTRY_EX            0x67
179 #define DEV_ENTRY_SYSMGT1       0x68
180 #define DEV_ENTRY_SYSMGT2       0x69
181 #define DEV_ENTRY_IRQ_TBL_EN	0x80
182 #define DEV_ENTRY_INIT_PASS     0xb8
183 #define DEV_ENTRY_EINT_PASS     0xb9
184 #define DEV_ENTRY_NMI_PASS      0xba
185 #define DEV_ENTRY_LINT0_PASS    0xbe
186 #define DEV_ENTRY_LINT1_PASS    0xbf
187 #define DEV_ENTRY_MODE_MASK	0x07
188 #define DEV_ENTRY_MODE_SHIFT	0x09
189 
190 #define MAX_DEV_TABLE_ENTRIES	0xffff
191 
192 /* constants to configure the command buffer */
193 #define CMD_BUFFER_SIZE    8192
194 #define CMD_BUFFER_UNINITIALIZED 1
195 #define CMD_BUFFER_ENTRIES 512
196 #define MMIO_CMD_SIZE_SHIFT 56
197 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
198 
199 /* constants for event buffer handling */
200 #define EVT_BUFFER_SIZE		8192 /* 512 entries */
201 #define EVT_LEN_MASK		(0x9ULL << 56)
202 
203 /* Constants for PPR Log handling */
204 #define PPR_LOG_ENTRIES		512
205 #define PPR_LOG_SIZE_SHIFT	56
206 #define PPR_LOG_SIZE_512	(0x9ULL << PPR_LOG_SIZE_SHIFT)
207 #define PPR_ENTRY_SIZE		16
208 #define PPR_LOG_SIZE		(PPR_ENTRY_SIZE * PPR_LOG_ENTRIES)
209 
210 #define PPR_REQ_TYPE(x)		(((x) >> 60) & 0xfULL)
211 #define PPR_FLAGS(x)		(((x) >> 48) & 0xfffULL)
212 #define PPR_DEVID(x)		((x) & 0xffffULL)
213 #define PPR_TAG(x)		(((x) >> 32) & 0x3ffULL)
214 #define PPR_PASID1(x)		(((x) >> 16) & 0xffffULL)
215 #define PPR_PASID2(x)		(((x) >> 42) & 0xfULL)
216 #define PPR_PASID(x)		((PPR_PASID2(x) << 16) | PPR_PASID1(x))
217 
218 #define PPR_REQ_FAULT		0x01
219 
220 #define PAGE_MODE_NONE    0x00
221 #define PAGE_MODE_1_LEVEL 0x01
222 #define PAGE_MODE_2_LEVEL 0x02
223 #define PAGE_MODE_3_LEVEL 0x03
224 #define PAGE_MODE_4_LEVEL 0x04
225 #define PAGE_MODE_5_LEVEL 0x05
226 #define PAGE_MODE_6_LEVEL 0x06
227 
228 #define PM_LEVEL_SHIFT(x)	(12 + ((x) * 9))
229 #define PM_LEVEL_SIZE(x)	(((x) < 6) ? \
230 				  ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \
231 				   (0xffffffffffffffffULL))
232 #define PM_LEVEL_INDEX(x, a)	(((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL)
233 #define PM_LEVEL_ENC(x)		(((x) << 9) & 0xe00ULL)
234 #define PM_LEVEL_PDE(x, a)	((a) | PM_LEVEL_ENC((x)) | \
235 				 IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
236 #define PM_PTE_LEVEL(pte)	(((pte) >> 9) & 0x7ULL)
237 
238 #define PM_MAP_4k		0
239 #define PM_ADDR_MASK		0x000ffffffffff000ULL
240 #define PM_MAP_MASK(lvl)	(PM_ADDR_MASK & \
241 				(~((1ULL << (12 + ((lvl) * 9))) - 1)))
242 #define PM_ALIGNED(lvl, addr)	((PM_MAP_MASK(lvl) & (addr)) == (addr))
243 
244 /*
245  * Returns the page table level to use for a given page size
246  * Pagesize is expected to be a power-of-two
247  */
248 #define PAGE_SIZE_LEVEL(pagesize) \
249 		((__ffs(pagesize) - 12) / 9)
250 /*
251  * Returns the number of ptes to use for a given page size
252  * Pagesize is expected to be a power-of-two
253  */
254 #define PAGE_SIZE_PTE_COUNT(pagesize) \
255 		(1ULL << ((__ffs(pagesize) - 12) % 9))
256 
257 /*
258  * Aligns a given io-virtual address to a given page size
259  * Pagesize is expected to be a power-of-two
260  */
261 #define PAGE_SIZE_ALIGN(address, pagesize) \
262 		((address) & ~((pagesize) - 1))
263 /*
264  * Creates an IOMMU PTE for an address and a given pagesize
265  * The PTE has no permission bits set
266  * Pagesize is expected to be a power-of-two larger than 4096
267  */
268 #define PAGE_SIZE_PTE(address, pagesize)		\
269 		(((address) | ((pagesize) - 1)) &	\
270 		 (~(pagesize >> 1)) & PM_ADDR_MASK)
271 
272 /*
273  * Takes a PTE value with mode=0x07 and returns the page size it maps
274  */
275 #define PTE_PAGE_SIZE(pte) \
276 	(1ULL << (1 + ffz(((pte) | 0xfffULL))))
277 
278 #define IOMMU_PTE_P  (1ULL << 0)
279 #define IOMMU_PTE_TV (1ULL << 1)
280 #define IOMMU_PTE_U  (1ULL << 59)
281 #define IOMMU_PTE_FC (1ULL << 60)
282 #define IOMMU_PTE_IR (1ULL << 61)
283 #define IOMMU_PTE_IW (1ULL << 62)
284 
285 #define DTE_FLAG_IOTLB	(0x01UL << 32)
286 #define DTE_FLAG_GV	(0x01ULL << 55)
287 #define DTE_GLX_SHIFT	(56)
288 #define DTE_GLX_MASK	(3)
289 
290 #define DTE_GCR3_VAL_A(x)	(((x) >> 12) & 0x00007ULL)
291 #define DTE_GCR3_VAL_B(x)	(((x) >> 15) & 0x0ffffULL)
292 #define DTE_GCR3_VAL_C(x)	(((x) >> 31) & 0xfffffULL)
293 
294 #define DTE_GCR3_INDEX_A	0
295 #define DTE_GCR3_INDEX_B	1
296 #define DTE_GCR3_INDEX_C	1
297 
298 #define DTE_GCR3_SHIFT_A	58
299 #define DTE_GCR3_SHIFT_B	16
300 #define DTE_GCR3_SHIFT_C	43
301 
302 #define GCR3_VALID		0x01ULL
303 
304 #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
305 #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
306 #define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
307 #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
308 
309 #define IOMMU_PROT_MASK 0x03
310 #define IOMMU_PROT_IR 0x01
311 #define IOMMU_PROT_IW 0x02
312 
313 /* IOMMU capabilities */
314 #define IOMMU_CAP_IOTLB   24
315 #define IOMMU_CAP_NPCACHE 26
316 #define IOMMU_CAP_EFR     27
317 
318 #define MAX_DOMAIN_ID 65536
319 
320 /* Protection domain flags */
321 #define PD_DMA_OPS_MASK		(1UL << 0) /* domain used for dma_ops */
322 #define PD_DEFAULT_MASK		(1UL << 1) /* domain is a default dma_ops
323 					      domain for an IOMMU */
324 #define PD_PASSTHROUGH_MASK	(1UL << 2) /* domain has no page
325 					      translation */
326 #define PD_IOMMUV2_MASK		(1UL << 3) /* domain has gcr3 table */
327 
328 extern bool amd_iommu_dump;
329 #define DUMP_printk(format, arg...)					\
330 	do {								\
331 		if (amd_iommu_dump)						\
332 			printk(KERN_INFO "AMD-Vi: " format, ## arg);	\
333 	} while(0);
334 
335 /* global flag if IOMMUs cache non-present entries */
336 extern bool amd_iommu_np_cache;
337 /* Only true if all IOMMUs support device IOTLBs */
338 extern bool amd_iommu_iotlb_sup;
339 
340 #define MAX_IRQS_PER_TABLE	256
341 #define IRQ_TABLE_ALIGNMENT	128
342 
343 struct irq_remap_table {
344 	spinlock_t lock;
345 	unsigned min_index;
346 	u32 *table;
347 };
348 
349 extern struct irq_remap_table **irq_lookup_table;
350 
351 /* Interrupt remapping feature used? */
352 extern bool amd_iommu_irq_remap;
353 
354 /* kmem_cache to get tables with 128 byte alignement */
355 extern struct kmem_cache *amd_iommu_irq_cache;
356 
357 /*
358  * Make iterating over all IOMMUs easier
359  */
360 #define for_each_iommu(iommu) \
361 	list_for_each_entry((iommu), &amd_iommu_list, list)
362 #define for_each_iommu_safe(iommu, next) \
363 	list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
364 
365 #define APERTURE_RANGE_SHIFT	27	/* 128 MB */
366 #define APERTURE_RANGE_SIZE	(1ULL << APERTURE_RANGE_SHIFT)
367 #define APERTURE_RANGE_PAGES	(APERTURE_RANGE_SIZE >> PAGE_SHIFT)
368 #define APERTURE_MAX_RANGES	32	/* allows 4GB of DMA address space */
369 #define APERTURE_RANGE_INDEX(a)	((a) >> APERTURE_RANGE_SHIFT)
370 #define APERTURE_PAGE_INDEX(a)	(((a) >> 21) & 0x3fULL)
371 
372 
373 /*
374  * This struct is used to pass information about
375  * incoming PPR faults around.
376  */
377 struct amd_iommu_fault {
378 	u64 address;    /* IO virtual address of the fault*/
379 	u32 pasid;      /* Address space identifier */
380 	u16 device_id;  /* Originating PCI device id */
381 	u16 tag;        /* PPR tag */
382 	u16 flags;      /* Fault flags */
383 
384 };
385 
386 #define PPR_FAULT_EXEC	(1 << 1)
387 #define PPR_FAULT_READ  (1 << 2)
388 #define PPR_FAULT_WRITE (1 << 5)
389 #define PPR_FAULT_USER  (1 << 6)
390 #define PPR_FAULT_RSVD  (1 << 7)
391 #define PPR_FAULT_GN    (1 << 8)
392 
393 struct iommu_domain;
394 
395 /*
396  * This structure contains generic data for  IOMMU protection domains
397  * independent of their use.
398  */
399 struct protection_domain {
400 	struct list_head list;  /* for list of all protection domains */
401 	struct list_head dev_list; /* List of all devices in this domain */
402 	spinlock_t lock;	/* mostly used to lock the page table*/
403 	struct mutex api_lock;	/* protect page tables in the iommu-api path */
404 	u16 id;			/* the domain id written to the device table */
405 	int mode;		/* paging mode (0-6 levels) */
406 	u64 *pt_root;		/* page table root pointer */
407 	int glx;		/* Number of levels for GCR3 table */
408 	u64 *gcr3_tbl;		/* Guest CR3 table */
409 	unsigned long flags;	/* flags to find out type of domain */
410 	bool updated;		/* complete domain flush required */
411 	unsigned dev_cnt;	/* devices assigned to this domain */
412 	unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */
413 	void *priv;		/* private data */
414 	struct iommu_domain *iommu_domain; /* Pointer to generic
415 					      domain structure */
416 
417 };
418 
419 /*
420  * This struct contains device specific data for the IOMMU
421  */
422 struct iommu_dev_data {
423 	struct list_head list;		  /* For domain->dev_list */
424 	struct list_head dev_data_list;	  /* For global dev_data_list */
425 	struct iommu_dev_data *alias_data;/* The alias dev_data */
426 	struct protection_domain *domain; /* Domain the device is bound to */
427 	atomic_t bind;			  /* Domain attach reference count */
428 	struct iommu_group *group;	  /* IOMMU group for virtual aliases */
429 	u16 devid;			  /* PCI Device ID */
430 	bool iommu_v2;			  /* Device can make use of IOMMUv2 */
431 	bool passthrough;		  /* Default for device is pt_domain */
432 	struct {
433 		bool enabled;
434 		int qdep;
435 	} ats;				  /* ATS state */
436 	bool pri_tlp;			  /* PASID TLB required for
437 					     PPR completions */
438 	u32 errata;			  /* Bitmap for errata to apply */
439 };
440 
441 /*
442  * For dynamic growth the aperture size is split into ranges of 128MB of
443  * DMA address space each. This struct represents one such range.
444  */
445 struct aperture_range {
446 
447 	/* address allocation bitmap */
448 	unsigned long *bitmap;
449 
450 	/*
451 	 * Array of PTE pages for the aperture. In this array we save all the
452 	 * leaf pages of the domain page table used for the aperture. This way
453 	 * we don't need to walk the page table to find a specific PTE. We can
454 	 * just calculate its address in constant time.
455 	 */
456 	u64 *pte_pages[64];
457 
458 	unsigned long offset;
459 };
460 
461 /*
462  * Data container for a dma_ops specific protection domain
463  */
464 struct dma_ops_domain {
465 	struct list_head list;
466 
467 	/* generic protection domain information */
468 	struct protection_domain domain;
469 
470 	/* size of the aperture for the mappings */
471 	unsigned long aperture_size;
472 
473 	/* address we start to search for free addresses */
474 	unsigned long next_address;
475 
476 	/* address space relevant data */
477 	struct aperture_range *aperture[APERTURE_MAX_RANGES];
478 
479 	/* This will be set to true when TLB needs to be flushed */
480 	bool need_flush;
481 
482 	/*
483 	 * if this is a preallocated domain, keep the device for which it was
484 	 * preallocated in this variable
485 	 */
486 	u16 target_dev;
487 };
488 
489 /*
490  * Structure where we save information about one hardware AMD IOMMU in the
491  * system.
492  */
493 struct amd_iommu {
494 	struct list_head list;
495 
496 	/* Index within the IOMMU array */
497 	int index;
498 
499 	/* locks the accesses to the hardware */
500 	spinlock_t lock;
501 
502 	/* Pointer to PCI device of this IOMMU */
503 	struct pci_dev *dev;
504 
505 	/* Cache pdev to root device for resume quirks */
506 	struct pci_dev *root_pdev;
507 
508 	/* physical address of MMIO space */
509 	u64 mmio_phys;
510 	/* virtual address of MMIO space */
511 	u8 __iomem *mmio_base;
512 
513 	/* capabilities of that IOMMU read from ACPI */
514 	u32 cap;
515 
516 	/* flags read from acpi table */
517 	u8 acpi_flags;
518 
519 	/* Extended features */
520 	u64 features;
521 
522 	/* IOMMUv2 */
523 	bool is_iommu_v2;
524 
525 	/* PCI device id of the IOMMU device */
526 	u16 devid;
527 
528 	/*
529 	 * Capability pointer. There could be more than one IOMMU per PCI
530 	 * device function if there are more than one AMD IOMMU capability
531 	 * pointers.
532 	 */
533 	u16 cap_ptr;
534 
535 	/* pci domain of this IOMMU */
536 	u16 pci_seg;
537 
538 	/* first device this IOMMU handles. read from PCI */
539 	u16 first_device;
540 	/* last device this IOMMU handles. read from PCI */
541 	u16 last_device;
542 
543 	/* start of exclusion range of that IOMMU */
544 	u64 exclusion_start;
545 	/* length of exclusion range of that IOMMU */
546 	u64 exclusion_length;
547 
548 	/* command buffer virtual address */
549 	u8 *cmd_buf;
550 	/* size of command buffer */
551 	u32 cmd_buf_size;
552 
553 	/* size of event buffer */
554 	u32 evt_buf_size;
555 	/* event buffer virtual address */
556 	u8 *evt_buf;
557 
558 	/* Base of the PPR log, if present */
559 	u8 *ppr_log;
560 
561 	/* true if interrupts for this IOMMU are already enabled */
562 	bool int_enabled;
563 
564 	/* if one, we need to send a completion wait command */
565 	bool need_sync;
566 
567 	/* default dma_ops domain for that IOMMU */
568 	struct dma_ops_domain *default_dom;
569 
570 	/*
571 	 * We can't rely on the BIOS to restore all values on reinit, so we
572 	 * need to stash them
573 	 */
574 
575 	/* The iommu BAR */
576 	u32 stored_addr_lo;
577 	u32 stored_addr_hi;
578 
579 	/*
580 	 * Each iommu has 6 l1s, each of which is documented as having 0x12
581 	 * registers
582 	 */
583 	u32 stored_l1[6][0x12];
584 
585 	/* The l2 indirect registers */
586 	u32 stored_l2[0x83];
587 };
588 
589 struct devid_map {
590 	struct list_head list;
591 	u8 id;
592 	u16 devid;
593 	bool cmd_line;
594 };
595 
596 /* Map HPET and IOAPIC ids to the devid used by the IOMMU */
597 extern struct list_head ioapic_map;
598 extern struct list_head hpet_map;
599 
600 /*
601  * List with all IOMMUs in the system. This list is not locked because it is
602  * only written and read at driver initialization or suspend time
603  */
604 extern struct list_head amd_iommu_list;
605 
606 /*
607  * Array with pointers to each IOMMU struct
608  * The indices are referenced in the protection domains
609  */
610 extern struct amd_iommu *amd_iommus[MAX_IOMMUS];
611 
612 /* Number of IOMMUs present in the system */
613 extern int amd_iommus_present;
614 
615 /*
616  * Declarations for the global list of all protection domains
617  */
618 extern spinlock_t amd_iommu_pd_lock;
619 extern struct list_head amd_iommu_pd_list;
620 
621 /*
622  * Structure defining one entry in the device table
623  */
624 struct dev_table_entry {
625 	u64 data[4];
626 };
627 
628 /*
629  * One entry for unity mappings parsed out of the ACPI table.
630  */
631 struct unity_map_entry {
632 	struct list_head list;
633 
634 	/* starting device id this entry is used for (including) */
635 	u16 devid_start;
636 	/* end device id this entry is used for (including) */
637 	u16 devid_end;
638 
639 	/* start address to unity map (including) */
640 	u64 address_start;
641 	/* end address to unity map (including) */
642 	u64 address_end;
643 
644 	/* required protection */
645 	int prot;
646 };
647 
648 /*
649  * List of all unity mappings. It is not locked because as runtime it is only
650  * read. It is created at ACPI table parsing time.
651  */
652 extern struct list_head amd_iommu_unity_map;
653 
654 /*
655  * Data structures for device handling
656  */
657 
658 /*
659  * Device table used by hardware. Read and write accesses by software are
660  * locked with the amd_iommu_pd_table lock.
661  */
662 extern struct dev_table_entry *amd_iommu_dev_table;
663 
664 /*
665  * Alias table to find requestor ids to device ids. Not locked because only
666  * read on runtime.
667  */
668 extern u16 *amd_iommu_alias_table;
669 
670 /*
671  * Reverse lookup table to find the IOMMU which translates a specific device.
672  */
673 extern struct amd_iommu **amd_iommu_rlookup_table;
674 
675 /* size of the dma_ops aperture as power of 2 */
676 extern unsigned amd_iommu_aperture_order;
677 
678 /* largest PCI device id we expect translation requests for */
679 extern u16 amd_iommu_last_bdf;
680 
681 /* allocation bitmap for domain ids */
682 extern unsigned long *amd_iommu_pd_alloc_bitmap;
683 
684 /*
685  * If true, the addresses will be flushed on unmap time, not when
686  * they are reused
687  */
688 extern u32 amd_iommu_unmap_flush;
689 
690 /* Smallest number of PASIDs supported by any IOMMU in the system */
691 extern u32 amd_iommu_max_pasids;
692 
693 extern bool amd_iommu_v2_present;
694 
695 extern bool amd_iommu_force_isolation;
696 
697 /* Max levels of glxval supported */
698 extern int amd_iommu_max_glx_val;
699 
700 /*
701  * This function flushes all internal caches of
702  * the IOMMU used by this driver.
703  */
704 extern void iommu_flush_all_caches(struct amd_iommu *iommu);
705 
get_ioapic_devid(int id)706 static inline int get_ioapic_devid(int id)
707 {
708 	struct devid_map *entry;
709 
710 	list_for_each_entry(entry, &ioapic_map, list) {
711 		if (entry->id == id)
712 			return entry->devid;
713 	}
714 
715 	return -EINVAL;
716 }
717 
get_hpet_devid(int id)718 static inline int get_hpet_devid(int id)
719 {
720 	struct devid_map *entry;
721 
722 	list_for_each_entry(entry, &hpet_map, list) {
723 		if (entry->id == id)
724 			return entry->devid;
725 	}
726 
727 	return -EINVAL;
728 }
729 
730 #ifdef CONFIG_AMD_IOMMU_STATS
731 
732 struct __iommu_counter {
733 	char *name;
734 	struct dentry *dent;
735 	u64 value;
736 };
737 
738 #define DECLARE_STATS_COUNTER(nm) \
739 	static struct __iommu_counter nm = {	\
740 		.name = #nm,			\
741 	}
742 
743 #define INC_STATS_COUNTER(name)		name.value += 1
744 #define ADD_STATS_COUNTER(name, x)	name.value += (x)
745 #define SUB_STATS_COUNTER(name, x)	name.value -= (x)
746 
747 #else /* CONFIG_AMD_IOMMU_STATS */
748 
749 #define DECLARE_STATS_COUNTER(name)
750 #define INC_STATS_COUNTER(name)
751 #define ADD_STATS_COUNTER(name, x)
752 #define SUB_STATS_COUNTER(name, x)
753 
754 #endif /* CONFIG_AMD_IOMMU_STATS */
755 
756 #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */
757