1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef ATH9K_H
18 #define ATH9K_H
19
20 #include <linux/etherdevice.h>
21 #include <linux/device.h>
22 #include <linux/interrupt.h>
23 #include <linux/leds.h>
24 #include <linux/completion.h>
25
26 #include "debug.h"
27 #include "common.h"
28 #include "mci.h"
29 #include "dfs.h"
30
31 /*
32 * Header for the ath9k.ko driver core *only* -- hw code nor any other driver
33 * should rely on this file or its contents.
34 */
35
36 struct ath_node;
37
38 /* Macro to expand scalars to 64-bit objects */
39
40 #define ito64(x) (sizeof(x) == 1) ? \
41 (((unsigned long long int)(x)) & (0xff)) : \
42 (sizeof(x) == 2) ? \
43 (((unsigned long long int)(x)) & 0xffff) : \
44 ((sizeof(x) == 4) ? \
45 (((unsigned long long int)(x)) & 0xffffffff) : \
46 (unsigned long long int)(x))
47
48 /* increment with wrap-around */
49 #define INCR(_l, _sz) do { \
50 (_l)++; \
51 (_l) &= ((_sz) - 1); \
52 } while (0)
53
54 /* decrement with wrap-around */
55 #define DECR(_l, _sz) do { \
56 (_l)--; \
57 (_l) &= ((_sz) - 1); \
58 } while (0)
59
60 #define TSF_TO_TU(_h,_l) \
61 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
62
63 #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
64
65 struct ath_config {
66 u16 txpowlimit;
67 u8 cabqReadytime;
68 };
69
70 /*************************/
71 /* Descriptor Management */
72 /*************************/
73
74 #define ATH_TXBUF_RESET(_bf) do { \
75 (_bf)->bf_stale = false; \
76 (_bf)->bf_lastbf = NULL; \
77 (_bf)->bf_next = NULL; \
78 memset(&((_bf)->bf_state), 0, \
79 sizeof(struct ath_buf_state)); \
80 } while (0)
81
82 #define ATH_RXBUF_RESET(_bf) do { \
83 (_bf)->bf_stale = false; \
84 } while (0)
85
86 /**
87 * enum buffer_type - Buffer type flags
88 *
89 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
90 * @BUF_AGGR: Indicates whether the buffer can be aggregated
91 * (used in aggregation scheduling)
92 */
93 enum buffer_type {
94 BUF_AMPDU = BIT(0),
95 BUF_AGGR = BIT(1),
96 };
97
98 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
99 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
100
101 #define ATH_TXSTATUS_RING_SIZE 512
102
103 #define DS2PHYS(_dd, _ds) \
104 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
105 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
106 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
107
108 struct ath_descdma {
109 void *dd_desc;
110 dma_addr_t dd_desc_paddr;
111 u32 dd_desc_len;
112 };
113
114 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
115 struct list_head *head, const char *name,
116 int nbuf, int ndesc, bool is_tx);
117
118 /***********/
119 /* RX / TX */
120 /***********/
121
122 #define ATH_RXBUF 512
123 #define ATH_TXBUF 512
124 #define ATH_TXBUF_RESERVE 5
125 #define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
126 #define ATH_TXMAXTRY 13
127
128 #define TID_TO_WME_AC(_tid) \
129 ((((_tid) == 0) || ((_tid) == 3)) ? IEEE80211_AC_BE : \
130 (((_tid) == 1) || ((_tid) == 2)) ? IEEE80211_AC_BK : \
131 (((_tid) == 4) || ((_tid) == 5)) ? IEEE80211_AC_VI : \
132 IEEE80211_AC_VO)
133
134 #define ATH_AGGR_DELIM_SZ 4
135 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
136 /* number of delimiters for encryption padding */
137 #define ATH_AGGR_ENCRYPTDELIM 10
138 /* minimum h/w qdepth to be sustained to maximize aggregation */
139 #define ATH_AGGR_MIN_QDEPTH 2
140 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
141
142 #define IEEE80211_SEQ_SEQ_SHIFT 4
143 #define IEEE80211_SEQ_MAX 4096
144 #define IEEE80211_WEP_IVLEN 3
145 #define IEEE80211_WEP_KIDLEN 1
146 #define IEEE80211_WEP_CRCLEN 4
147 #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
148 (IEEE80211_WEP_IVLEN + \
149 IEEE80211_WEP_KIDLEN + \
150 IEEE80211_WEP_CRCLEN))
151
152 /* return whether a bit at index _n in bitmap _bm is set
153 * _sz is the size of the bitmap */
154 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
155 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
156
157 /* return block-ack bitmap index given sequence and starting sequence */
158 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
159
160 /* return the seqno for _start + _offset */
161 #define ATH_BA_INDEX2SEQ(_seq, _offset) (((_seq) + (_offset)) & (IEEE80211_SEQ_MAX - 1))
162
163 /* returns delimiter padding required given the packet length */
164 #define ATH_AGGR_GET_NDELIM(_len) \
165 (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \
166 DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
167
168 #define BAW_WITHIN(_start, _bawsz, _seqno) \
169 ((((_seqno) - (_start)) & 4095) < (_bawsz))
170
171 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
172
173 #define IS_CCK_RATE(rate) ((rate >= 0x18) && (rate <= 0x1e))
174
175 #define ATH_TX_COMPLETE_POLL_INT 1000
176
177 enum ATH_AGGR_STATUS {
178 ATH_AGGR_DONE,
179 ATH_AGGR_BAW_CLOSED,
180 ATH_AGGR_LIMITED,
181 };
182
183 #define ATH_TXFIFO_DEPTH 8
184 struct ath_txq {
185 int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */
186 u32 axq_qnum; /* ath9k hardware queue number */
187 void *axq_link;
188 struct list_head axq_q;
189 spinlock_t axq_lock;
190 u32 axq_depth;
191 u32 axq_ampdu_depth;
192 bool stopped;
193 bool axq_tx_inprogress;
194 struct list_head axq_acq;
195 struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
196 u8 txq_headidx;
197 u8 txq_tailidx;
198 int pending_frames;
199 struct sk_buff_head complete_q;
200 };
201
202 struct ath_atx_ac {
203 struct ath_txq *txq;
204 int sched;
205 struct list_head list;
206 struct list_head tid_q;
207 bool clear_ps_filter;
208 };
209
210 struct ath_frame_info {
211 struct ath_buf *bf;
212 int framelen;
213 enum ath9k_key_type keytype;
214 u8 keyix;
215 u8 retries;
216 u8 rtscts_rate;
217 };
218
219 struct ath_buf_state {
220 u8 bf_type;
221 u8 bfs_paprd;
222 u8 ndelim;
223 u16 seqno;
224 unsigned long bfs_paprd_timestamp;
225 };
226
227 struct ath_buf {
228 struct list_head list;
229 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
230 an aggregate) */
231 struct ath_buf *bf_next; /* next subframe in the aggregate */
232 struct sk_buff *bf_mpdu; /* enclosing frame structure */
233 void *bf_desc; /* virtual addr of desc */
234 dma_addr_t bf_daddr; /* physical addr of desc */
235 dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
236 bool bf_stale;
237 struct ieee80211_tx_rate rates[4];
238 struct ath_buf_state bf_state;
239 };
240
241 struct ath_atx_tid {
242 struct list_head list;
243 struct sk_buff_head buf_q;
244 struct ath_node *an;
245 struct ath_atx_ac *ac;
246 unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
247 int bar_index;
248 u16 seq_start;
249 u16 seq_next;
250 u16 baw_size;
251 int tidno;
252 int baw_head; /* first un-acked tx buffer */
253 int baw_tail; /* next unused tx buffer slot */
254 bool sched;
255 bool paused;
256 bool active;
257 };
258
259 struct ath_node {
260 struct ath_softc *sc;
261 struct ieee80211_sta *sta; /* station struct we're part of */
262 struct ieee80211_vif *vif; /* interface with which we're associated */
263 struct ath_atx_tid tid[IEEE80211_NUM_TIDS];
264 struct ath_atx_ac ac[IEEE80211_NUM_ACS];
265 int ps_key;
266
267 u16 maxampdu;
268 u8 mpdudensity;
269
270 bool sleeping;
271
272 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_DEBUGFS)
273 struct dentry *node_stat;
274 #endif
275 };
276
277 struct ath_tx_control {
278 struct ath_txq *txq;
279 struct ath_node *an;
280 u8 paprd;
281 struct ieee80211_sta *sta;
282 };
283
284 #define ATH_TX_ERROR 0x01
285
286 /**
287 * @txq_map: Index is mac80211 queue number. This is
288 * not necessarily the same as the hardware queue number
289 * (axq_qnum).
290 */
291 struct ath_tx {
292 u16 seq_no;
293 u32 txqsetup;
294 spinlock_t txbuflock;
295 struct list_head txbuf;
296 struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
297 struct ath_descdma txdma;
298 struct ath_txq *txq_map[IEEE80211_NUM_ACS];
299 u32 txq_max_pending[IEEE80211_NUM_ACS];
300 u16 max_aggr_framelen[IEEE80211_NUM_ACS][4][32];
301 };
302
303 struct ath_rx_edma {
304 struct sk_buff_head rx_fifo;
305 u32 rx_fifo_hwsize;
306 };
307
308 struct ath_rx {
309 u8 defant;
310 u8 rxotherant;
311 bool discard_next;
312 u32 *rxlink;
313 u32 num_pkts;
314 unsigned int rxfilter;
315 struct list_head rxbuf;
316 struct ath_descdma rxdma;
317 struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
318
319 struct sk_buff *frag;
320
321 u32 ampdu_ref;
322 };
323
324 int ath_startrecv(struct ath_softc *sc);
325 bool ath_stoprecv(struct ath_softc *sc);
326 u32 ath_calcrxfilter(struct ath_softc *sc);
327 int ath_rx_init(struct ath_softc *sc, int nbufs);
328 void ath_rx_cleanup(struct ath_softc *sc);
329 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
330 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
331 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq);
332 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq);
333 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq);
334 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
335 bool ath_drain_all_txq(struct ath_softc *sc);
336 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq);
337 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
338 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
339 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
340 int ath_tx_init(struct ath_softc *sc, int nbufs);
341 int ath_txq_update(struct ath_softc *sc, int qnum,
342 struct ath9k_tx_queue_info *q);
343 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop);
344 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
345 struct ath_tx_control *txctl);
346 void ath_tx_tasklet(struct ath_softc *sc);
347 void ath_tx_edma_tasklet(struct ath_softc *sc);
348 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
349 u16 tid, u16 *ssn);
350 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
351 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
352
353 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an);
354 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
355 struct ath_node *an);
356
357 /********/
358 /* VIFs */
359 /********/
360
361 struct ath_vif {
362 int av_bslot;
363 bool primary_sta_vif;
364 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
365 struct ath_buf *av_bcbuf;
366 };
367
368 /*******************/
369 /* Beacon Handling */
370 /*******************/
371
372 /*
373 * Regardless of the number of beacons we stagger, (i.e. regardless of the
374 * number of BSSIDs) if a given beacon does not go out even after waiting this
375 * number of beacon intervals, the game's up.
376 */
377 #define BSTUCK_THRESH 9
378 #define ATH_BCBUF 8
379 #define ATH_DEFAULT_BINTVAL 100 /* TU */
380 #define ATH_DEFAULT_BMISS_LIMIT 10
381 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
382
383 struct ath_beacon_config {
384 int beacon_interval;
385 u16 listen_interval;
386 u16 dtim_period;
387 u16 bmiss_timeout;
388 u8 dtim_count;
389 bool enable_beacon;
390 bool ibss_creator;
391 };
392
393 struct ath_beacon {
394 enum {
395 OK, /* no change needed */
396 UPDATE, /* update pending */
397 COMMIT /* beacon sent, commit change */
398 } updateslot; /* slot time update fsm */
399
400 u32 beaconq;
401 u32 bmisscnt;
402 u32 bc_tstamp;
403 struct ieee80211_vif *bslot[ATH_BCBUF];
404 int slottime;
405 int slotupdate;
406 struct ath9k_tx_queue_info beacon_qi;
407 struct ath_descdma bdma;
408 struct ath_txq *cabq;
409 struct list_head bbuf;
410
411 bool tx_processed;
412 bool tx_last;
413 };
414
415 void ath9k_beacon_tasklet(unsigned long data);
416 bool ath9k_allow_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
417 void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif,
418 u32 changed);
419 void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
420 void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
421 void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif);
422 void ath9k_set_beacon(struct ath_softc *sc);
423
424 /*******************/
425 /* Link Monitoring */
426 /*******************/
427
428 #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */
429 #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */
430 #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */
431 #define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */
432 #define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */
433 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */
434 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */
435 #define ATH_ANI_MAX_SKIP_COUNT 10
436
437 #define ATH_PAPRD_TIMEOUT 100 /* msecs */
438 #define ATH_PLL_WORK_INTERVAL 100
439
440 void ath_tx_complete_poll_work(struct work_struct *work);
441 void ath_reset_work(struct work_struct *work);
442 void ath_hw_check(struct work_struct *work);
443 void ath_hw_pll_work(struct work_struct *work);
444 void ath_rx_poll(unsigned long data);
445 void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon);
446 void ath_paprd_calibrate(struct work_struct *work);
447 void ath_ani_calibrate(unsigned long data);
448 void ath_start_ani(struct ath_softc *sc);
449 void ath_stop_ani(struct ath_softc *sc);
450 void ath_check_ani(struct ath_softc *sc);
451 int ath_update_survey_stats(struct ath_softc *sc);
452 void ath_update_survey_nf(struct ath_softc *sc, int channel);
453 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type);
454
455 /**********/
456 /* BTCOEX */
457 /**********/
458
459 #define ATH_DUMP_BTCOEX(_s, _val) \
460 do { \
461 len += snprintf(buf + len, size - len, \
462 "%20s : %10d\n", _s, (_val)); \
463 } while (0)
464
465 enum bt_op_flags {
466 BT_OP_PRIORITY_DETECTED,
467 BT_OP_SCAN,
468 };
469
470 struct ath_btcoex {
471 bool hw_timer_enabled;
472 spinlock_t btcoex_lock;
473 struct timer_list period_timer; /* Timer for BT period */
474 u32 bt_priority_cnt;
475 unsigned long bt_priority_time;
476 unsigned long op_flags;
477 int bt_stomp_type; /* Types of BT stomping */
478 u32 btcoex_no_stomp; /* in usec */
479 u32 btcoex_period; /* in msec */
480 u32 btscan_no_stomp; /* in usec */
481 u32 duty_cycle;
482 u32 bt_wait_time;
483 int rssi_count;
484 struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */
485 struct ath_mci_profile mci;
486 u8 stomp_audio;
487 };
488
489 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
490 int ath9k_init_btcoex(struct ath_softc *sc);
491 void ath9k_deinit_btcoex(struct ath_softc *sc);
492 void ath9k_start_btcoex(struct ath_softc *sc);
493 void ath9k_stop_btcoex(struct ath_softc *sc);
494 void ath9k_btcoex_timer_resume(struct ath_softc *sc);
495 void ath9k_btcoex_timer_pause(struct ath_softc *sc);
496 void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status);
497 u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen);
498 void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc);
499 int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size);
500 #else
ath9k_init_btcoex(struct ath_softc * sc)501 static inline int ath9k_init_btcoex(struct ath_softc *sc)
502 {
503 return 0;
504 }
ath9k_deinit_btcoex(struct ath_softc * sc)505 static inline void ath9k_deinit_btcoex(struct ath_softc *sc)
506 {
507 }
ath9k_start_btcoex(struct ath_softc * sc)508 static inline void ath9k_start_btcoex(struct ath_softc *sc)
509 {
510 }
ath9k_stop_btcoex(struct ath_softc * sc)511 static inline void ath9k_stop_btcoex(struct ath_softc *sc)
512 {
513 }
ath9k_btcoex_handle_interrupt(struct ath_softc * sc,u32 status)514 static inline void ath9k_btcoex_handle_interrupt(struct ath_softc *sc,
515 u32 status)
516 {
517 }
ath9k_btcoex_aggr_limit(struct ath_softc * sc,u32 max_4ms_framelen)518 static inline u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc,
519 u32 max_4ms_framelen)
520 {
521 return 0;
522 }
ath9k_btcoex_stop_gen_timer(struct ath_softc * sc)523 static inline void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc)
524 {
525 }
ath9k_dump_btcoex(struct ath_softc * sc,u8 * buf,u32 size)526 static inline int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size)
527 {
528 return 0;
529 }
530 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
531
532 struct ath9k_wow_pattern {
533 u8 pattern_bytes[MAX_PATTERN_SIZE];
534 u8 mask_bytes[MAX_PATTERN_SIZE];
535 u32 pattern_len;
536 };
537
538 /********************/
539 /* LED Control */
540 /********************/
541
542 #define ATH_LED_PIN_DEF 1
543 #define ATH_LED_PIN_9287 8
544 #define ATH_LED_PIN_9300 10
545 #define ATH_LED_PIN_9485 6
546 #define ATH_LED_PIN_9462 4
547
548 #ifdef CONFIG_MAC80211_LEDS
549 void ath_init_leds(struct ath_softc *sc);
550 void ath_deinit_leds(struct ath_softc *sc);
551 void ath_fill_led_pin(struct ath_softc *sc);
552 #else
ath_init_leds(struct ath_softc * sc)553 static inline void ath_init_leds(struct ath_softc *sc)
554 {
555 }
556
ath_deinit_leds(struct ath_softc * sc)557 static inline void ath_deinit_leds(struct ath_softc *sc)
558 {
559 }
ath_fill_led_pin(struct ath_softc * sc)560 static inline void ath_fill_led_pin(struct ath_softc *sc)
561 {
562 }
563 #endif
564
565 /*******************************/
566 /* Antenna diversity/combining */
567 /*******************************/
568
569 #define ATH_ANT_RX_CURRENT_SHIFT 4
570 #define ATH_ANT_RX_MAIN_SHIFT 2
571 #define ATH_ANT_RX_MASK 0x3
572
573 #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50
574 #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100
575 #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200
576 #define ATH_ANT_DIV_COMB_INIT_COUNT 95
577 #define ATH_ANT_DIV_COMB_MAX_COUNT 100
578 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30
579 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20
580
581 #define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1
582 #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4
583 #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
584 #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
585
586 enum ath9k_ant_div_comb_lna_conf {
587 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
588 ATH_ANT_DIV_COMB_LNA2,
589 ATH_ANT_DIV_COMB_LNA1,
590 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2,
591 };
592
593 struct ath_ant_comb {
594 u16 count;
595 u16 total_pkt_count;
596 bool scan;
597 bool scan_not_start;
598 int main_total_rssi;
599 int alt_total_rssi;
600 int alt_recv_cnt;
601 int main_recv_cnt;
602 int rssi_lna1;
603 int rssi_lna2;
604 int rssi_add;
605 int rssi_sub;
606 int rssi_first;
607 int rssi_second;
608 int rssi_third;
609 bool alt_good;
610 int quick_scan_cnt;
611 int main_conf;
612 enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf;
613 enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf;
614 bool first_ratio;
615 bool second_ratio;
616 unsigned long scan_start_time;
617 };
618
619 void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs);
620 void ath_ant_comb_update(struct ath_softc *sc);
621
622 /********************/
623 /* Main driver core */
624 /********************/
625
626 /*
627 * Default cache line size, in bytes.
628 * Used when PCI device not fully initialized by bootrom/BIOS
629 */
630 #define DEFAULT_CACHELINE 32
631 #define ATH_REGCLASSIDS_MAX 10
632 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
633 #define ATH_MAX_SW_RETRIES 30
634 #define ATH_CHAN_MAX 255
635
636 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */
637 #define ATH_RATE_DUMMY_MARKER 0
638
639 enum sc_op_flags {
640 SC_OP_INVALID,
641 SC_OP_BEACONS,
642 SC_OP_ANI_RUN,
643 SC_OP_PRIM_STA_VIF,
644 SC_OP_HW_RESET,
645 };
646
647 /* Powersave flags */
648 #define PS_WAIT_FOR_BEACON BIT(0)
649 #define PS_WAIT_FOR_CAB BIT(1)
650 #define PS_WAIT_FOR_PSPOLL_DATA BIT(2)
651 #define PS_WAIT_FOR_TX_ACK BIT(3)
652 #define PS_BEACON_SYNC BIT(4)
653 #define PS_WAIT_FOR_ANI BIT(5)
654
655 struct ath_rate_table;
656
657 struct ath9k_vif_iter_data {
658 u8 hw_macaddr[ETH_ALEN]; /* address of the first vif */
659 u8 mask[ETH_ALEN]; /* bssid mask */
660 bool has_hw_macaddr;
661
662 int naps; /* number of AP vifs */
663 int nmeshes; /* number of mesh vifs */
664 int nstations; /* number of station vifs */
665 int nwds; /* number of WDS vifs */
666 int nadhocs; /* number of adhoc vifs */
667 };
668
669 /* enum spectral_mode:
670 *
671 * @SPECTRAL_DISABLED: spectral mode is disabled
672 * @SPECTRAL_BACKGROUND: hardware sends samples when it is not busy with
673 * something else.
674 * @SPECTRAL_MANUAL: spectral scan is enabled, triggering for samples
675 * is performed manually.
676 * @SPECTRAL_CHANSCAN: Like manual, but also triggered when changing channels
677 * during a channel scan.
678 */
679 enum spectral_mode {
680 SPECTRAL_DISABLED = 0,
681 SPECTRAL_BACKGROUND,
682 SPECTRAL_MANUAL,
683 SPECTRAL_CHANSCAN,
684 };
685
686 struct ath_softc {
687 struct ieee80211_hw *hw;
688 struct device *dev;
689
690 struct survey_info *cur_survey;
691 struct survey_info survey[ATH9K_NUM_CHANNELS];
692
693 struct tasklet_struct intr_tq;
694 struct tasklet_struct bcon_tasklet;
695 struct ath_hw *sc_ah;
696 void __iomem *mem;
697 int irq;
698 spinlock_t sc_serial_rw;
699 spinlock_t sc_pm_lock;
700 spinlock_t sc_pcu_lock;
701 struct mutex mutex;
702 struct work_struct paprd_work;
703 struct work_struct hw_check_work;
704 struct work_struct hw_reset_work;
705 struct completion paprd_complete;
706
707 unsigned int hw_busy_count;
708 unsigned long sc_flags;
709
710 u32 intrstatus;
711 u16 ps_flags; /* PS_* */
712 u16 curtxpow;
713 bool ps_enabled;
714 bool ps_idle;
715 short nbcnvifs;
716 short nvifs;
717 unsigned long ps_usecount;
718
719 struct ath_config config;
720 struct ath_rx rx;
721 struct ath_tx tx;
722 struct ath_beacon beacon;
723 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
724
725 #ifdef CONFIG_MAC80211_LEDS
726 bool led_registered;
727 char led_name[32];
728 struct led_classdev led_cdev;
729 #endif
730
731 struct ath9k_hw_cal_data caldata;
732 int last_rssi;
733
734 #ifdef CONFIG_ATH9K_DEBUGFS
735 struct ath9k_debug debug;
736 #endif
737 struct ath_beacon_config cur_beacon_conf;
738 struct delayed_work tx_complete_work;
739 struct delayed_work hw_pll_work;
740 struct timer_list rx_poll_timer;
741
742 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
743 struct ath_btcoex btcoex;
744 struct ath_mci_coex mci_coex;
745 struct work_struct mci_work;
746 #endif
747
748 struct ath_descdma txsdma;
749
750 struct ath_ant_comb ant_comb;
751 u8 ant_tx, ant_rx;
752 struct dfs_pattern_detector *dfs_detector;
753 u32 wow_enabled;
754 /* relay(fs) channel for spectral scan */
755 struct rchan *rfs_chan_spec_scan;
756 enum spectral_mode spectral_mode;
757 struct ath_spec_scan spec_config;
758 int scanning;
759
760 #ifdef CONFIG_PM_SLEEP
761 atomic_t wow_got_bmiss_intr;
762 atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */
763 u32 wow_intr_before_sleep;
764 #endif
765 };
766
767 #define SPECTRAL_SCAN_BITMASK 0x10
768 /* Radar info packet format, used for DFS and spectral formats. */
769 struct ath_radar_info {
770 u8 pulse_length_pri;
771 u8 pulse_length_ext;
772 u8 pulse_bw_info;
773 } __packed;
774
775 /* The HT20 spectral data has 4 bytes of additional information at it's end.
776 *
777 * [7:0]: all bins {max_magnitude[1:0], bitmap_weight[5:0]}
778 * [7:0]: all bins max_magnitude[9:2]
779 * [7:0]: all bins {max_index[5:0], max_magnitude[11:10]}
780 * [3:0]: max_exp (shift amount to size max bin to 8-bit unsigned)
781 */
782 struct ath_ht20_mag_info {
783 u8 all_bins[3];
784 u8 max_exp;
785 } __packed;
786
787 #define SPECTRAL_HT20_NUM_BINS 56
788
789 /* WARNING: don't actually use this struct! MAC may vary the amount of
790 * data by -1/+2. This struct is for reference only.
791 */
792 struct ath_ht20_fft_packet {
793 u8 data[SPECTRAL_HT20_NUM_BINS];
794 struct ath_ht20_mag_info mag_info;
795 struct ath_radar_info radar_info;
796 } __packed;
797
798 #define SPECTRAL_HT20_TOTAL_DATA_LEN (sizeof(struct ath_ht20_fft_packet))
799
800 /* Dynamic 20/40 mode:
801 *
802 * [7:0]: lower bins {max_magnitude[1:0], bitmap_weight[5:0]}
803 * [7:0]: lower bins max_magnitude[9:2]
804 * [7:0]: lower bins {max_index[5:0], max_magnitude[11:10]}
805 * [7:0]: upper bins {max_magnitude[1:0], bitmap_weight[5:0]}
806 * [7:0]: upper bins max_magnitude[9:2]
807 * [7:0]: upper bins {max_index[5:0], max_magnitude[11:10]}
808 * [3:0]: max_exp (shift amount to size max bin to 8-bit unsigned)
809 */
810 struct ath_ht20_40_mag_info {
811 u8 lower_bins[3];
812 u8 upper_bins[3];
813 u8 max_exp;
814 } __packed;
815
816 #define SPECTRAL_HT20_40_NUM_BINS 128
817
818 /* WARNING: don't actually use this struct! MAC may vary the amount of
819 * data. This struct is for reference only.
820 */
821 struct ath_ht20_40_fft_packet {
822 u8 data[SPECTRAL_HT20_40_NUM_BINS];
823 struct ath_ht20_40_mag_info mag_info;
824 struct ath_radar_info radar_info;
825 } __packed;
826
827
828 #define SPECTRAL_HT20_40_TOTAL_DATA_LEN (sizeof(struct ath_ht20_40_fft_packet))
829
830 /* grabs the max magnitude from the all/upper/lower bins */
spectral_max_magnitude(u8 * bins)831 static inline u16 spectral_max_magnitude(u8 *bins)
832 {
833 return (bins[0] & 0xc0) >> 6 |
834 (bins[1] & 0xff) << 2 |
835 (bins[2] & 0x03) << 10;
836 }
837
838 /* return the max magnitude from the all/upper/lower bins */
spectral_max_index(u8 * bins)839 static inline u8 spectral_max_index(u8 *bins)
840 {
841 s8 m = (bins[2] & 0xfc) >> 2;
842
843 /* TODO: this still doesn't always report the right values ... */
844 if (m > 32)
845 m |= 0xe0;
846 else
847 m &= ~0xe0;
848
849 return m + 29;
850 }
851
852 /* return the bitmap weight from the all/upper/lower bins */
spectral_bitmap_weight(u8 * bins)853 static inline u8 spectral_bitmap_weight(u8 *bins)
854 {
855 return bins[0] & 0x3f;
856 }
857
858 /* FFT sample format given to userspace via debugfs.
859 *
860 * Please keep the type/length at the front position and change
861 * other fields after adding another sample type
862 *
863 * TODO: this might need rework when switching to nl80211-based
864 * interface.
865 */
866 enum ath_fft_sample_type {
867 ATH_FFT_SAMPLE_HT20 = 1,
868 };
869
870 struct fft_sample_tlv {
871 u8 type; /* see ath_fft_sample */
872 __be16 length;
873 /* type dependent data follows */
874 } __packed;
875
876 struct fft_sample_ht20 {
877 struct fft_sample_tlv tlv;
878
879 u8 max_exp;
880
881 __be16 freq;
882 s8 rssi;
883 s8 noise;
884
885 __be16 max_magnitude;
886 u8 max_index;
887 u8 bitmap_weight;
888
889 __be64 tsf;
890
891 u8 data[SPECTRAL_HT20_NUM_BINS];
892 } __packed;
893
894 void ath9k_tasklet(unsigned long data);
895 int ath_cabq_update(struct ath_softc *);
896
ath_read_cachesize(struct ath_common * common,int * csz)897 static inline void ath_read_cachesize(struct ath_common *common, int *csz)
898 {
899 common->bus_ops->read_cachesize(common, csz);
900 }
901
902 extern struct ieee80211_ops ath9k_ops;
903 extern int ath9k_modparam_nohwcrypt;
904 extern int led_blink;
905 extern bool is_ath9k_unloaded;
906
907 u8 ath9k_parse_mpdudensity(u8 mpdudensity);
908 irqreturn_t ath_isr(int irq, void *dev);
909 int ath9k_init_device(u16 devid, struct ath_softc *sc,
910 const struct ath_bus_ops *bus_ops);
911 void ath9k_deinit_device(struct ath_softc *sc);
912 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
913 void ath9k_reload_chainmask_settings(struct ath_softc *sc);
914
915 bool ath9k_uses_beacons(int type);
916 void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw);
917 int ath9k_spectral_scan_config(struct ieee80211_hw *hw,
918 enum spectral_mode spectral_mode);
919
920
921 #ifdef CONFIG_ATH9K_PCI
922 int ath_pci_init(void);
923 void ath_pci_exit(void);
924 #else
ath_pci_init(void)925 static inline int ath_pci_init(void) { return 0; };
ath_pci_exit(void)926 static inline void ath_pci_exit(void) {};
927 #endif
928
929 #ifdef CONFIG_ATH9K_AHB
930 int ath_ahb_init(void);
931 void ath_ahb_exit(void);
932 #else
ath_ahb_init(void)933 static inline int ath_ahb_init(void) { return 0; };
ath_ahb_exit(void)934 static inline void ath_ahb_exit(void) {};
935 #endif
936
937 void ath9k_ps_wakeup(struct ath_softc *sc);
938 void ath9k_ps_restore(struct ath_softc *sc);
939
940 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
941
942 void ath_start_rfkill_poll(struct ath_softc *sc);
943 extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
944 void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
945 struct ieee80211_vif *vif,
946 struct ath9k_vif_iter_data *iter_data);
947
948 #endif /* ATH9K_H */
949