1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 Waldorf GMBH 7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle 8 * Copyright (C) 1996 Paul M. Antoine 9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 10 */ 11 #ifndef _ASM_PROCESSOR_H 12 #define _ASM_PROCESSOR_H 13 14 #include <linux/cpumask.h> 15 #include <linux/threads.h> 16 17 #include <asm/cachectl.h> 18 #include <asm/cpu.h> 19 #include <asm/cpu-info.h> 20 #include <asm/mipsregs.h> 21 #include <asm/prefetch.h> 22 23 /* 24 * Return current * instruction pointer ("program counter"). 25 */ 26 #define current_text_addr() ({ __label__ _l; _l: &&_l;}) 27 28 /* 29 * System setup and hardware flags.. 30 */ 31 32 extern unsigned int vced_count, vcei_count; 33 34 /* 35 * MIPS does have an arch_pick_mmap_layout() 36 */ 37 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 38 39 /* 40 * A special page (the vdso) is mapped into all processes at the very 41 * top of the virtual memory space. 42 */ 43 #define SPECIAL_PAGES_SIZE (PAGE_SIZE * 2) 44 45 #ifdef CONFIG_32BIT 46 #ifdef CONFIG_KVM_GUEST 47 /* User space process size is limited to 1GB in KVM Guest Mode */ 48 #define TASK_SIZE 0x3fff8000UL 49 #else 50 /* 51 * User space process size: 2GB. This is hardcoded into a few places, 52 * so don't change it unless you know what you are doing. 53 */ 54 #define TASK_SIZE 0x7fff8000UL 55 #endif 56 57 #ifdef __KERNEL__ 58 #define STACK_TOP_MAX TASK_SIZE 59 #endif 60 61 #define TASK_IS_32BIT_ADDR 1 62 63 #endif 64 65 #ifdef CONFIG_64BIT 66 /* 67 * User space process size: 1TB. This is hardcoded into a few places, 68 * so don't change it unless you know what you are doing. TASK_SIZE 69 * is limited to 1TB by the R4000 architecture; R10000 and better can 70 * support 16TB; the architectural reserve for future expansion is 71 * 8192EB ... 72 */ 73 #define TASK_SIZE32 0x7fff8000UL 74 #ifdef CONFIG_48VMBITS 75 #define TASK_SIZE64 (0x1UL << ((cpu_data[0].vmbits>48)?48:cpu_data[0].vmbits)) 76 #else 77 #define TASK_SIZE64 (0x10000000000UL) 78 #endif 79 #define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64) 80 81 #ifdef __KERNEL__ 82 #define STACK_TOP_MAX TASK_SIZE64 83 #endif 84 85 86 #define TASK_SIZE_OF(tsk) \ 87 (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64) 88 89 #define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR) 90 91 #endif 92 93 #define STACK_TOP ((TASK_SIZE & PAGE_MASK) - SPECIAL_PAGES_SIZE) 94 95 /* 96 * This decides where the kernel will search for a free chunk of vm 97 * space during mmap's. 98 */ 99 #define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3) 100 101 102 #define NUM_FPU_REGS 32 103 104 #ifdef CONFIG_CPU_HAS_MSA 105 # define FPU_REG_WIDTH 128 106 #else 107 # define FPU_REG_WIDTH 64 108 #endif 109 110 union fpureg { 111 __u8 val8[FPU_REG_WIDTH / 8]; 112 __u16 val16[FPU_REG_WIDTH / 16]; 113 __u32 val32[FPU_REG_WIDTH / 32]; 114 __u64 val64[FPU_REG_WIDTH / 64]; 115 }; 116 117 #ifdef CONFIG_CPU_LITTLE_ENDIAN 118 # define FPR_IDX(width, idx) (idx) 119 #else 120 # define FPR_IDX(width, idx) ((idx) ^ ((64 / (width)) - 1)) 121 #endif 122 123 #define BUILD_FPR_ACCESS(width) \ 124 static inline u##width get_fpr##width(union fpureg *fpr, unsigned idx) \ 125 { \ 126 return fpr->val##width[FPR_IDX(width, idx)]; \ 127 } \ 128 \ 129 static inline void set_fpr##width(union fpureg *fpr, unsigned idx, \ 130 u##width val) \ 131 { \ 132 fpr->val##width[FPR_IDX(width, idx)] = val; \ 133 } 134 135 BUILD_FPR_ACCESS(32) 136 BUILD_FPR_ACCESS(64) 137 138 /* 139 * It would be nice to add some more fields for emulator statistics, but there 140 * are a number of fixed offsets in offset.h and elsewhere that would have to 141 * be recalculated by hand. So the additional information will be private to 142 * the FPU emulator for now. See asm-mips/fpu_emulator.h. 143 */ 144 145 struct mips_fpu_struct { 146 union fpureg fpr[NUM_FPU_REGS]; 147 unsigned int fcr31; 148 unsigned int msacsr; 149 }; 150 151 #define NUM_DSP_REGS 6 152 153 typedef __u32 dspreg_t; 154 155 struct mips_dsp_state { 156 dspreg_t dspr[NUM_DSP_REGS]; 157 unsigned int dspcontrol; 158 }; 159 160 #define INIT_CPUMASK { \ 161 {0,} \ 162 } 163 164 struct mips3264_watch_reg_state { 165 /* The width of watchlo is 32 in a 32 bit kernel and 64 in a 166 64 bit kernel. We use unsigned long as it has the same 167 property. */ 168 unsigned long watchlo[NUM_WATCH_REGS]; 169 /* Only the mask and IRW bits from watchhi. */ 170 u16 watchhi[NUM_WATCH_REGS]; 171 }; 172 173 union mips_watch_reg_state { 174 struct mips3264_watch_reg_state mips3264; 175 }; 176 177 #ifdef CONFIG_CPU_CAVIUM_OCTEON 178 179 struct octeon_cop2_state { 180 /* DMFC2 rt, 0x0201 */ 181 unsigned long cop2_crc_iv; 182 /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */ 183 unsigned long cop2_crc_length; 184 /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */ 185 unsigned long cop2_crc_poly; 186 /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */ 187 unsigned long cop2_llm_dat[2]; 188 /* DMFC2 rt, 0x0084 */ 189 unsigned long cop2_3des_iv; 190 /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */ 191 unsigned long cop2_3des_key[3]; 192 /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */ 193 unsigned long cop2_3des_result; 194 /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */ 195 unsigned long cop2_aes_inp0; 196 /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */ 197 unsigned long cop2_aes_iv[2]; 198 /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2 199 * rt, 0x0107 */ 200 unsigned long cop2_aes_key[4]; 201 /* DMFC2 rt, 0x0110 */ 202 unsigned long cop2_aes_keylen; 203 /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */ 204 unsigned long cop2_aes_result[2]; 205 /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2 206 * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt, 207 * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt, 208 * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt, 209 * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */ 210 unsigned long cop2_hsh_datw[15]; 211 /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2 212 * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt, 213 * 0x0256; DMFC2 rt, 0x0257 - Pass2 */ 214 unsigned long cop2_hsh_ivw[8]; 215 /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */ 216 unsigned long cop2_gfm_mult[2]; 217 /* DMFC2 rt, 0x025E - Pass2 */ 218 unsigned long cop2_gfm_poly; 219 /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */ 220 unsigned long cop2_gfm_result[2]; 221 }; 222 #define INIT_OCTEON_COP2 {0,} 223 224 struct octeon_cvmseg_state { 225 unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE] 226 [cpu_dcache_line_size() / sizeof(unsigned long)]; 227 }; 228 229 #endif 230 231 typedef struct { 232 unsigned long seg; 233 } mm_segment_t; 234 235 #ifdef CONFIG_CPU_HAS_MSA 236 # define ARCH_MIN_TASKALIGN 16 237 # define FPU_ALIGN __aligned(16) 238 #else 239 # define ARCH_MIN_TASKALIGN 8 240 # define FPU_ALIGN 241 #endif 242 243 struct mips_abi; 244 245 /* 246 * If you change thread_struct remember to change the #defines below too! 247 */ 248 struct thread_struct { 249 /* Saved main processor registers. */ 250 unsigned long reg16; 251 unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23; 252 unsigned long reg29, reg30, reg31; 253 254 /* Saved cp0 stuff. */ 255 unsigned long cp0_status; 256 257 /* Saved fpu/fpu emulator stuff. */ 258 struct mips_fpu_struct fpu FPU_ALIGN; 259 #ifdef CONFIG_MIPS_MT_FPAFF 260 /* Emulated instruction count */ 261 unsigned long emulated_fp; 262 /* Saved per-thread scheduler affinity mask */ 263 cpumask_t user_cpus_allowed; 264 #endif /* CONFIG_MIPS_MT_FPAFF */ 265 266 /* Saved state of the DSP ASE, if available. */ 267 struct mips_dsp_state dsp; 268 269 /* Saved watch register state, if available. */ 270 union mips_watch_reg_state watch; 271 272 /* Other stuff associated with the thread. */ 273 unsigned long cp0_badvaddr; /* Last user fault */ 274 unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ 275 unsigned long error_code; 276 #ifdef CONFIG_CPU_CAVIUM_OCTEON 277 struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128))); 278 struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128))); 279 #endif 280 struct mips_abi *abi; 281 }; 282 283 #ifdef CONFIG_MIPS_MT_FPAFF 284 #define FPAFF_INIT \ 285 .emulated_fp = 0, \ 286 .user_cpus_allowed = INIT_CPUMASK, 287 #else 288 #define FPAFF_INIT 289 #endif /* CONFIG_MIPS_MT_FPAFF */ 290 291 #ifdef CONFIG_CPU_CAVIUM_OCTEON 292 #define OCTEON_INIT \ 293 .cp2 = INIT_OCTEON_COP2, 294 #else 295 #define OCTEON_INIT 296 #endif /* CONFIG_CPU_CAVIUM_OCTEON */ 297 298 #define INIT_THREAD { \ 299 /* \ 300 * Saved main processor registers \ 301 */ \ 302 .reg16 = 0, \ 303 .reg17 = 0, \ 304 .reg18 = 0, \ 305 .reg19 = 0, \ 306 .reg20 = 0, \ 307 .reg21 = 0, \ 308 .reg22 = 0, \ 309 .reg23 = 0, \ 310 .reg29 = 0, \ 311 .reg30 = 0, \ 312 .reg31 = 0, \ 313 /* \ 314 * Saved cp0 stuff \ 315 */ \ 316 .cp0_status = 0, \ 317 /* \ 318 * Saved FPU/FPU emulator stuff \ 319 */ \ 320 .fpu = { \ 321 .fpr = {{{0,},},}, \ 322 .fcr31 = 0, \ 323 .msacsr = 0, \ 324 }, \ 325 /* \ 326 * FPU affinity state (null if not FPAFF) \ 327 */ \ 328 FPAFF_INIT \ 329 /* \ 330 * Saved DSP stuff \ 331 */ \ 332 .dsp = { \ 333 .dspr = {0, }, \ 334 .dspcontrol = 0, \ 335 }, \ 336 /* \ 337 * saved watch register stuff \ 338 */ \ 339 .watch = {{{0,},},}, \ 340 /* \ 341 * Other stuff associated with the process \ 342 */ \ 343 .cp0_badvaddr = 0, \ 344 .cp0_baduaddr = 0, \ 345 .error_code = 0, \ 346 /* \ 347 * Cavium Octeon specifics (null if not Octeon) \ 348 */ \ 349 OCTEON_INIT \ 350 } 351 352 struct task_struct; 353 354 /* Free all resources held by a thread. */ 355 #define release_thread(thread) do { } while(0) 356 357 extern unsigned long thread_saved_pc(struct task_struct *tsk); 358 359 /* 360 * Do necessary setup to start up a newly executed thread. 361 */ 362 extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp); 363 364 unsigned long get_wchan(struct task_struct *p); 365 366 #define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \ 367 THREAD_SIZE - 32 - sizeof(struct pt_regs)) 368 #define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk)) 369 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc) 370 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29]) 371 #define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status) 372 373 #define cpu_relax() barrier() 374 375 /* 376 * Return_address is a replacement for __builtin_return_address(count) 377 * which on certain architectures cannot reasonably be implemented in GCC 378 * (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386). 379 * Note that __builtin_return_address(x>=1) is forbidden because GCC 380 * aborts compilation on some CPUs. It's simply not possible to unwind 381 * some CPU's stackframes. 382 * 383 * __builtin_return_address works only for non-leaf functions. We avoid the 384 * overhead of a function call by forcing the compiler to save the return 385 * address register on the stack. 386 */ 387 #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);}) 388 389 #ifdef CONFIG_CPU_HAS_PREFETCH 390 391 #define ARCH_HAS_PREFETCH 392 #define prefetch(x) __builtin_prefetch((x), 0, 1) 393 394 #define ARCH_HAS_PREFETCHW 395 #define prefetchw(x) __builtin_prefetch((x), 1, 1) 396 397 /* 398 * See Documentation/scheduler/sched-arch.txt; prevents deadlock on SMP 399 * systems. 400 */ 401 #define __ARCH_WANT_UNLOCKED_CTXSW 402 403 #endif 404 405 /* 406 * Functions & macros implementing the PR_GET_FP_MODE & PR_SET_FP_MODE options 407 * to the prctl syscall. 408 */ 409 extern long mips_get_process_fp_mode(struct task_struct *task); 410 extern long mips_set_process_fp_mode(struct task_struct *task, 411 unsigned long value); 412 413 #define GET_FP_MODE(task) mips_get_process_fp_mode(task) 414 #define SET_FP_MODE(task,value) mips_set_process_fp_mode(task, value) 415 416 417 #endif /* _ASM_PROCESSOR_H */ 418