1 /*
2 * linux/drivers/video/omap2/dss/dss_features.c
3 *
4 * Copyright (C) 2010 Texas Instruments
5 * Author: Archit Taneja <archit@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/types.h>
23 #include <linux/err.h>
24 #include <linux/slab.h>
25
26 #include <video/omapdss.h>
27
28 #include "dss.h"
29 #include "dss_features.h"
30
31 /* Defines a generic omap register field */
32 struct dss_reg_field {
33 u8 start, end;
34 };
35
36 struct dss_param_range {
37 int min, max;
38 };
39
40 struct omap_dss_features {
41 const struct dss_reg_field *reg_fields;
42 const int num_reg_fields;
43
44 const enum dss_feat_id *features;
45 const int num_features;
46
47 const int num_mgrs;
48 const int num_ovls;
49 const int num_wbs;
50 const enum omap_display_type *supported_displays;
51 const enum omap_dss_output_id *supported_outputs;
52 const enum omap_color_mode *supported_color_modes;
53 const enum omap_overlay_caps *overlay_caps;
54 const char * const *clksrc_names;
55 const struct dss_param_range *dss_params;
56
57 const enum omap_dss_rotation_type supported_rotation_types;
58
59 const u32 buffer_size_unit;
60 const u32 burst_size_unit;
61 };
62
63 /* This struct is assigned to one of the below during initialization */
64 static const struct omap_dss_features *omap_current_dss_features;
65
66 static const struct dss_reg_field omap2_dss_reg_fields[] = {
67 [FEAT_REG_FIRHINC] = { 11, 0 },
68 [FEAT_REG_FIRVINC] = { 27, 16 },
69 [FEAT_REG_FIFOLOWTHRESHOLD] = { 8, 0 },
70 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 24, 16 },
71 [FEAT_REG_FIFOSIZE] = { 8, 0 },
72 [FEAT_REG_HORIZONTALACCU] = { 9, 0 },
73 [FEAT_REG_VERTICALACCU] = { 25, 16 },
74 [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
75 [FEAT_REG_DSIPLL_REGN] = { 0, 0 },
76 [FEAT_REG_DSIPLL_REGM] = { 0, 0 },
77 [FEAT_REG_DSIPLL_REGM_DISPC] = { 0, 0 },
78 [FEAT_REG_DSIPLL_REGM_DSI] = { 0, 0 },
79 };
80
81 static const struct dss_reg_field omap3_dss_reg_fields[] = {
82 [FEAT_REG_FIRHINC] = { 12, 0 },
83 [FEAT_REG_FIRVINC] = { 28, 16 },
84 [FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 },
85 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 },
86 [FEAT_REG_FIFOSIZE] = { 10, 0 },
87 [FEAT_REG_HORIZONTALACCU] = { 9, 0 },
88 [FEAT_REG_VERTICALACCU] = { 25, 16 },
89 [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
90 [FEAT_REG_DSIPLL_REGN] = { 7, 1 },
91 [FEAT_REG_DSIPLL_REGM] = { 18, 8 },
92 [FEAT_REG_DSIPLL_REGM_DISPC] = { 22, 19 },
93 [FEAT_REG_DSIPLL_REGM_DSI] = { 26, 23 },
94 };
95
96 static const struct dss_reg_field omap4_dss_reg_fields[] = {
97 [FEAT_REG_FIRHINC] = { 12, 0 },
98 [FEAT_REG_FIRVINC] = { 28, 16 },
99 [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 },
100 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 },
101 [FEAT_REG_FIFOSIZE] = { 15, 0 },
102 [FEAT_REG_HORIZONTALACCU] = { 10, 0 },
103 [FEAT_REG_VERTICALACCU] = { 26, 16 },
104 [FEAT_REG_DISPC_CLK_SWITCH] = { 9, 8 },
105 [FEAT_REG_DSIPLL_REGN] = { 8, 1 },
106 [FEAT_REG_DSIPLL_REGM] = { 20, 9 },
107 [FEAT_REG_DSIPLL_REGM_DISPC] = { 25, 21 },
108 [FEAT_REG_DSIPLL_REGM_DSI] = { 30, 26 },
109 };
110
111 static const struct dss_reg_field omap5_dss_reg_fields[] = {
112 [FEAT_REG_FIRHINC] = { 12, 0 },
113 [FEAT_REG_FIRVINC] = { 28, 16 },
114 [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 },
115 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 },
116 [FEAT_REG_FIFOSIZE] = { 15, 0 },
117 [FEAT_REG_HORIZONTALACCU] = { 10, 0 },
118 [FEAT_REG_VERTICALACCU] = { 26, 16 },
119 [FEAT_REG_DISPC_CLK_SWITCH] = { 9, 7 },
120 [FEAT_REG_DSIPLL_REGN] = { 8, 1 },
121 [FEAT_REG_DSIPLL_REGM] = { 20, 9 },
122 [FEAT_REG_DSIPLL_REGM_DISPC] = { 25, 21 },
123 [FEAT_REG_DSIPLL_REGM_DSI] = { 30, 26 },
124 };
125
126 static const enum omap_display_type omap2_dss_supported_displays[] = {
127 /* OMAP_DSS_CHANNEL_LCD */
128 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI,
129
130 /* OMAP_DSS_CHANNEL_DIGIT */
131 OMAP_DISPLAY_TYPE_VENC,
132 };
133
134 static const enum omap_display_type omap3430_dss_supported_displays[] = {
135 /* OMAP_DSS_CHANNEL_LCD */
136 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
137 OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI,
138
139 /* OMAP_DSS_CHANNEL_DIGIT */
140 OMAP_DISPLAY_TYPE_VENC,
141 };
142
143 static const enum omap_display_type omap3630_dss_supported_displays[] = {
144 /* OMAP_DSS_CHANNEL_LCD */
145 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
146 OMAP_DISPLAY_TYPE_DSI,
147
148 /* OMAP_DSS_CHANNEL_DIGIT */
149 OMAP_DISPLAY_TYPE_VENC,
150 };
151
152 static const enum omap_display_type omap4_dss_supported_displays[] = {
153 /* OMAP_DSS_CHANNEL_LCD */
154 OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI,
155
156 /* OMAP_DSS_CHANNEL_DIGIT */
157 OMAP_DISPLAY_TYPE_VENC | OMAP_DISPLAY_TYPE_HDMI,
158
159 /* OMAP_DSS_CHANNEL_LCD2 */
160 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
161 OMAP_DISPLAY_TYPE_DSI,
162 };
163
164 static const enum omap_display_type omap5_dss_supported_displays[] = {
165 /* OMAP_DSS_CHANNEL_LCD */
166 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
167 OMAP_DISPLAY_TYPE_DSI,
168
169 /* OMAP_DSS_CHANNEL_DIGIT */
170 OMAP_DISPLAY_TYPE_HDMI | OMAP_DISPLAY_TYPE_DPI,
171
172 /* OMAP_DSS_CHANNEL_LCD2 */
173 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
174 OMAP_DISPLAY_TYPE_DSI,
175 };
176
177 static const enum omap_dss_output_id omap2_dss_supported_outputs[] = {
178 /* OMAP_DSS_CHANNEL_LCD */
179 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI,
180
181 /* OMAP_DSS_CHANNEL_DIGIT */
182 OMAP_DSS_OUTPUT_VENC,
183 };
184
185 static const enum omap_dss_output_id omap3430_dss_supported_outputs[] = {
186 /* OMAP_DSS_CHANNEL_LCD */
187 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
188 OMAP_DSS_OUTPUT_SDI | OMAP_DSS_OUTPUT_DSI1,
189
190 /* OMAP_DSS_CHANNEL_DIGIT */
191 OMAP_DSS_OUTPUT_VENC,
192 };
193
194 static const enum omap_dss_output_id omap3630_dss_supported_outputs[] = {
195 /* OMAP_DSS_CHANNEL_LCD */
196 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
197 OMAP_DSS_OUTPUT_DSI1,
198
199 /* OMAP_DSS_CHANNEL_DIGIT */
200 OMAP_DSS_OUTPUT_VENC,
201 };
202
203 static const enum omap_dss_output_id omap4_dss_supported_outputs[] = {
204 /* OMAP_DSS_CHANNEL_LCD */
205 OMAP_DSS_OUTPUT_DBI | OMAP_DSS_OUTPUT_DSI1,
206
207 /* OMAP_DSS_CHANNEL_DIGIT */
208 OMAP_DSS_OUTPUT_VENC | OMAP_DSS_OUTPUT_HDMI,
209
210 /* OMAP_DSS_CHANNEL_LCD2 */
211 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
212 OMAP_DSS_OUTPUT_DSI2,
213 };
214
215 static const enum omap_dss_output_id omap5_dss_supported_outputs[] = {
216 /* OMAP_DSS_CHANNEL_LCD */
217 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
218 OMAP_DSS_OUTPUT_DSI1 | OMAP_DSS_OUTPUT_DSI2,
219
220 /* OMAP_DSS_CHANNEL_DIGIT */
221 OMAP_DSS_OUTPUT_HDMI | OMAP_DSS_OUTPUT_DPI,
222
223 /* OMAP_DSS_CHANNEL_LCD2 */
224 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
225 OMAP_DSS_OUTPUT_DSI1,
226
227 /* OMAP_DSS_CHANNEL_LCD3 */
228 OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
229 OMAP_DSS_OUTPUT_DSI2,
230 };
231
232 static const enum omap_color_mode omap2_dss_supported_color_modes[] = {
233 /* OMAP_DSS_GFX */
234 OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
235 OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
236 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
237 OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,
238
239 /* OMAP_DSS_VIDEO1 */
240 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
241 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
242 OMAP_DSS_COLOR_UYVY,
243
244 /* OMAP_DSS_VIDEO2 */
245 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
246 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
247 OMAP_DSS_COLOR_UYVY,
248 };
249
250 static const enum omap_color_mode omap3_dss_supported_color_modes[] = {
251 /* OMAP_DSS_GFX */
252 OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
253 OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
254 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
255 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
256 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
257 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
258
259 /* OMAP_DSS_VIDEO1 */
260 OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
261 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
262 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
263
264 /* OMAP_DSS_VIDEO2 */
265 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
266 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
267 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
268 OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
269 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
270 };
271
272 static const enum omap_color_mode omap4_dss_supported_color_modes[] = {
273 /* OMAP_DSS_GFX */
274 OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
275 OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
276 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
277 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
278 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
279 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32 |
280 OMAP_DSS_COLOR_ARGB16_1555 | OMAP_DSS_COLOR_RGBX16 |
281 OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_XRGB16_1555,
282
283 /* OMAP_DSS_VIDEO1 */
284 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
285 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
286 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
287 OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
288 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
289 OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
290 OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
291 OMAP_DSS_COLOR_RGBX32,
292
293 /* OMAP_DSS_VIDEO2 */
294 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
295 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
296 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
297 OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
298 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
299 OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
300 OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
301 OMAP_DSS_COLOR_RGBX32,
302
303 /* OMAP_DSS_VIDEO3 */
304 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
305 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
306 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
307 OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
308 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
309 OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
310 OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
311 OMAP_DSS_COLOR_RGBX32,
312
313 /* OMAP_DSS_WB */
314 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
315 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
316 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
317 OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
318 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
319 OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
320 OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
321 OMAP_DSS_COLOR_RGBX32,
322 };
323
324 static const enum omap_overlay_caps omap2_dss_overlay_caps[] = {
325 /* OMAP_DSS_GFX */
326 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
327
328 /* OMAP_DSS_VIDEO1 */
329 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
330 OMAP_DSS_OVL_CAP_REPLICATION,
331
332 /* OMAP_DSS_VIDEO2 */
333 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
334 OMAP_DSS_OVL_CAP_REPLICATION,
335 };
336
337 static const enum omap_overlay_caps omap3430_dss_overlay_caps[] = {
338 /* OMAP_DSS_GFX */
339 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_POS |
340 OMAP_DSS_OVL_CAP_REPLICATION,
341
342 /* OMAP_DSS_VIDEO1 */
343 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
344 OMAP_DSS_OVL_CAP_REPLICATION,
345
346 /* OMAP_DSS_VIDEO2 */
347 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
348 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
349 };
350
351 static const enum omap_overlay_caps omap3630_dss_overlay_caps[] = {
352 /* OMAP_DSS_GFX */
353 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA |
354 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
355
356 /* OMAP_DSS_VIDEO1 */
357 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
358 OMAP_DSS_OVL_CAP_REPLICATION,
359
360 /* OMAP_DSS_VIDEO2 */
361 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
362 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_POS |
363 OMAP_DSS_OVL_CAP_REPLICATION,
364 };
365
366 static const enum omap_overlay_caps omap4_dss_overlay_caps[] = {
367 /* OMAP_DSS_GFX */
368 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA |
369 OMAP_DSS_OVL_CAP_ZORDER | OMAP_DSS_OVL_CAP_POS |
370 OMAP_DSS_OVL_CAP_REPLICATION,
371
372 /* OMAP_DSS_VIDEO1 */
373 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
374 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER |
375 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
376
377 /* OMAP_DSS_VIDEO2 */
378 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
379 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER |
380 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
381
382 /* OMAP_DSS_VIDEO3 */
383 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
384 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER |
385 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
386 };
387
388 static const char * const omap2_dss_clk_source_names[] = {
389 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "N/A",
390 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "N/A",
391 [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCLK1",
392 };
393
394 static const char * const omap3_dss_clk_source_names[] = {
395 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI1_PLL_FCLK",
396 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI2_PLL_FCLK",
397 [OMAP_DSS_CLK_SRC_FCK] = "DSS1_ALWON_FCLK",
398 };
399
400 static const char * const omap4_dss_clk_source_names[] = {
401 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "PLL1_CLK1",
402 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "PLL1_CLK2",
403 [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCLK",
404 [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "PLL2_CLK1",
405 [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI] = "PLL2_CLK2",
406 };
407
408 static const char * const omap5_dss_clk_source_names[] = {
409 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DPLL_DSI1_A_CLK1",
410 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DPLL_DSI1_A_CLK2",
411 [OMAP_DSS_CLK_SRC_FCK] = "DSS_CLK",
412 [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "DPLL_DSI1_C_CLK1",
413 [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI] = "DPLL_DSI1_C_CLK2",
414 };
415
416 static const struct dss_param_range omap2_dss_param_range[] = {
417 [FEAT_PARAM_DSS_FCK] = { 0, 133000000 },
418 [FEAT_PARAM_DSS_PCD] = { 2, 255 },
419 [FEAT_PARAM_DSIPLL_REGN] = { 0, 0 },
420 [FEAT_PARAM_DSIPLL_REGM] = { 0, 0 },
421 [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, 0 },
422 [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, 0 },
423 [FEAT_PARAM_DSIPLL_FINT] = { 0, 0 },
424 [FEAT_PARAM_DSIPLL_LPDIV] = { 0, 0 },
425 [FEAT_PARAM_DOWNSCALE] = { 1, 2 },
426 /*
427 * Assuming the line width buffer to be 768 pixels as OMAP2 DISPC
428 * scaler cannot scale a image with width more than 768.
429 */
430 [FEAT_PARAM_LINEWIDTH] = { 1, 768 },
431 };
432
433 static const struct dss_param_range omap3_dss_param_range[] = {
434 [FEAT_PARAM_DSS_FCK] = { 0, 173000000 },
435 [FEAT_PARAM_DSS_PCD] = { 1, 255 },
436 [FEAT_PARAM_DSIPLL_REGN] = { 0, (1 << 7) - 1 },
437 [FEAT_PARAM_DSIPLL_REGM] = { 0, (1 << 11) - 1 },
438 [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, (1 << 4) - 1 },
439 [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, (1 << 4) - 1 },
440 [FEAT_PARAM_DSIPLL_FINT] = { 750000, 2100000 },
441 [FEAT_PARAM_DSIPLL_LPDIV] = { 1, (1 << 13) - 1},
442 [FEAT_PARAM_DSI_FCK] = { 0, 173000000 },
443 [FEAT_PARAM_DOWNSCALE] = { 1, 4 },
444 [FEAT_PARAM_LINEWIDTH] = { 1, 1024 },
445 };
446
447 static const struct dss_param_range omap4_dss_param_range[] = {
448 [FEAT_PARAM_DSS_FCK] = { 0, 186000000 },
449 [FEAT_PARAM_DSS_PCD] = { 1, 255 },
450 [FEAT_PARAM_DSIPLL_REGN] = { 0, (1 << 8) - 1 },
451 [FEAT_PARAM_DSIPLL_REGM] = { 0, (1 << 12) - 1 },
452 [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, (1 << 5) - 1 },
453 [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, (1 << 5) - 1 },
454 [FEAT_PARAM_DSIPLL_FINT] = { 500000, 2500000 },
455 [FEAT_PARAM_DSIPLL_LPDIV] = { 0, (1 << 13) - 1 },
456 [FEAT_PARAM_DSI_FCK] = { 0, 170000000 },
457 [FEAT_PARAM_DOWNSCALE] = { 1, 4 },
458 [FEAT_PARAM_LINEWIDTH] = { 1, 2048 },
459 };
460
461 static const struct dss_param_range omap5_dss_param_range[] = {
462 [FEAT_PARAM_DSS_FCK] = { 0, 209250000 },
463 [FEAT_PARAM_DSS_PCD] = { 1, 255 },
464 [FEAT_PARAM_DSIPLL_REGN] = { 0, (1 << 8) - 1 },
465 [FEAT_PARAM_DSIPLL_REGM] = { 0, (1 << 12) - 1 },
466 [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, (1 << 5) - 1 },
467 [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, (1 << 5) - 1 },
468 [FEAT_PARAM_DSIPLL_FINT] = { 150000, 52000000 },
469 [FEAT_PARAM_DSIPLL_LPDIV] = { 0, (1 << 13) - 1 },
470 [FEAT_PARAM_DSI_FCK] = { 0, 209250000 },
471 [FEAT_PARAM_DOWNSCALE] = { 1, 4 },
472 [FEAT_PARAM_LINEWIDTH] = { 1, 2048 },
473 };
474
475 static const enum dss_feat_id omap2_dss_feat_list[] = {
476 FEAT_LCDENABLEPOL,
477 FEAT_LCDENABLESIGNAL,
478 FEAT_PCKFREEENABLE,
479 FEAT_FUNCGATED,
480 FEAT_ROWREPEATENABLE,
481 FEAT_RESIZECONF,
482 };
483
484 static const enum dss_feat_id omap3430_dss_feat_list[] = {
485 FEAT_LCDENABLEPOL,
486 FEAT_LCDENABLESIGNAL,
487 FEAT_PCKFREEENABLE,
488 FEAT_FUNCGATED,
489 FEAT_LINEBUFFERSPLIT,
490 FEAT_ROWREPEATENABLE,
491 FEAT_RESIZECONF,
492 FEAT_DSI_PLL_FREQSEL,
493 FEAT_DSI_REVERSE_TXCLKESC,
494 FEAT_VENC_REQUIRES_TV_DAC_CLK,
495 FEAT_CPR,
496 FEAT_PRELOAD,
497 FEAT_FIR_COEF_V,
498 FEAT_ALPHA_FIXED_ZORDER,
499 FEAT_FIFO_MERGE,
500 FEAT_OMAP3_DSI_FIFO_BUG,
501 FEAT_DPI_USES_VDDS_DSI,
502 };
503
504 static const enum dss_feat_id am35xx_dss_feat_list[] = {
505 FEAT_LCDENABLEPOL,
506 FEAT_LCDENABLESIGNAL,
507 FEAT_PCKFREEENABLE,
508 FEAT_FUNCGATED,
509 FEAT_LINEBUFFERSPLIT,
510 FEAT_ROWREPEATENABLE,
511 FEAT_RESIZECONF,
512 FEAT_DSI_PLL_FREQSEL,
513 FEAT_DSI_REVERSE_TXCLKESC,
514 FEAT_VENC_REQUIRES_TV_DAC_CLK,
515 FEAT_CPR,
516 FEAT_PRELOAD,
517 FEAT_FIR_COEF_V,
518 FEAT_ALPHA_FIXED_ZORDER,
519 FEAT_FIFO_MERGE,
520 FEAT_OMAP3_DSI_FIFO_BUG,
521 };
522
523 static const enum dss_feat_id omap3630_dss_feat_list[] = {
524 FEAT_LCDENABLEPOL,
525 FEAT_LCDENABLESIGNAL,
526 FEAT_PCKFREEENABLE,
527 FEAT_FUNCGATED,
528 FEAT_LINEBUFFERSPLIT,
529 FEAT_ROWREPEATENABLE,
530 FEAT_RESIZECONF,
531 FEAT_DSI_PLL_PWR_BUG,
532 FEAT_DSI_PLL_FREQSEL,
533 FEAT_CPR,
534 FEAT_PRELOAD,
535 FEAT_FIR_COEF_V,
536 FEAT_ALPHA_FIXED_ZORDER,
537 FEAT_FIFO_MERGE,
538 FEAT_OMAP3_DSI_FIFO_BUG,
539 FEAT_DPI_USES_VDDS_DSI,
540 };
541
542 static const enum dss_feat_id omap4430_es1_0_dss_feat_list[] = {
543 FEAT_MGR_LCD2,
544 FEAT_CORE_CLK_DIV,
545 FEAT_LCD_CLK_SRC,
546 FEAT_DSI_DCS_CMD_CONFIG_VC,
547 FEAT_DSI_VC_OCP_WIDTH,
548 FEAT_DSI_GNQ,
549 FEAT_HANDLE_UV_SEPARATE,
550 FEAT_ATTR2,
551 FEAT_CPR,
552 FEAT_PRELOAD,
553 FEAT_FIR_COEF_V,
554 FEAT_ALPHA_FREE_ZORDER,
555 FEAT_FIFO_MERGE,
556 FEAT_BURST_2D,
557 };
558
559 static const enum dss_feat_id omap4430_es2_0_1_2_dss_feat_list[] = {
560 FEAT_MGR_LCD2,
561 FEAT_CORE_CLK_DIV,
562 FEAT_LCD_CLK_SRC,
563 FEAT_DSI_DCS_CMD_CONFIG_VC,
564 FEAT_DSI_VC_OCP_WIDTH,
565 FEAT_DSI_GNQ,
566 FEAT_HDMI_CTS_SWMODE,
567 FEAT_HANDLE_UV_SEPARATE,
568 FEAT_ATTR2,
569 FEAT_CPR,
570 FEAT_PRELOAD,
571 FEAT_FIR_COEF_V,
572 FEAT_ALPHA_FREE_ZORDER,
573 FEAT_FIFO_MERGE,
574 FEAT_BURST_2D,
575 };
576
577 static const enum dss_feat_id omap4_dss_feat_list[] = {
578 FEAT_MGR_LCD2,
579 FEAT_CORE_CLK_DIV,
580 FEAT_LCD_CLK_SRC,
581 FEAT_DSI_DCS_CMD_CONFIG_VC,
582 FEAT_DSI_VC_OCP_WIDTH,
583 FEAT_DSI_GNQ,
584 FEAT_HDMI_CTS_SWMODE,
585 FEAT_HDMI_AUDIO_USE_MCLK,
586 FEAT_HANDLE_UV_SEPARATE,
587 FEAT_ATTR2,
588 FEAT_CPR,
589 FEAT_PRELOAD,
590 FEAT_FIR_COEF_V,
591 FEAT_ALPHA_FREE_ZORDER,
592 FEAT_FIFO_MERGE,
593 FEAT_BURST_2D,
594 };
595
596 static const enum dss_feat_id omap5_dss_feat_list[] = {
597 FEAT_MGR_LCD2,
598 FEAT_CORE_CLK_DIV,
599 FEAT_LCD_CLK_SRC,
600 FEAT_DSI_DCS_CMD_CONFIG_VC,
601 FEAT_DSI_VC_OCP_WIDTH,
602 FEAT_DSI_GNQ,
603 FEAT_HDMI_CTS_SWMODE,
604 FEAT_HDMI_AUDIO_USE_MCLK,
605 FEAT_HANDLE_UV_SEPARATE,
606 FEAT_ATTR2,
607 FEAT_CPR,
608 FEAT_PRELOAD,
609 FEAT_FIR_COEF_V,
610 FEAT_ALPHA_FREE_ZORDER,
611 FEAT_FIFO_MERGE,
612 FEAT_BURST_2D,
613 FEAT_DSI_PLL_SELFREQDCO,
614 FEAT_DSI_PLL_REFSEL,
615 FEAT_DSI_PHY_DCC,
616 };
617
618 /* OMAP2 DSS Features */
619 static const struct omap_dss_features omap2_dss_features = {
620 .reg_fields = omap2_dss_reg_fields,
621 .num_reg_fields = ARRAY_SIZE(omap2_dss_reg_fields),
622
623 .features = omap2_dss_feat_list,
624 .num_features = ARRAY_SIZE(omap2_dss_feat_list),
625
626 .num_mgrs = 2,
627 .num_ovls = 3,
628 .supported_displays = omap2_dss_supported_displays,
629 .supported_outputs = omap2_dss_supported_outputs,
630 .supported_color_modes = omap2_dss_supported_color_modes,
631 .overlay_caps = omap2_dss_overlay_caps,
632 .clksrc_names = omap2_dss_clk_source_names,
633 .dss_params = omap2_dss_param_range,
634 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
635 .buffer_size_unit = 1,
636 .burst_size_unit = 8,
637 };
638
639 /* OMAP3 DSS Features */
640 static const struct omap_dss_features omap3430_dss_features = {
641 .reg_fields = omap3_dss_reg_fields,
642 .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
643
644 .features = omap3430_dss_feat_list,
645 .num_features = ARRAY_SIZE(omap3430_dss_feat_list),
646
647 .num_mgrs = 2,
648 .num_ovls = 3,
649 .supported_displays = omap3430_dss_supported_displays,
650 .supported_outputs = omap3430_dss_supported_outputs,
651 .supported_color_modes = omap3_dss_supported_color_modes,
652 .overlay_caps = omap3430_dss_overlay_caps,
653 .clksrc_names = omap3_dss_clk_source_names,
654 .dss_params = omap3_dss_param_range,
655 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
656 .buffer_size_unit = 1,
657 .burst_size_unit = 8,
658 };
659
660 /*
661 * AM35xx DSS Features. This is basically OMAP3 DSS Features without the
662 * vdds_dsi regulator.
663 */
664 static const struct omap_dss_features am35xx_dss_features = {
665 .reg_fields = omap3_dss_reg_fields,
666 .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
667
668 .features = am35xx_dss_feat_list,
669 .num_features = ARRAY_SIZE(am35xx_dss_feat_list),
670
671 .num_mgrs = 2,
672 .num_ovls = 3,
673 .supported_displays = omap3430_dss_supported_displays,
674 .supported_outputs = omap3430_dss_supported_outputs,
675 .supported_color_modes = omap3_dss_supported_color_modes,
676 .overlay_caps = omap3430_dss_overlay_caps,
677 .clksrc_names = omap3_dss_clk_source_names,
678 .dss_params = omap3_dss_param_range,
679 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
680 .buffer_size_unit = 1,
681 .burst_size_unit = 8,
682 };
683
684 static const struct omap_dss_features omap3630_dss_features = {
685 .reg_fields = omap3_dss_reg_fields,
686 .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
687
688 .features = omap3630_dss_feat_list,
689 .num_features = ARRAY_SIZE(omap3630_dss_feat_list),
690
691 .num_mgrs = 2,
692 .num_ovls = 3,
693 .supported_displays = omap3630_dss_supported_displays,
694 .supported_outputs = omap3630_dss_supported_outputs,
695 .supported_color_modes = omap3_dss_supported_color_modes,
696 .overlay_caps = omap3630_dss_overlay_caps,
697 .clksrc_names = omap3_dss_clk_source_names,
698 .dss_params = omap3_dss_param_range,
699 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
700 .buffer_size_unit = 1,
701 .burst_size_unit = 8,
702 };
703
704 /* OMAP4 DSS Features */
705 /* For OMAP4430 ES 1.0 revision */
706 static const struct omap_dss_features omap4430_es1_0_dss_features = {
707 .reg_fields = omap4_dss_reg_fields,
708 .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
709
710 .features = omap4430_es1_0_dss_feat_list,
711 .num_features = ARRAY_SIZE(omap4430_es1_0_dss_feat_list),
712
713 .num_mgrs = 3,
714 .num_ovls = 4,
715 .num_wbs = 1,
716 .supported_displays = omap4_dss_supported_displays,
717 .supported_outputs = omap4_dss_supported_outputs,
718 .supported_color_modes = omap4_dss_supported_color_modes,
719 .overlay_caps = omap4_dss_overlay_caps,
720 .clksrc_names = omap4_dss_clk_source_names,
721 .dss_params = omap4_dss_param_range,
722 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
723 .buffer_size_unit = 16,
724 .burst_size_unit = 16,
725 };
726
727 /* For OMAP4430 ES 2.0, 2.1 and 2.2 revisions */
728 static const struct omap_dss_features omap4430_es2_0_1_2_dss_features = {
729 .reg_fields = omap4_dss_reg_fields,
730 .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
731
732 .features = omap4430_es2_0_1_2_dss_feat_list,
733 .num_features = ARRAY_SIZE(omap4430_es2_0_1_2_dss_feat_list),
734
735 .num_mgrs = 3,
736 .num_ovls = 4,
737 .num_wbs = 1,
738 .supported_displays = omap4_dss_supported_displays,
739 .supported_outputs = omap4_dss_supported_outputs,
740 .supported_color_modes = omap4_dss_supported_color_modes,
741 .overlay_caps = omap4_dss_overlay_caps,
742 .clksrc_names = omap4_dss_clk_source_names,
743 .dss_params = omap4_dss_param_range,
744 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
745 .buffer_size_unit = 16,
746 .burst_size_unit = 16,
747 };
748
749 /* For all the other OMAP4 versions */
750 static const struct omap_dss_features omap4_dss_features = {
751 .reg_fields = omap4_dss_reg_fields,
752 .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
753
754 .features = omap4_dss_feat_list,
755 .num_features = ARRAY_SIZE(omap4_dss_feat_list),
756
757 .num_mgrs = 3,
758 .num_ovls = 4,
759 .num_wbs = 1,
760 .supported_displays = omap4_dss_supported_displays,
761 .supported_outputs = omap4_dss_supported_outputs,
762 .supported_color_modes = omap4_dss_supported_color_modes,
763 .overlay_caps = omap4_dss_overlay_caps,
764 .clksrc_names = omap4_dss_clk_source_names,
765 .dss_params = omap4_dss_param_range,
766 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
767 .buffer_size_unit = 16,
768 .burst_size_unit = 16,
769 };
770
771 /* OMAP5 DSS Features */
772 static const struct omap_dss_features omap5_dss_features = {
773 .reg_fields = omap5_dss_reg_fields,
774 .num_reg_fields = ARRAY_SIZE(omap5_dss_reg_fields),
775
776 .features = omap5_dss_feat_list,
777 .num_features = ARRAY_SIZE(omap5_dss_feat_list),
778
779 .num_mgrs = 3,
780 .num_ovls = 4,
781 .supported_displays = omap5_dss_supported_displays,
782 .supported_outputs = omap5_dss_supported_outputs,
783 .supported_color_modes = omap4_dss_supported_color_modes,
784 .overlay_caps = omap4_dss_overlay_caps,
785 .clksrc_names = omap5_dss_clk_source_names,
786 .dss_params = omap5_dss_param_range,
787 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
788 .buffer_size_unit = 16,
789 .burst_size_unit = 16,
790 };
791
792 #if defined(CONFIG_OMAP4_DSS_HDMI)
793 /* HDMI OMAP4 Functions*/
794 static const struct ti_hdmi_ip_ops omap4_hdmi_functions = {
795
796 .video_configure = ti_hdmi_4xxx_basic_configure,
797 .phy_enable = ti_hdmi_4xxx_phy_enable,
798 .phy_disable = ti_hdmi_4xxx_phy_disable,
799 .read_edid = ti_hdmi_4xxx_read_edid,
800 .detect = ti_hdmi_4xxx_detect,
801 .pll_enable = ti_hdmi_4xxx_pll_enable,
802 .pll_disable = ti_hdmi_4xxx_pll_disable,
803 .video_enable = ti_hdmi_4xxx_wp_video_start,
804 .video_disable = ti_hdmi_4xxx_wp_video_stop,
805 .dump_wrapper = ti_hdmi_4xxx_wp_dump,
806 .dump_core = ti_hdmi_4xxx_core_dump,
807 .dump_pll = ti_hdmi_4xxx_pll_dump,
808 .dump_phy = ti_hdmi_4xxx_phy_dump,
809 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
810 .audio_enable = ti_hdmi_4xxx_wp_audio_enable,
811 .audio_disable = ti_hdmi_4xxx_wp_audio_disable,
812 .audio_start = ti_hdmi_4xxx_audio_start,
813 .audio_stop = ti_hdmi_4xxx_audio_stop,
814 .audio_config = ti_hdmi_4xxx_audio_config,
815 .audio_get_dma_port = ti_hdmi_4xxx_audio_get_dma_port,
816 #endif
817
818 };
819
dss_init_hdmi_ip_ops(struct hdmi_ip_data * ip_data,enum omapdss_version version)820 void dss_init_hdmi_ip_ops(struct hdmi_ip_data *ip_data,
821 enum omapdss_version version)
822 {
823 switch (version) {
824 case OMAPDSS_VER_OMAP4430_ES1:
825 case OMAPDSS_VER_OMAP4430_ES2:
826 case OMAPDSS_VER_OMAP4:
827 ip_data->ops = &omap4_hdmi_functions;
828 break;
829 default:
830 ip_data->ops = NULL;
831 }
832
833 WARN_ON(ip_data->ops == NULL);
834 }
835 #endif
836
837 /* Functions returning values related to a DSS feature */
dss_feat_get_num_mgrs(void)838 int dss_feat_get_num_mgrs(void)
839 {
840 return omap_current_dss_features->num_mgrs;
841 }
842 EXPORT_SYMBOL(dss_feat_get_num_mgrs);
843
dss_feat_get_num_ovls(void)844 int dss_feat_get_num_ovls(void)
845 {
846 return omap_current_dss_features->num_ovls;
847 }
848 EXPORT_SYMBOL(dss_feat_get_num_ovls);
849
dss_feat_get_num_wbs(void)850 int dss_feat_get_num_wbs(void)
851 {
852 return omap_current_dss_features->num_wbs;
853 }
854
dss_feat_get_param_min(enum dss_range_param param)855 unsigned long dss_feat_get_param_min(enum dss_range_param param)
856 {
857 return omap_current_dss_features->dss_params[param].min;
858 }
859
dss_feat_get_param_max(enum dss_range_param param)860 unsigned long dss_feat_get_param_max(enum dss_range_param param)
861 {
862 return omap_current_dss_features->dss_params[param].max;
863 }
864
dss_feat_get_supported_displays(enum omap_channel channel)865 enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel)
866 {
867 return omap_current_dss_features->supported_displays[channel];
868 }
869 EXPORT_SYMBOL(dss_feat_get_supported_displays);
870
dss_feat_get_supported_outputs(enum omap_channel channel)871 enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel)
872 {
873 return omap_current_dss_features->supported_outputs[channel];
874 }
875 EXPORT_SYMBOL(dss_feat_get_supported_outputs);
876
dss_feat_get_supported_color_modes(enum omap_plane plane)877 enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane)
878 {
879 return omap_current_dss_features->supported_color_modes[plane];
880 }
881 EXPORT_SYMBOL(dss_feat_get_supported_color_modes);
882
dss_feat_get_overlay_caps(enum omap_plane plane)883 enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane plane)
884 {
885 return omap_current_dss_features->overlay_caps[plane];
886 }
887
dss_feat_color_mode_supported(enum omap_plane plane,enum omap_color_mode color_mode)888 bool dss_feat_color_mode_supported(enum omap_plane plane,
889 enum omap_color_mode color_mode)
890 {
891 return omap_current_dss_features->supported_color_modes[plane] &
892 color_mode;
893 }
894
dss_feat_get_clk_source_name(enum omap_dss_clk_source id)895 const char *dss_feat_get_clk_source_name(enum omap_dss_clk_source id)
896 {
897 return omap_current_dss_features->clksrc_names[id];
898 }
899
dss_feat_get_buffer_size_unit(void)900 u32 dss_feat_get_buffer_size_unit(void)
901 {
902 return omap_current_dss_features->buffer_size_unit;
903 }
904
dss_feat_get_burst_size_unit(void)905 u32 dss_feat_get_burst_size_unit(void)
906 {
907 return omap_current_dss_features->burst_size_unit;
908 }
909
910 /* DSS has_feature check */
dss_has_feature(enum dss_feat_id id)911 bool dss_has_feature(enum dss_feat_id id)
912 {
913 int i;
914 const enum dss_feat_id *features = omap_current_dss_features->features;
915 const int num_features = omap_current_dss_features->num_features;
916
917 for (i = 0; i < num_features; i++) {
918 if (features[i] == id)
919 return true;
920 }
921
922 return false;
923 }
924
dss_feat_get_reg_field(enum dss_feat_reg_field id,u8 * start,u8 * end)925 void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end)
926 {
927 if (id >= omap_current_dss_features->num_reg_fields)
928 BUG();
929
930 *start = omap_current_dss_features->reg_fields[id].start;
931 *end = omap_current_dss_features->reg_fields[id].end;
932 }
933
dss_feat_rotation_type_supported(enum omap_dss_rotation_type rot_type)934 bool dss_feat_rotation_type_supported(enum omap_dss_rotation_type rot_type)
935 {
936 return omap_current_dss_features->supported_rotation_types & rot_type;
937 }
938
dss_features_init(enum omapdss_version version)939 void dss_features_init(enum omapdss_version version)
940 {
941 switch (version) {
942 case OMAPDSS_VER_OMAP24xx:
943 omap_current_dss_features = &omap2_dss_features;
944 break;
945
946 case OMAPDSS_VER_OMAP34xx_ES1:
947 case OMAPDSS_VER_OMAP34xx_ES3:
948 omap_current_dss_features = &omap3430_dss_features;
949 break;
950
951 case OMAPDSS_VER_OMAP3630:
952 omap_current_dss_features = &omap3630_dss_features;
953 break;
954
955 case OMAPDSS_VER_OMAP4430_ES1:
956 omap_current_dss_features = &omap4430_es1_0_dss_features;
957 break;
958
959 case OMAPDSS_VER_OMAP4430_ES2:
960 omap_current_dss_features = &omap4430_es2_0_1_2_dss_features;
961 break;
962
963 case OMAPDSS_VER_OMAP4:
964 omap_current_dss_features = &omap4_dss_features;
965 break;
966
967 case OMAPDSS_VER_OMAP5:
968 omap_current_dss_features = &omap5_dss_features;
969 break;
970
971 case OMAPDSS_VER_AM35xx:
972 omap_current_dss_features = &am35xx_dss_features;
973 break;
974
975 default:
976 DSSWARN("Unsupported OMAP version");
977 break;
978 }
979 }
980