1 /* 2 * lppaca.h 3 * Copyright (C) 2001 Mike Corrigan IBM Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 #ifndef _ASM_POWERPC_LPPACA_H 20 #define _ASM_POWERPC_LPPACA_H 21 #ifdef __KERNEL__ 22 23 /* 24 * These definitions relate to hypervisors that only exist when using 25 * a server type processor 26 */ 27 #ifdef CONFIG_PPC_BOOK3S 28 29 /* 30 * This control block contains the data that is shared between the 31 * hypervisor and the OS. 32 */ 33 #include <linux/cache.h> 34 #include <linux/threads.h> 35 #include <asm/types.h> 36 #include <asm/mmu.h> 37 38 /* 39 * We only have to have statically allocated lppaca structs on 40 * legacy iSeries, which supports at most 64 cpus. 41 */ 42 #define NR_LPPACAS 1 43 44 /* 45 * The Hypervisor barfs if the lppaca crosses a page boundary. A 1k 46 * alignment is sufficient to prevent this 47 */ 48 struct lppaca { 49 /* cacheline 1 contains read-only data */ 50 51 u32 desc; /* Eye catcher 0xD397D781 */ 52 u16 size; /* Size of this struct */ 53 u16 reserved1; 54 u16 reserved2:14; 55 u8 shared_proc:1; /* Shared processor indicator */ 56 u8 secondary_thread:1; /* Secondary thread indicator */ 57 u8 reserved3[14]; 58 volatile u32 dyn_hw_node_id; /* Dynamic hardware node id */ 59 volatile u32 dyn_hw_proc_id; /* Dynamic hardware proc id */ 60 u8 reserved4[56]; 61 volatile u8 vphn_assoc_counts[8]; /* Virtual processor home node */ 62 /* associativity change counters */ 63 u8 reserved5[32]; 64 65 /* cacheline 2 contains local read-write data */ 66 67 u8 reserved6[48]; 68 u8 cede_latency_hint; 69 u8 reserved7[7]; 70 u8 dtl_enable_mask; /* Dispatch Trace Log mask */ 71 u8 donate_dedicated_cpu; /* Donate dedicated CPU cycles */ 72 u8 fpregs_in_use; 73 u8 pmcregs_in_use; 74 u8 reserved8[28]; 75 u64 wait_state_cycles; /* Wait cycles for this proc */ 76 u8 reserved9[28]; 77 u16 slb_count; /* # of SLBs to maintain */ 78 u8 idle; /* Indicate OS is idle */ 79 u8 vmxregs_in_use; 80 81 /* cacheline 3 is shared with other processors */ 82 83 /* 84 * This is the yield_count. An "odd" value (low bit on) means that 85 * the processor is yielded (either because of an OS yield or a 86 * hypervisor preempt). An even value implies that the processor is 87 * currently executing. 88 * NOTE: This value will ALWAYS be zero for dedicated processors and 89 * will NEVER be zero for shared processors (ie, initialized to a 1). 90 */ 91 volatile u32 yield_count; 92 volatile u32 dispersion_count; /* dispatch changed physical cpu */ 93 volatile u64 cmo_faults; /* CMO page fault count */ 94 volatile u64 cmo_fault_time; /* CMO page fault time */ 95 u8 reserved10[104]; 96 97 /* cacheline 4-5 */ 98 99 u32 page_ins; /* CMO Hint - # page ins by OS */ 100 u8 reserved11[148]; 101 volatile u64 dtl_idx; /* Dispatch Trace Log head index */ 102 u8 reserved12[96]; 103 } __attribute__((__aligned__(0x400))); 104 105 extern struct lppaca lppaca[]; 106 107 #define lppaca_of(cpu) (*paca[cpu].lppaca_ptr) 108 109 /* 110 * SLB shadow buffer structure as defined in the PAPR. The save_area 111 * contains adjacent ESID and VSID pairs for each shadowed SLB. The 112 * ESID is stored in the lower 64bits, then the VSID. 113 */ 114 struct slb_shadow { 115 u32 persistent; /* Number of persistent SLBs */ 116 u32 buffer_length; /* Total shadow buffer length */ 117 u64 reserved; 118 struct { 119 u64 esid; 120 u64 vsid; 121 } save_area[SLB_NUM_BOLTED]; 122 } ____cacheline_aligned; 123 124 extern struct slb_shadow slb_shadow[]; 125 126 /* 127 * Layout of entries in the hypervisor's dispatch trace log buffer. 128 */ 129 struct dtl_entry { 130 u8 dispatch_reason; 131 u8 preempt_reason; 132 u16 processor_id; 133 u32 enqueue_to_dispatch_time; 134 u32 ready_to_enqueue_time; 135 u32 waiting_to_ready_time; 136 u64 timebase; 137 u64 fault_addr; 138 u64 srr0; 139 u64 srr1; 140 }; 141 142 #define DISPATCH_LOG_BYTES 4096 /* bytes per cpu */ 143 #define N_DISPATCH_LOG (DISPATCH_LOG_BYTES / sizeof(struct dtl_entry)) 144 145 extern struct kmem_cache *dtl_cache; 146 147 /* 148 * When CONFIG_VIRT_CPU_ACCOUNTING_NATIVE = y, the cpu accounting code controls 149 * reading from the dispatch trace log. If other code wants to consume 150 * DTL entries, it can set this pointer to a function that will get 151 * called once for each DTL entry that gets processed. 152 */ 153 extern void (*dtl_consumer)(struct dtl_entry *entry, u64 index); 154 155 #endif /* CONFIG_PPC_BOOK3S */ 156 #endif /* __KERNEL__ */ 157 #endif /* _ASM_POWERPC_LPPACA_H */ 158