1 /*
2 * hcd_queue.c - DesignWare HS OTG Controller host queuing routines
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37 /*
38 * This file contains the functions to manage Queue Heads and Queue
39 * Transfer Descriptors for Host mode
40 */
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/spinlock.h>
44 #include <linux/interrupt.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/io.h>
47 #include <linux/slab.h>
48 #include <linux/usb.h>
49
50 #include <linux/usb/hcd.h>
51 #include <linux/usb/ch11.h>
52
53 #include "core.h"
54 #include "hcd.h"
55
56 /**
57 * dwc2_qh_init() - Initializes a QH structure
58 *
59 * @hsotg: The HCD state structure for the DWC OTG controller
60 * @qh: The QH to init
61 * @urb: Holds the information about the device/endpoint needed to initialize
62 * the QH
63 */
64 #define SCHEDULE_SLOP 10
dwc2_qh_init(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh,struct dwc2_hcd_urb * urb)65 static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
66 struct dwc2_hcd_urb *urb)
67 {
68 int dev_speed, hub_addr, hub_port;
69 char *speed, *type;
70
71 dev_vdbg(hsotg->dev, "%s()\n", __func__);
72
73 /* Initialize QH */
74 qh->ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
75 qh->ep_is_in = dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0;
76
77 qh->data_toggle = DWC2_HC_PID_DATA0;
78 qh->maxp = dwc2_hcd_get_mps(&urb->pipe_info);
79 INIT_LIST_HEAD(&qh->qtd_list);
80 INIT_LIST_HEAD(&qh->qh_list_entry);
81
82 /* FS/LS Endpoint on HS Hub, NOT virtual root hub */
83 dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
84
85 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
86
87 if ((dev_speed == USB_SPEED_LOW || dev_speed == USB_SPEED_FULL) &&
88 hub_addr != 0 && hub_addr != 1) {
89 dev_vdbg(hsotg->dev,
90 "QH init: EP %d: TT found at hub addr %d, for port %d\n",
91 dwc2_hcd_get_ep_num(&urb->pipe_info), hub_addr,
92 hub_port);
93 qh->do_split = 1;
94 }
95
96 if (qh->ep_type == USB_ENDPOINT_XFER_INT ||
97 qh->ep_type == USB_ENDPOINT_XFER_ISOC) {
98 /* Compute scheduling parameters once and save them */
99 u32 hprt, prtspd;
100
101 /* Todo: Account for split transfers in the bus time */
102 int bytecount =
103 dwc2_hb_mult(qh->maxp) * dwc2_max_packet(qh->maxp);
104
105 qh->usecs = NS_TO_US(usb_calc_bus_time(qh->do_split ?
106 USB_SPEED_HIGH : dev_speed, qh->ep_is_in,
107 qh->ep_type == USB_ENDPOINT_XFER_ISOC,
108 bytecount));
109 /* Start in a slightly future (micro)frame */
110 qh->sched_frame = dwc2_frame_num_inc(hsotg->frame_number,
111 SCHEDULE_SLOP);
112 qh->interval = urb->interval;
113 #if 0
114 /* Increase interrupt polling rate for debugging */
115 if (qh->ep_type == USB_ENDPOINT_XFER_INT)
116 qh->interval = 8;
117 #endif
118 hprt = readl(hsotg->regs + HPRT0);
119 prtspd = hprt & HPRT0_SPD_MASK;
120 if (prtspd == HPRT0_SPD_HIGH_SPEED &&
121 (dev_speed == USB_SPEED_LOW ||
122 dev_speed == USB_SPEED_FULL)) {
123 qh->interval *= 8;
124 qh->sched_frame |= 0x7;
125 qh->start_split_frame = qh->sched_frame;
126 }
127 dev_dbg(hsotg->dev, "interval=%d\n", qh->interval);
128 }
129
130 dev_vdbg(hsotg->dev, "DWC OTG HCD QH Initialized\n");
131 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - qh = %p\n", qh);
132 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Device Address = %d\n",
133 dwc2_hcd_get_dev_addr(&urb->pipe_info));
134 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Endpoint %d, %s\n",
135 dwc2_hcd_get_ep_num(&urb->pipe_info),
136 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
137
138 qh->dev_speed = dev_speed;
139
140 switch (dev_speed) {
141 case USB_SPEED_LOW:
142 speed = "low";
143 break;
144 case USB_SPEED_FULL:
145 speed = "full";
146 break;
147 case USB_SPEED_HIGH:
148 speed = "high";
149 break;
150 default:
151 speed = "?";
152 break;
153 }
154 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Speed = %s\n", speed);
155
156 switch (qh->ep_type) {
157 case USB_ENDPOINT_XFER_ISOC:
158 type = "isochronous";
159 break;
160 case USB_ENDPOINT_XFER_INT:
161 type = "interrupt";
162 break;
163 case USB_ENDPOINT_XFER_CONTROL:
164 type = "control";
165 break;
166 case USB_ENDPOINT_XFER_BULK:
167 type = "bulk";
168 break;
169 default:
170 type = "?";
171 break;
172 }
173
174 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Type = %s\n", type);
175
176 if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
177 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - usecs = %d\n",
178 qh->usecs);
179 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - interval = %d\n",
180 qh->interval);
181 }
182 }
183
184 /**
185 * dwc2_hcd_qh_create() - Allocates and initializes a QH
186 *
187 * @hsotg: The HCD state structure for the DWC OTG controller
188 * @urb: Holds the information about the device/endpoint needed
189 * to initialize the QH
190 * @atomic_alloc: Flag to do atomic allocation if needed
191 *
192 * Return: Pointer to the newly allocated QH, or NULL on error
193 */
dwc2_hcd_qh_create(struct dwc2_hsotg * hsotg,struct dwc2_hcd_urb * urb,gfp_t mem_flags)194 static struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
195 struct dwc2_hcd_urb *urb,
196 gfp_t mem_flags)
197 {
198 struct dwc2_qh *qh;
199
200 /* Allocate memory */
201 qh = kzalloc(sizeof(*qh), mem_flags);
202 if (!qh)
203 return NULL;
204
205 dwc2_qh_init(hsotg, qh, urb);
206
207 if (hsotg->core_params->dma_desc_enable > 0 &&
208 dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) {
209 dwc2_hcd_qh_free(hsotg, qh);
210 return NULL;
211 }
212
213 return qh;
214 }
215
216 /**
217 * dwc2_hcd_qh_free() - Frees the QH
218 *
219 * @hsotg: HCD instance
220 * @qh: The QH to free
221 *
222 * QH should already be removed from the list. QTD list should already be empty
223 * if called from URB Dequeue.
224 *
225 * Must NOT be called with interrupt disabled or spinlock held
226 */
dwc2_hcd_qh_free(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh)227 void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
228 {
229 u32 buf_size;
230
231 if (hsotg->core_params->dma_desc_enable > 0) {
232 dwc2_hcd_qh_free_ddma(hsotg, qh);
233 } else if (qh->dw_align_buf) {
234 if (qh->ep_type == USB_ENDPOINT_XFER_ISOC)
235 buf_size = 4096;
236 else
237 buf_size = hsotg->core_params->max_transfer_size;
238 dma_free_coherent(hsotg->dev, buf_size, qh->dw_align_buf,
239 qh->dw_align_buf_dma);
240 }
241
242 kfree(qh);
243 }
244
245 /**
246 * dwc2_periodic_channel_available() - Checks that a channel is available for a
247 * periodic transfer
248 *
249 * @hsotg: The HCD state structure for the DWC OTG controller
250 *
251 * Return: 0 if successful, negative error code otherise
252 */
dwc2_periodic_channel_available(struct dwc2_hsotg * hsotg)253 static int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg)
254 {
255 /*
256 * Currently assuming that there is a dedicated host channnel for
257 * each periodic transaction plus at least one host channel for
258 * non-periodic transactions
259 */
260 int status;
261 int num_channels;
262
263 num_channels = hsotg->core_params->host_channels;
264 if (hsotg->periodic_channels + hsotg->non_periodic_channels <
265 num_channels
266 && hsotg->periodic_channels < num_channels - 1) {
267 status = 0;
268 } else {
269 dev_dbg(hsotg->dev,
270 "%s: Total channels: %d, Periodic: %d, "
271 "Non-periodic: %d\n", __func__, num_channels,
272 hsotg->periodic_channels, hsotg->non_periodic_channels);
273 status = -ENOSPC;
274 }
275
276 return status;
277 }
278
279 /**
280 * dwc2_check_periodic_bandwidth() - Checks that there is sufficient bandwidth
281 * for the specified QH in the periodic schedule
282 *
283 * @hsotg: The HCD state structure for the DWC OTG controller
284 * @qh: QH containing periodic bandwidth required
285 *
286 * Return: 0 if successful, negative error code otherwise
287 *
288 * For simplicity, this calculation assumes that all the transfers in the
289 * periodic schedule may occur in the same (micro)frame
290 */
dwc2_check_periodic_bandwidth(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh)291 static int dwc2_check_periodic_bandwidth(struct dwc2_hsotg *hsotg,
292 struct dwc2_qh *qh)
293 {
294 int status;
295 s16 max_claimed_usecs;
296
297 status = 0;
298
299 if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) {
300 /*
301 * High speed mode
302 * Max periodic usecs is 80% x 125 usec = 100 usec
303 */
304 max_claimed_usecs = 100 - qh->usecs;
305 } else {
306 /*
307 * Full speed mode
308 * Max periodic usecs is 90% x 1000 usec = 900 usec
309 */
310 max_claimed_usecs = 900 - qh->usecs;
311 }
312
313 if (hsotg->periodic_usecs > max_claimed_usecs) {
314 dev_err(hsotg->dev,
315 "%s: already claimed usecs %d, required usecs %d\n",
316 __func__, hsotg->periodic_usecs, qh->usecs);
317 status = -ENOSPC;
318 }
319
320 return status;
321 }
322
323 /**
324 * dwc2_check_max_xfer_size() - Checks that the max transfer size allowed in a
325 * host channel is large enough to handle the maximum data transfer in a single
326 * (micro)frame for a periodic transfer
327 *
328 * @hsotg: The HCD state structure for the DWC OTG controller
329 * @qh: QH for a periodic endpoint
330 *
331 * Return: 0 if successful, negative error code otherwise
332 */
dwc2_check_max_xfer_size(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh)333 static int dwc2_check_max_xfer_size(struct dwc2_hsotg *hsotg,
334 struct dwc2_qh *qh)
335 {
336 u32 max_xfer_size;
337 u32 max_channel_xfer_size;
338 int status = 0;
339
340 max_xfer_size = dwc2_max_packet(qh->maxp) * dwc2_hb_mult(qh->maxp);
341 max_channel_xfer_size = hsotg->core_params->max_transfer_size;
342
343 if (max_xfer_size > max_channel_xfer_size) {
344 dev_err(hsotg->dev,
345 "%s: Periodic xfer length %d > max xfer length for channel %d\n",
346 __func__, max_xfer_size, max_channel_xfer_size);
347 status = -ENOSPC;
348 }
349
350 return status;
351 }
352
353 /**
354 * dwc2_schedule_periodic() - Schedules an interrupt or isochronous transfer in
355 * the periodic schedule
356 *
357 * @hsotg: The HCD state structure for the DWC OTG controller
358 * @qh: QH for the periodic transfer. The QH should already contain the
359 * scheduling information.
360 *
361 * Return: 0 if successful, negative error code otherwise
362 */
dwc2_schedule_periodic(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh)363 static int dwc2_schedule_periodic(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
364 {
365 int status;
366
367 status = dwc2_periodic_channel_available(hsotg);
368 if (status) {
369 dev_dbg(hsotg->dev,
370 "%s: No host channel available for periodic transfer\n",
371 __func__);
372 return status;
373 }
374
375 status = dwc2_check_periodic_bandwidth(hsotg, qh);
376 if (status) {
377 dev_dbg(hsotg->dev,
378 "%s: Insufficient periodic bandwidth for periodic transfer\n",
379 __func__);
380 return status;
381 }
382
383 status = dwc2_check_max_xfer_size(hsotg, qh);
384 if (status) {
385 dev_dbg(hsotg->dev,
386 "%s: Channel max transfer size too small for periodic transfer\n",
387 __func__);
388 return status;
389 }
390
391 if (hsotg->core_params->dma_desc_enable > 0)
392 /* Don't rely on SOF and start in ready schedule */
393 list_add_tail(&qh->qh_list_entry, &hsotg->periodic_sched_ready);
394 else
395 /* Always start in inactive schedule */
396 list_add_tail(&qh->qh_list_entry,
397 &hsotg->periodic_sched_inactive);
398
399 /* Reserve periodic channel */
400 hsotg->periodic_channels++;
401
402 /* Update claimed usecs per (micro)frame */
403 hsotg->periodic_usecs += qh->usecs;
404
405 return status;
406 }
407
408 /**
409 * dwc2_deschedule_periodic() - Removes an interrupt or isochronous transfer
410 * from the periodic schedule
411 *
412 * @hsotg: The HCD state structure for the DWC OTG controller
413 * @qh: QH for the periodic transfer
414 */
dwc2_deschedule_periodic(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh)415 static void dwc2_deschedule_periodic(struct dwc2_hsotg *hsotg,
416 struct dwc2_qh *qh)
417 {
418 list_del_init(&qh->qh_list_entry);
419
420 /* Release periodic channel reservation */
421 hsotg->periodic_channels--;
422
423 /* Update claimed usecs per (micro)frame */
424 hsotg->periodic_usecs -= qh->usecs;
425 }
426
427 /**
428 * dwc2_hcd_qh_add() - Adds a QH to either the non periodic or periodic
429 * schedule if it is not already in the schedule. If the QH is already in
430 * the schedule, no action is taken.
431 *
432 * @hsotg: The HCD state structure for the DWC OTG controller
433 * @qh: The QH to add
434 *
435 * Return: 0 if successful, negative error code otherwise
436 */
dwc2_hcd_qh_add(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh)437 int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
438 {
439 int status = 0;
440 u32 intr_mask;
441
442 if (dbg_qh(qh))
443 dev_vdbg(hsotg->dev, "%s()\n", __func__);
444
445 if (!list_empty(&qh->qh_list_entry))
446 /* QH already in a schedule */
447 return status;
448
449 /* Add the new QH to the appropriate schedule */
450 if (dwc2_qh_is_non_per(qh)) {
451 /* Always start in inactive schedule */
452 list_add_tail(&qh->qh_list_entry,
453 &hsotg->non_periodic_sched_inactive);
454 } else {
455 status = dwc2_schedule_periodic(hsotg, qh);
456 if (status == 0) {
457 if (!hsotg->periodic_qh_count) {
458 intr_mask = readl(hsotg->regs + GINTMSK);
459 intr_mask |= GINTSTS_SOF;
460 writel(intr_mask, hsotg->regs + GINTMSK);
461 }
462 hsotg->periodic_qh_count++;
463 }
464 }
465
466 return status;
467 }
468
469 /**
470 * dwc2_hcd_qh_unlink() - Removes a QH from either the non-periodic or periodic
471 * schedule. Memory is not freed.
472 *
473 * @hsotg: The HCD state structure
474 * @qh: QH to remove from schedule
475 */
dwc2_hcd_qh_unlink(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh)476 void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
477 {
478 u32 intr_mask;
479
480 dev_vdbg(hsotg->dev, "%s()\n", __func__);
481
482 if (list_empty(&qh->qh_list_entry))
483 /* QH is not in a schedule */
484 return;
485
486 if (dwc2_qh_is_non_per(qh)) {
487 if (hsotg->non_periodic_qh_ptr == &qh->qh_list_entry)
488 hsotg->non_periodic_qh_ptr =
489 hsotg->non_periodic_qh_ptr->next;
490 list_del_init(&qh->qh_list_entry);
491 } else {
492 dwc2_deschedule_periodic(hsotg, qh);
493 hsotg->periodic_qh_count--;
494 if (!hsotg->periodic_qh_count) {
495 intr_mask = readl(hsotg->regs + GINTMSK);
496 intr_mask &= ~GINTSTS_SOF;
497 writel(intr_mask, hsotg->regs + GINTMSK);
498 }
499 }
500 }
501
502 /*
503 * Schedule the next continuing periodic split transfer
504 */
dwc2_sched_periodic_split(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh,u16 frame_number,int sched_next_periodic_split)505 static void dwc2_sched_periodic_split(struct dwc2_hsotg *hsotg,
506 struct dwc2_qh *qh, u16 frame_number,
507 int sched_next_periodic_split)
508 {
509 u16 incr;
510
511 if (sched_next_periodic_split) {
512 qh->sched_frame = frame_number;
513 incr = dwc2_frame_num_inc(qh->start_split_frame, 1);
514 if (dwc2_frame_num_le(frame_number, incr)) {
515 /*
516 * Allow one frame to elapse after start split
517 * microframe before scheduling complete split, but
518 * DON'T if we are doing the next start split in the
519 * same frame for an ISOC out
520 */
521 if (qh->ep_type != USB_ENDPOINT_XFER_ISOC ||
522 qh->ep_is_in != 0) {
523 qh->sched_frame =
524 dwc2_frame_num_inc(qh->sched_frame, 1);
525 }
526 }
527 } else {
528 qh->sched_frame = dwc2_frame_num_inc(qh->start_split_frame,
529 qh->interval);
530 if (dwc2_frame_num_le(qh->sched_frame, frame_number))
531 qh->sched_frame = frame_number;
532 qh->sched_frame |= 0x7;
533 qh->start_split_frame = qh->sched_frame;
534 }
535 }
536
537 /*
538 * Deactivates a QH. For non-periodic QHs, removes the QH from the active
539 * non-periodic schedule. The QH is added to the inactive non-periodic
540 * schedule if any QTDs are still attached to the QH.
541 *
542 * For periodic QHs, the QH is removed from the periodic queued schedule. If
543 * there are any QTDs still attached to the QH, the QH is added to either the
544 * periodic inactive schedule or the periodic ready schedule and its next
545 * scheduled frame is calculated. The QH is placed in the ready schedule if
546 * the scheduled frame has been reached already. Otherwise it's placed in the
547 * inactive schedule. If there are no QTDs attached to the QH, the QH is
548 * completely removed from the periodic schedule.
549 */
dwc2_hcd_qh_deactivate(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh,int sched_next_periodic_split)550 void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
551 int sched_next_periodic_split)
552 {
553 if (dbg_qh(qh))
554 dev_vdbg(hsotg->dev, "%s()\n", __func__);
555
556 if (dwc2_qh_is_non_per(qh)) {
557 dwc2_hcd_qh_unlink(hsotg, qh);
558 if (!list_empty(&qh->qtd_list))
559 /* Add back to inactive non-periodic schedule */
560 dwc2_hcd_qh_add(hsotg, qh);
561 } else {
562 u16 frame_number = dwc2_hcd_get_frame_number(hsotg);
563
564 if (qh->do_split) {
565 dwc2_sched_periodic_split(hsotg, qh, frame_number,
566 sched_next_periodic_split);
567 } else {
568 qh->sched_frame = dwc2_frame_num_inc(qh->sched_frame,
569 qh->interval);
570 if (dwc2_frame_num_le(qh->sched_frame, frame_number))
571 qh->sched_frame = frame_number;
572 }
573
574 if (list_empty(&qh->qtd_list)) {
575 dwc2_hcd_qh_unlink(hsotg, qh);
576 } else {
577 /*
578 * Remove from periodic_sched_queued and move to
579 * appropriate queue
580 */
581 if (qh->sched_frame == frame_number)
582 list_move(&qh->qh_list_entry,
583 &hsotg->periodic_sched_ready);
584 else
585 list_move(&qh->qh_list_entry,
586 &hsotg->periodic_sched_inactive);
587 }
588 }
589 }
590
591 /**
592 * dwc2_hcd_qtd_init() - Initializes a QTD structure
593 *
594 * @qtd: The QTD to initialize
595 * @urb: The associated URB
596 */
dwc2_hcd_qtd_init(struct dwc2_qtd * qtd,struct dwc2_hcd_urb * urb)597 void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
598 {
599 qtd->urb = urb;
600 if (dwc2_hcd_get_pipe_type(&urb->pipe_info) ==
601 USB_ENDPOINT_XFER_CONTROL) {
602 /*
603 * The only time the QTD data toggle is used is on the data
604 * phase of control transfers. This phase always starts with
605 * DATA1.
606 */
607 qtd->data_toggle = DWC2_HC_PID_DATA1;
608 qtd->control_phase = DWC2_CONTROL_SETUP;
609 }
610
611 /* Start split */
612 qtd->complete_split = 0;
613 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
614 qtd->isoc_split_offset = 0;
615 qtd->in_process = 0;
616
617 /* Store the qtd ptr in the urb to reference the QTD */
618 urb->qtd = qtd;
619 }
620
621 /**
622 * dwc2_hcd_qtd_add() - Adds a QTD to the QTD-list of a QH
623 *
624 * @hsotg: The DWC HCD structure
625 * @qtd: The QTD to add
626 * @qh: Out parameter to return queue head
627 * @atomic_alloc: Flag to do atomic alloc if needed
628 *
629 * Return: 0 if successful, negative error code otherwise
630 *
631 * Finds the correct QH to place the QTD into. If it does not find a QH, it
632 * will create a new QH. If the QH to which the QTD is added is not currently
633 * scheduled, it is placed into the proper schedule based on its EP type.
634 */
dwc2_hcd_qtd_add(struct dwc2_hsotg * hsotg,struct dwc2_qtd * qtd,struct dwc2_qh ** qh,gfp_t mem_flags)635 int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
636 struct dwc2_qh **qh, gfp_t mem_flags)
637 {
638 struct dwc2_hcd_urb *urb = qtd->urb;
639 unsigned long flags;
640 int allocated = 0;
641 int retval = 0;
642
643 /*
644 * Get the QH which holds the QTD-list to insert to. Create QH if it
645 * doesn't exist.
646 */
647 if (*qh == NULL) {
648 *qh = dwc2_hcd_qh_create(hsotg, urb, mem_flags);
649 if (*qh == NULL)
650 return -ENOMEM;
651 allocated = 1;
652 }
653
654 spin_lock_irqsave(&hsotg->lock, flags);
655 retval = dwc2_hcd_qh_add(hsotg, *qh);
656 if (retval && allocated) {
657 struct dwc2_qtd *qtd2, *qtd2_tmp;
658 struct dwc2_qh *qh_tmp = *qh;
659
660 *qh = NULL;
661 dwc2_hcd_qh_unlink(hsotg, qh_tmp);
662
663 /* Free each QTD in the QH's QTD list */
664 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh_tmp->qtd_list,
665 qtd_list_entry)
666 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh_tmp);
667
668 spin_unlock_irqrestore(&hsotg->lock, flags);
669 dwc2_hcd_qh_free(hsotg, qh_tmp);
670 } else {
671 qtd->qh = *qh;
672 list_add_tail(&qtd->qtd_list_entry, &(*qh)->qtd_list);
673 spin_unlock_irqrestore(&hsotg->lock, flags);
674 }
675
676 return retval;
677 }
678